U.S. patent application number 12/488379 was filed with the patent office on 2009-12-24 for system and method for reducing temperature variation during burn in.
Invention is credited to David H. Hoffman, John Laurence Niven, Eric Chen-Li Sheng.
Application Number | 20090316750 12/488379 |
Document ID | / |
Family ID | 34887569 |
Filed Date | 2009-12-24 |
United States Patent
Application |
20090316750 |
Kind Code |
A1 |
Sheng; Eric Chen-Li ; et
al. |
December 24, 2009 |
SYSTEM AND METHOD FOR REDUCING TEMPERATURE VARIATION DURING BURN
IN
Abstract
Systems and methods for reducing temperature variation during
burn-in testing. In one embodiment, power consumed by an integrated
circuit under test is measured. An ambient temperature associated
with the integrated circuit is measured. A desired junction
temperature of the integrated circuit is achieved by adjusting a
body bias voltage of the integrated circuit. By controlling
temperature of individual integrated circuits, temperature
variation during burn-in testing can be reduced.
Inventors: |
Sheng; Eric Chen-Li; (San
Jose, CA) ; Hoffman; David H.; (Sunnyvale, CA)
; Niven; John Laurence; (Livermore, CA) |
Correspondence
Address: |
TRANSMETA C/O MURABITO, HAO & BARNES LLP
TWO NORTH MARKET STREET, THIRD FLOOR
SAN JOSE
CA
95113
US
|
Family ID: |
34887569 |
Appl. No.: |
12/488379 |
Filed: |
June 19, 2009 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
11881006 |
Jul 24, 2007 |
7565259 |
|
|
12488379 |
|
|
|
|
10791099 |
Mar 1, 2004 |
7248988 |
|
|
11881006 |
|
|
|
|
Current U.S.
Class: |
374/152 ;
374/E13.001 |
Current CPC
Class: |
G01K 7/42 20130101; G01R
31/2874 20130101; G01R 31/2879 20130101 |
Class at
Publication: |
374/152 ;
374/E13.001 |
International
Class: |
G01K 13/00 20060101
G01K013/00 |
Claims
1. A method of determining a junction temperature of an integrated
circuit, said method comprising: measuring an ambient temperature
in a region proximate to said integrated circuit; measuring
electrical power utilized by said integrated circuit; accessing a
thermal resistance value for said integrated circuit, wherein said
thermal resistance value is dependent on packaging of said
integrated circuit; and determining a junction temperature of said
integrated circuit by using at least said measured ambient
temperature, said measured power, and said thermal resistance
value.
2. The method of claim 1 wherein said determining comprises
multiplying said thermal resistance value by said measured
electrical power and adding said measured ambient temperature.
3. The method of claim 1 wherein said measuring electrical power
comprises measuring current supplied to said integrated
circuit.
4. The method of claim 1 wherein said measuring electrical power
comprises measuring voltage supplied to said integrated
circuit.
5. The method of claim 1 wherein said thermal resistance value is
accessed from a computer usable media.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This patent application is a Divisional of U.S. patent
application Ser. No. 11/881,006, filed on Jul. 24, 2007, which is a
Continuation of U.S. patent application Ser. No. 10/791,099, filed
on Mar. 1, 2004, now U.S. Pat. No. 7,248,988, which are hereby
incorporated by reference in their entirety. Commonly-owned U.S.
patent application Ser. No. 10/334,272, filed Dec. 31, 2002, now
U.S. Pat. No. 6,936,898, entitled "Diagonal Deep Well Region for
Routing Body-Bias Voltage for MOSFETs in Surface Well Regions" to
Pelham and Burr, is hereby incorporated by reference in its
entirety.
FIELD OF THE INVENTION
[0002] Embodiments relate to systems and methods for reducing
temperature variation during burn in.
BACKGROUND
[0003] Highly integrated semiconductor devices, e.g.,
microprocessors, frequently dissipate a great deal of heat,
particularly when operated at elevated temperatures and voltages to
screen for defects during burn-in operations. Such heat dissipation
is deleterious during burn-in operations, conventionally requiring
complex and expensive heat sinking, e.g., water baths and/or liquid
metal cooling, and expensive test chambers with very high cooling
capacities.
SUMMARY OF THE INVENTION
[0004] Therefore, systems and methods for reducing temperature
variation during burn-in are highly desired.
[0005] Accordingly, systems and methods for reducing temperature
variation during burn-in testing are disclosed. In one embodiment,
power consumed by an integrated circuit under test is measured. An
ambient temperature associated with the integrated circuit is
measured. A desired junction temperature of the integrated circuit
is achieved by adjusting a body bias voltage of the integrated
circuit. By controlling temperature of individual integrated
circuits, temperature variation during burn-in testing can be
reduced.
[0006] In accordance with other embodiments, an ambient temperature
in a region proximate to an integrated circuit is measured.
Electrical power utilized by the integrated circuit is measured. A
thermal resistance value for the integrated circuit is accessed and
a junction temperature of the integrated circuit id determined
without direct measurement of the junction temperature.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 illustrates an exemplary arrangement of integrated
circuit devices configured for a burn-in operation, in accordance
with embodiments.
[0008] FIG. 2 illustrates a flow chart for a computer-implemented
method of reducing power during burn in testing, in accordance with
embodiments.
[0009] FIG. 3 illustrates an exemplary arrangement of integrated
circuit devices configured for a burn-in operation, in accordance
with other embodiments.
[0010] FIG. 4 illustrates a flow chart for a computer-implemented
method of reducing power during burn in testing, in accordance with
embodiments.
[0011] FIG. 5 illustrates a flow chart for a computer-implemented
method of determining a junction temperature of an integrated
circuit, in accordance with embodiments.
DETAILED DESCRIPTION OF THE INVENTION
[0012] In the following detailed description, system and method for
reducing temperature variation during burn in, numerous specific
details are set forth in order to provide a thorough understanding.
However, it will be recognized by one skilled in the art that
embodiments may be practiced without these specific details or with
equivalents thereof. In other instances, well-known methods,
procedures, components, and circuits have not been described in
detail as not to unnecessarily obscure aspects of embodiments.
Notation and Nomenclature
[0013] Some portions of the detailed descriptions which follow
(e.g., processes 200, 400 and 500) are presented in terms of
procedures, steps, logic blocks, processing, and other symbolic
representations of operations on data bits that can be performed on
computer memory. These descriptions and representations are the
means used by those skilled in the data processing arts to most
effectively convey the substance of their work to others skilled in
the art. A procedure, computer executed step, logic block, process,
etc., is here, and generally, conceived to be a self-consistent
sequence of steps or instructions leading to a desired result. The
steps are those requiring physical manipulations of physical
quantities. Usually, though not necessarily, these quantities take
the form of electrical or magnetic signals capable of being stored,
transferred, combined, compared, and otherwise manipulated in a
computer system. It has proven convenient at times, principally for
reasons of common usage, to refer to these signals as bits, values,
elements, symbols, characters, terms, numbers, or the like.
[0014] It should be borne in mind, however, that all of these and
similar terms are to be associated with the appropriate physical
quantities and are merely convenient labels applied to these
quantities. Unless specifically stated otherwise as apparent from
the following discussions, it is appreciated that throughout the
detailed description of embodiments, discussions utilizing terms
such as "storing" or "dividing" or "computing" or "testing" or
"calculating" or "determining" or "storing" or "measuring" or
"adjusting" or "generating" or "performing" or "comparing" or
"synchronizing" or "accessing" or "retrieving" or "conveying" or
"sending" or "resuming" or "installing" or "gathering" or the like,
refer to the action and processes of a computer system, or similar
electronic computing device" that manipulates and transforms data
represented as physical (electronic) quantities within the computer
system's registers and memories into other data similarly
represented as physical quantities within the computer system
memories or registers or other such information storage,
transmission or display devices.
System and Method for Reducing Temperature Variation During Burn
In
[0015] Embodiments are described in the context of design and
operation of integrated semiconductors. More particularly,
embodiments relate to systems and methods for reducing temperature
variation during burn-in testing of integrated circuits. It is
appreciated, however, that elements of embodiments may be utilized
in other areas of semiconductor operation.
[0016] Although the following description of embodiments will focus
on coupling a body-bias voltage to pFETs (or p-type MOSFETS) formed
in surface N-wells via a conductive sub-surface region of N-type
doping when a p-type substrate and an N-well process are utilized,
embodiments are equally applicable to coupling a body-bias voltage
to nFETs (or n-type MOSFETS) formed in surface P-wells via a
conductive sub-surface region of P-type doping when an n-type
substrate and a P-well process are utilized. Consequently,
embodiments are well suited to semiconductors formed in n-type
materials, and such embodiments are considered within the scope of
the disclosure.
[0017] Burn-in operations to detect integrated circuit defects are
generally performed at stressing temperatures, e.g., 150 degrees
Celsius, stressing voltages, e.g., 1.5 times nominal operating
voltage, and at low operating frequencies, usually orders of
magnitude slower than normal operating frequencies. Under these
conditions, leakage current tends to dominate power consumption and
heat production of the integrated circuit device.
[0018] FIG. 1 illustrates an exemplary arrangement 100 of
integrated circuit devices configured for a burn-in operation, in
accordance with embodiments. Arrangement 100 comprises a plurality
of integrated circuit devices under test, 101, 102 through N. The
integrated circuits may be typically arrayed on a printed wiring
board 110, which may include sockets for accepting the integrated
circuit devices under test. Because it is desirable to operate the
integrated circuit devices under test at a stressing elevated
temperature, wiring board 110 is typically placed in a temperature
chamber capable of temperature regulation, e.g., adding or removing
heat, at high temperatures, e.g., 150 degrees Celsius. A typical
burn-in chamber may comprise a plurality of similar wiring
boards.
[0019] Wiring board 110 comprises a distribution network, e.g.,
wiring traces, to conduct electrical signals between various power
supplies, test controllers and/or instrumentation and the
integrated circuit devices under test. Wiring board 110 comprises
an operating voltage (Vdd) supply distribution network 141 and a
test control distribution network 142. It is appreciated that such
wiring networks can be configured in a wide varied of well known
networks, including bus, point-to-point, and individual topologies
in accordance with embodiments.
[0020] Operating voltage supply 140 and test controller 150 are
shown on wiring board 110. Embodiments are well suited to situating
such components elsewhere within a test environment. For example,
operating voltage supply 140 is frequently located outside of a
thermal chamber, and wired to a connector on wiring board 110. Test
control distribution network 142 couples a plurality of signals
between test controller 150 and the integrated circuit devices
under test. Similarly, operating voltage supply distribution
network 141 couples a plurality of signals between operating
voltage supply 140 and the integrated circuit devices under
test.
[0021] A test unit controller, which may or may not be apart of
test controller 150, typically stimulates the integrated circuit
devices under test with a test pattern sequence and/or test
commands and accesses a result. Embodiments are well suited to a
wide variety of test unit controllers and testing methods,
including, for example, Joint Test Action Group (JTAG) boundary
scan and array built-in self test (ABIST).
[0022] Operating voltage supply 140 provides voltage and current to
operate the integrated circuit devices under test, typically at a
stressing voltage, e.g., 1.5 times nominal operating voltage for
the integrated circuit devices under test. Current consumption,
particularly leakage current consumption, in most semiconductors
increases with increasing operating voltage and with increases in
operating temperature. Such current increases are generally
exponential in nature, e.g., a ten percent increase in operating
voltage can cause a 100 percent increase in leakage current
consumption. Operating the integrated circuit devices under test at
a stressing elevated temperature also greatly increases their
current requirements. As a deleterious consequence, operating
voltage supply 140 must have a significantly greater current
capacity to operate the integrated circuit devices under test in
comparison to a current capacity required to operate the same
integrated circuit devices under nominal temperature and voltage
conditions.
[0023] As a typical burn-in configuration can comprise several tens
of integrated circuit devices under test per wiring board 110, and
numerous wiring boards per chamber, the requirements placed upon
operating voltage supply 140 can easily be measured in multiple
kilowatts. A precision voltage supply capable of supplying such
power and suitable for testing integrated circuit devices can be
prohibitively expensive.
[0024] Static power consumption in modern semiconductor processes,
e.g., processes with a minimum feature size of about 0.13 microns
and smaller, is no longer a negligible component of total power
consumption. Further, static power, as a percentage of total power,
is tending to increase with successive generations of semiconductor
process.
[0025] For example, maximum operating frequency is generally
proportional to the quantity (1-Vt/Vdd), that is, one minus the
threshold voltage divided by the supply voltage (for small process
geometries). As process geometry shrinks, supply voltage (Vdd)
typically also is decreased in order to avoid deleterious effects
such as oxide breakdown. Consequently, threshold voltage should
also be decreased in order to maintain or increase a desirable
maximum operating frequency. Correspondingly, gate oxides are made
thinner so that a gate can maintain control of the channel. A
thinner gate oxide leads to an increased gate capacitance. Since
"off" or leakage current of a CMOS device is generally proportional
to gate capacitance, the trend to make gate oxides thinner tends to
increase leakage current. As an unfortunate result, the on-going
decrease in semiconductor process size also leads to an
ever-increasing power consumption deriving from static power
dissipation. Further, essentially all of the electrical energy
provided by operating voltage supply 140 is converted into heat by
the integrated circuit devices under test. As a deleterious effect,
for most highly integrated circuits, the integrated circuits under
test produce more than enough heat to achieve a desired stress
temperature, and the temperature chamber is no longer required to
provide such heat. In sharp contrast, the temperature chamber must
now be capable of removing vast heat loads, contributing to
requirements for a very expensive chamber.
[0026] Further, conducting such vast amounts of heat out of the
integrated circuit die, through the integrated circuit packaging
and into the temperature chamber environment is problematic. Heat
dissipation requirements of highly integrated circuits, e.g.,
microprocessors, generally outpace heat dissipation capabilities of
the integrated circuit packaging under burn-in stress conditions.
Consequently, very expensive "exotic" heat sinking arrangements,
e.g., water baths and liquid metal cooling are conventionally
employed to get the heat out of integrated circuits during burn-in
testing.
[0027] Certain semiconductor devices have beet body biasing well
structures to control power consumption during operation. U.S.
patent application Ser. No. 10/334,272, now U.S. Pat. No.
6,936,898, incorporated herein by reference and referenced above,
describes such devices in more depth. In accordance with
embodiments, such body biasing well structures can be
advantageously utilized during burn-in operations to control
particular parameters of a burn-in process.
[0028] Still referring to FIG. 1, positive bias voltage generator
120 is coupled to positive bias voltage distribution network 121,
which in turn is coupled to the integrated circuits under test.
Positive bias voltage generator 120 provides a body-biasing
voltage, e.g., zero to five volts, to n type wells disposed beneath
pFET devices in the integrated circuit devices under test. Such
body biasing enables adjustment of threshold voltages of the pFET
devices, for example, to reduce leakage current of the pFET
devices.
[0029] In a similar manner, negative bias voltage generator 130 is
coupled to negative bias voltage distribution network 131, which in
turn is coupled to the integrated circuits under test. Negative
bias voltage generator 130 provides a body-biasing voltage, e.g.,
-5 to zero volts, to p type wells disposed beneath nFET devices in
the integrated circuit devices under test. Such body biasing
enables adjustment of threshold voltages of the nFET devices, for
example, to reduce leakage current of the nFET devices.
[0030] It is appreciated that such bias voltage distribution
networks 121 and 131 can be configured in a wide varied of well
known networks, including bus, point-to-point, and individual
topologies in accordance with embodiments. There may be a plurality
of bias generators 120, 130 on wiring board 110, or bias generators
may be located off of wiring board 110, in accordance with
embodiments.
[0031] In general, bias voltage generators 120 and 130 are variable
voltage sources. Their output voltage can be set (within a range)
to a specific value. It is desirable, but not required, that such
specific values be set digitally, e.g., by a command from test
controller 150. Body biasing currents are typically on the order of
low micro amps per integrated circuit. Consequently, bias voltage
generators 120 and 130 generally can be relatively small and
inexpensive voltage sources.
[0032] FIG. 2 illustrates a flow chart for a computer-implemented
method 200 of reducing power during burn in testing, in accordance
with embodiments. In block 210, an integrated circuit device is
tested to determine a set of body bias voltages which minimize
leakage current. In general, the testing will determine a unique n
well voltage and a unique p well voltage for the integrated circuit
device. It is appreciated that integrated circuits with a variety
of power domains and body biasing wells are well suited to
embodiments.
[0033] Advantageously, semiconductor packaging does not affect
leakage current; therefore leakage current may be accurately
measured on an unpackaged device, e.g., on a wafer tester. As a
beneficial consequence, in general, no additional special test
equipment or fixturing is required to perform block 210 within a
typical semiconductor manufacturing process. Body bias voltages
that minimize leakage current will generally be determined outside
of a burn-in process, for example during wafer testing. A set of
body bias voltages that minimize leakage current may be determined
for an entire batch of integrated circuits, e.g., for a wafer or
for multiple wafers processes at the same time. Further,
embodiments are well suited to determining body bias voltages that
minimize leakage current for individual integrated circuits.
[0034] In optional block 220, information of the set of body bias
voltages, e.g., numerical representations of the voltages, is
stored in a computer usable media. As previously described, block
210 and block 240, below, are well suited to being performed on
different test equipment, physically separated, e.g., on different
continents, at different times, e.g., weeks or months apart.
Storing information of the set of body bias voltages enables
transmission and/or retrieval of this information for use over
distances in time and space.
[0035] In optional block 230, information of the set of body bias
voltages is accessed from a computer usable media. In accordance
with embodiments, the computer usable media of block 220 may differ
from the computer usable media of block 230. As is well known in
the data processing arts, information (data) may be copied and/or
transmitted in a variety of ways from media to media. In block 240,
the body bias voltages determined in block 210 are applied to an
integrated circuit during burn-in testing.
[0036] Advantageously, by controlling body bias voltages to
minimize leakage current during burn-in processing, power
consumption and dissipation of the integrated circuits under test
can be reduced by orders of magnitude. As a beneficial consequence
of such greatly reduced power consumption, much less capable and
much less expensive operating voltage supplies and thermal chambers
may be utilized for performing burn-in testing. Alternatively,
greater numbers of integrated circuits can be burned in with
existing equipment, thereby increasing throughput of a burn-in
process. In addition, expensive exotic heat sinking arrangements
conventionally utilized with high function integrated circuits are
no longer required.
[0037] It is desirable to operate each integrated circuit at a
specific junction temperature during burn in, for example 150
degrees Celsius. Unfortunately, there will generally be a
distribution of junction temperatures, "chip temperatures," in a
population of integrated circuits undergoing burn in. For example,
most temperature chambers are unable to maintain a precisely
uniform ambient temperature at all locations within the chamber. In
addition, manufacturing variations among the integrated circuits
under test contribute to differences in power consumption, and
hence differences in heat output between the various integrated
circuits. Consequently, such differences in ambient temperature and
heat output contribute to variations in junction temperatures among
the integrated circuits under test.
[0038] Conventionally, junction temperature variation has been
addressed by mechanical temperature control of each integrated
circuit, e.g., forcing heat into and drawing heat out of each
integrated circuit in order to adjust its junction temperature to
the desired temperature. Unfortunately, such conventional
individual device temperature control is mechanically complex and
expensive. In addition, such structures for externally applied
heating and cooling generally have their own relatively large
thermal mass, which greatly limits their ability to respond to
changes in thermal requirements. Further, the coupling of heating
and cooling, as well as temperature measurements, are generally
made to integrated circuit packaging, rather than directly to
junctions. Consequently, the junction temperature of the integrated
circuit is controlled to an undesirable approximation.
[0039] Relation 1 below is an approximation of junction temperature
of an integrated circuit:
Tjunction=Tambient+P.theta.i (Relation 1)
where T is temperature, P is power consumed by the integrated
circuit. ".theta.i" is the lumped thermal resistance of the
integrated circuit package comprising, for example, a thermal
resistance from the integrated circuit to a coupled heatsink to
ambient and/or a thermal resistance from the integrated circuit to
a circuit board.
[0040] It is to be appreciated that the thermal resistance of the
integrated circuit package, .theta.i, is highly consistent among
similar integrated circuits under test, and can be treated as a
constant herein.
[0041] It is to be further appreciated that a desire of a burn-in
process is to operate the integrated circuits under test at a
specific operating voltage, e.g., 1.5 times nominal operating
voltage. Current requirements of an integrated circuit, in general,
are a function of attributes of that integrated circuit and the
voltage applied. Hence, for a desirable specific operating voltage,
the power consumed by a particular integrated circuit is
essentially fixed for that integrated circuit under the
conventional art.
[0042] Beneficially, however, in accordance with embodiments, power
consumption of an integrated circuit can be adjusted by adjusting
threshold voltage(s) of the integrated circuit, even if operating
voltage of the integrated circuit is held constant. Threshold
voltage(s) can be adjusted by adjusting body-bias voltage(s)
supplied to body-biasing wells disposed beneath active
semiconductors of the integrated circuit. Adjusting threshold
voltage(s) of an integrated circuit can make changes in, e.g.,
increase or decrease, the leakage current of the integrated
circuit, which is a significant component of an integrated
circuit's power consumption, especially during low frequency
operation, for example, during a burn-in process.
[0043] In accordance with an embodiment, junction temperature of an
integrated circuit under test can be controlled by controlling the
power consumed by the integrated circuit. The power consumed by the
integrated circuit operating at a fixed operating voltage can be
controlled by adjusting body biasing voltages to the integrated
circuit, which in turn influence leakage current of the integrated
circuit.
[0044] FIG. 3 illustrates an exemplary arrangement 300 of
integrated circuit devices configured for a burn-in operation, in
accordance with embodiments. Arrangement 300 comprises a plurality
of integrated circuit devices under test, 101, 102 through N. The
integrated circuits are typically arrayed on a printed wiring board
310, which may comprise sockets for accepting the integrated
circuit devices under test. Because it is desirable to operate the
integrated circuit devices under test at a stressing elevated
temperature, wiring board 310 is typically placed in a temperature
chamber capable of temperature regulation, e.g., adding or removing
heat, at high temperatures, e.g., 150 degrees Celsius. A typical
burn-in chamber may comprise a plurality of similar wiring
boards.
[0045] Wiring board 310 comprises an operating voltage supply 340,
which may be similar to operating voltage supply 140. Operating
voltage supply 340 provides voltage and current to integrated
circuit devices under test 101, 102, etc., though current monitors
301, 302, etc. Operating voltage supply 340 is shown on wiring
board 310. Embodiments are well suited to situating such components
elsewhere within a test environment. For example, operating voltage
supply 340 is frequently located outside of a thermal chamber, and
wired to a connector on wiring board 310.
[0046] In accordance with embodiments, test controller 350 provides
significantly more function than test controller 150 (FIG. 1). As
will be discussed in more detail below, test controller 350 is
coupled to voltage supplies, current measurement devices and
ambient temperature sensor(s) in order to measure and control
electrical parameters related to power consumption and temperature
of the integrated circuit devices under test.
[0047] Test controller 350 is desirably located on wiring board
310. However, due to various factors, e.g., the physical size
and/or nature of equipment used to implement test controller 350,
embodiments are well suited to situating test controller 350
components elsewhere within a test environment, e.g., on a separate
wiring board coupled to wiring board 310, or outside of a thermal
chamber. For example, if test controller 350 were implemented as a
workstation computer, it would generally be impractical to place
such a workstation in a thermal chamber due to its size and
operating temperature limits.
[0048] A test unit controller, which may or may not be apart of
test controller 350, typically stimulates the integrated circuit
devices under test with a test pattern sequence and/or test
commands and accesses a result. Embodiments are well suited to a
wide variety of test unit controllers and testing methods,
including, for example, Joint Test Action Group (JTAG) boundary
scan and array built-in self test (ABIST).
[0049] It is to be appreciated that current monitor 301 measures
current supplied to integrated circuit 101, and that current
monitor 302 measures current supplied to integrated circuit 102.
Each current measurement is reported back to test controller 350,
for example via a digital bus. It is appreciated that other wiring
arrangements for reporting individual integrated circuit currents
are well suited to embodiments.
[0050] Test controller 350 is further coupled to operating voltage
supply 340, such that test controller 350 has knowledge of the
operating voltage supplied to each integrated circuit under test.
In general, the operating voltage for each integrated circuit under
test will be the same. However, embodiments are well suited to a
variety of operating voltages for the integrated circuits under
test.
[0051] Each integrated circuit under test is coupled to an
associated positive and/or negative body-bias voltage source. For
example, integrated circuit 101 is coupled to positive body-bias
voltage source 321 and negative body-bias voltage source 331.
Likewise, integrated circuit 102 is coupled to positive body-bias
voltage source 322 and negative body-bias voltage source 332. The
body-bias voltage sources are in turn coupled to, and controlled by
test controller 350.
[0052] With information of the operating voltage and current
supplied to each integrated circuit under test, test controller 350
can determine the power consumed by each integrated circuit under
test. Ambient temperature sensor 360 provides an ambient
temperature measurement to test controller 350. There can be a
plurality of ambient temperature sensors associated with wiring
board 310. For example, one ambient temperature sensor per wiring
board 310 provides a good approximation of the ambient temperature
for integrated circuits under test on wiring board 310.
Alternatively, there could be an ambient temperature sensor
associated with, and in proximity to, each integrated circuit under
test on wiring board 310.
[0053] Advantageously, it is generally less complex and less
expensive to measure ambient temperature than to directly measure
junction temperature of the integrated circuits under test. The
number of ambient temperature sensors utilized can be adjusted
based upon cost constraints, accuracy requirements and
understanding of thermal variations within a particular
chamber.
[0054] With information of power consumed by each integrated
circuit under test and ambient temperature, the junction
temperature of each integrated circuit under test can be determined
using Relation 1, above. If the computed junction temperature is
not the desired junction temperature, test controller 350 can
adjust the positive and/or negative body biases of each integrated
circuit under test to increase or decrease threshold voltage, and
thus leakage current, and consequently power consumption and in
turn to achieve the desired junction temperature.
[0055] FIG. 4 illustrates a flow chart for a computer-implemented
method 400 of reducing power during burn in testing, in accordance
with embodiments. In block 410, power consumed by an integrated
circuit during a test process is measured. For example, current and
voltage to the integrated circuit can be measured.
[0056] In block 420, an ambient temperature associated with the
integrated circuit is measured. The ambient temperature should be
more closely associated with the integrated circuit than a "set
point" of a temperature chamber. For example, the ambient
temperature can be measured by a single ambient temperature sensor
on a wiring board, e.g., wiring board 310 of FIG. 3, comprising an
array of integrated circuits. Alternatively, the ambient
temperature can be measured by an ambient temperature sensor in
close proximity to the integrated circuit.
[0057] In block 430, a body bias voltage of the integrated circuit
is adjusted to achieve a desired junction temperature of the
integrated circuit. It is to be appreciated that body-biasing
voltage can affect threshold voltages, which in turn affect leakage
current which is a significant component of integrated circuit
power consumption. By adjusting, e.g., increasing or decreasing,
integrated circuit power consumption, the junction temperature of
an integrated circuit can be directly manipulated. In combination
with information of an ambient temperature of the integrated
circuit, a desired junction temperature can be achieved.
[0058] In this novel manner, a junction temperature of an
integrated circuit can be controlled without directly measuring the
junction temperature of the integrated circuit. It is generally
less complex and less expensive to measure ambient temperature than
to directly measure junction temperature of an integrated circuit.
Further, systems to measure power and control low current voltages
are typically less complex and less expensive than creating
individual thermal environments for large numbers of integrated
circuits. As a beneficial result, embodiments reduce temperature
variation during burn in with much less cost, much less complexity
and with greater reliability than the conventional practice.
[0059] FIG. 5 illustrates a flow chart for a computer-implemented
method 500 of determining a junction temperature of an integrated
circuit, in accordance with embodiments. In block 510, an ambient
temperature in a region proximate to the integrated circuit is
measured. The ambient temperature sensing device should be in the
same thermal conditions as the integrated circuit.
[0060] In block 520, electrical power utilized by the integrated
circuit is measured. Typically, such measurement is performed by
measuring voltage and current supplied to the integrated
circuit.
[0061] In block 530, a thermal resistance value for the integrated
circuit is accessed, for example, from computer memory. The thermal
resistance value can be determined from packaging design
information, but is typically measured during development of the
integrated circuit and its packaging.
[0062] In block 540, a junction temperature of the integrated
circuit is determined. For example, using power, ambient
temperature and thermal resistance, junction temperature can be
computed using Relation 1, above.
[0063] In this novel manner, a junction temperature of an
integrated circuit can be determined without directly measuring the
junction temperature of the integrated circuit. It is generally
less complex and less expensive to measure ambient temperature than
to directly measure junction temperature of an integrated circuit.
Further, power utilized by an integrated circuit can be measured in
a straightforward manner. Beneficially, embodiments determine a
junction temperature of an integrated circuit in a less costly and
less complex manner than under the conventional art.
[0064] In accordance with embodiments, system and method for
reducing temperature variation during burn in, are thus described.
While the detailed description has been described in particular
embodiments, it should be appreciated that the scope of this
disclosure should not be construed as limited by such embodiments,
but rather construed according to the below claims.
* * * * *