U.S. patent application number 12/542316 was filed with the patent office on 2009-12-17 for method and device of measuring interface trap density in semiconductor device.
Invention is credited to Jong Kyu SONG.
Application Number | 20090309624 12/542316 |
Document ID | / |
Family ID | 38106491 |
Filed Date | 2009-12-17 |
United States Patent
Application |
20090309624 |
Kind Code |
A1 |
SONG; Jong Kyu |
December 17, 2009 |
Method and Device of Measuring Interface Trap Density in
Semiconductor Device
Abstract
A method is provided for measuring interface trap density in a
semiconductor device. In the method, measurement parameters are
input to a host computer. A pulse condition is set at a pulse
generator using the measurement parameters. A pulse of a
predetermined frequency generated by the pulse generator is applied
to a gate of a transistor, and a charge pumping current is measured
from a bulk of the transistor. A charge pumping current measurement
may be repeated for a plurality of frequencies while changing the
frequency until a set frequency is reached. A pure charge pumping
current is calculated for each frequency where a gate tunneling
leakage current is removed from the charge pumping current measured
for each frequency. Interface trap density is calculated from the
calculated pure charge pumping current for each frequency.
Inventors: |
SONG; Jong Kyu; (Seoul,
KR) |
Correspondence
Address: |
THE LAW OFFICES OF ANDREW D. FORTNEY, PH.D., P.C.
215 W FALLBROOK AVE SUITE 203
FRESNO
CA
93711
US
|
Family ID: |
38106491 |
Appl. No.: |
12/542316 |
Filed: |
August 17, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11646806 |
Dec 27, 2006 |
7592828 |
|
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12542316 |
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Current U.S.
Class: |
324/762.05 ;
438/17; 702/117 |
Current CPC
Class: |
G01R 31/2648
20130101 |
Class at
Publication: |
324/765 ; 438/17;
702/117 |
International
Class: |
G01R 31/28 20060101
G01R031/28; H01L 21/66 20060101 H01L021/66; G06F 19/00 20060101
G06F019/00 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 30, 2005 |
KR |
10-2005-0134764 |
Claims
1. A device for measuring interface trap density, the device
comprising: a pulse generator configured to generate a pulse of a
predetermined frequency, wherein the pulse is applied to an object
wafer; and an amperemeter configured to measure a charge pumping
current from the object wafer.
2. The device of claim 1, further comprising a host computer
configured to receive at least one measurement parameter required
for measurement, and wherein the pulse generator is configured to
generate the pulse in accordance with the at least one measurement
parameter.
3. The device according to claim 2, further comprising a selector
which controls the pulse generated at the pulse generator.
4. The device according to claim 1, wherein the wafer has a
transistor comprising a gate, a grounded source/drain, and a bulk,
and wherein the pulse is applied to the gate and the amperemeter is
connected to the bulk.
5. The device according to claim 4, wherein the pulse has a fixed
base voltage.
6. The device according to claim 4, the transistor further
comprising a gate channel, wherein the gate channel operates
between an accumulation state and an inversion state to generate
the charge pumping current (I.sub.cp).
7. The device according to claim 4, wherein the pulse generated
from the pulse generator comprises a fixed low level gate voltage
and an increasing high level gate voltage.
Description
[0001] This application is a divisional of co-pending U.S. patent
application Ser. No. 11/646,806, filed Dec. 27, 2006 (Attorney
Docket No. SPO200611-0001US), which is incorporated herein by
reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a method and device for
measuring interface trap density in a semiconductor device.
[0004] 2. Description of the Related Art
[0005] As a semiconductor technology develops constantly, the
length of gates gradually become shorter and the thickness of gate
oxide layers gradually become thinner. Accordingly, characteristics
of semiconductor devices are inevitably affected by these smaller
dimensions. One of the characteristics affected is the interface
trap density between a silicon substrate and a gate oxide
layer.
[0006] Generally, when a gate oxide layer is grown, a sufficient
bonding is not made between a silicon atom and an oxygen atom, so
that a dangling bond (where there are insufficient oxygen atoms) is
generated at an interface between a silicon substrate and the gate
oxide layer.
[0007] A dangling bond easily attracts an electron when a
transistor operates, thereby increasing the interface trap density
of the gate oxide layer. Accordingly, the quality of the gate oxide
layer deteriorates or the driving current is reduced, which may
degrade some characteristics of a semiconductor device.
[0008] Traditionally, a charge pumping test has been used as a
method for measuring a surface state located under a gate oxide
layer. The interface trap density may be calculated from data
obtained using this test. However, when the conventional method is
applied to a device having a very thin gate oxide layer, gate
tunneling leakage current and/or quantum mechanical effects can
result in an incorrect calculation of the interface trap density
(generally resulting in a calculated interface trap density that is
too high).
SUMMARY OF THE INVENTION
[0009] Accordingly, the present invention is directed to a method
and device for measuring interface trap density in a semiconductor
device that substantially obviates one or more problems due to
limitations and disadvantages of the related art.
[0010] An object of the present invention is to more accurately
measure and calculate interface trap density in a semiconductor
device having a thin gate oxide layer.
[0011] Additional advantages, objects, and features of the
invention will be set forth in part in the description which
follows and in part will become apparent to those having ordinary
skill in the art upon examination of the following or may be
learned from practice of the invention. The objectives and other
advantages of the invention may be realized and attained by the
structure particularly pointed out in the written description and
claims hereof as well as the appended drawings.
[0012] To achieve these objects and other advantages and in
accordance with the purpose of the invention, as embodied and
broadly described herein, there is provided a method for measuring
interface trap density, the method including: inputting measurement
parameters to a host computer; setting a pulse condition at a pulse
generator using the measurement parameters; applying a pulse of a
predetermined frequency generated by the pulse generator to a gate
of a transistor; measuring a charge pumping current from a bulk of
the transistor; repeating a charge pumping current measurement for
a plurality of frequencies while changing a frequency until a set
frequency is reached; calculating a pure charge pumping current for
each frequency where a gate tunneling leakage current is removed
from the charge pumping current measured for each frequency; and
calculating interface trap density from the calculated pure charge
pumping current for each frequency.
[0013] Also, there is provided a device for measuring interface
trap density, the device including: a host computer to input
measurement parameters; a pulse generator to generate a pulse of a
predetermined frequency by using the measurement parameters,
wherein the pulse is applied to an object wafer; and an amperemeter
to measure a charge pumping current from the object wafer.
[0014] It is to be understood that both the foregoing general
description and the following detailed description of the present
invention are exemplary and explanatory and are intended to provide
further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings, which are included to provide a
further understanding of the invention and are incorporated in and
constitute a part of this application, illustrate embodiment(s) of
the invention and together with the description serve to explain
the principle of the invention. In the drawings:
[0016] FIG. 1 is a view illustrating an apparatus for measuring a
charge pumping current according to an embodiment of the present
invention;
[0017] FIG. 2 is a graph illustrating a charge pumping current
versus a high level gate voltage for each frequency according to an
embodiment of the present invention; and
[0018] FIG. 3 is a graph illustrating interface trap density versus
a pulse frequency according to an embodiment of the present
invention.
DETAILED DESCRIPTION OF THE INVENTION
[0019] Reference will now be made in detail to the preferred
embodiments of the present invention, examples of which are
illustrated in the accompanying drawings.
[0020] FIG. 1 is a view illustrating a construction of an apparatus
for measuring a charge pumping current according to an embodiment
of the present invention.
[0021] Referring to FIG. 1, a pulse 16 having a fixed base voltage
is applied to a gate 12 of a transistor in wafer 10, with
source/drain 11 of the transistor grounded, and an amperemeter 17
in a measuring apparatus connected to a bulk 13 (also called a body
or a base) of the transistor. Accordingly, a gate channel of the
transistor operates between an accumulation state and an inversion
state to generate the charge pumping current (I.sub.cp). This
current is measured from the bulk 13 (e.g. by amperemeter 17).
[0022] The pulse 16 has a fixed low level gate voltage (i.e., a
base voltage) and an increasing high level gate voltage (i.e., a
peak voltage). The pulse 16 is generated at a pulse generator 14
(e.g., HP8110A). A selector 15 (e.g., HP16440A) controls the pulse
16 generated at the pulse generator 14 and applies the pulse 16 for
a predetermined time for measurement. That is, the selector 15
serves as a switch. Meanwhile, though not shown in the drawing, a
probe station on which the wafer 10 is put, and a host computer
responsible for an overall control are also parts of the measuring
apparatus.
[0023] Hereinafter, a method for measuring interface trap density
will be described.
[0024] First, measurement parameters may be input to the host
computer. Examples of the measurement parameters include a width
and a length of a gate (i.e., an area of a gate), a base voltage of
a pulse, an initial peak voltage of a pulse, a final peak voltage
of a pulse, a pulse frequency, and/or a pulse width. Pulse
generator 14 may be configured with a pulse condition according to
the measurement parameters as input to the host computer. In a
preferred embodiment, the pulse condition includes a predetermined
value of a pulse frequency.
[0025] The pulse 16 of the predetermined frequency is generated by
the pulse generator 14. The selector 15 is operated to apply the
pulse 16 of the predetermined frequency to the gate 12. After a
charge pumping current I.sub.cp is measured from the bulk 13, the
selector 15 is stopped. The measurement of a charge pumping current
is repeatedly performed for each frequency. A pulse frequency to be
measured may be set in advance (e.g., by configuring the
measurement parameters). In one embodiment, the measurement of a
charge pumping current may be repeated while the pulse frequency is
changed until a set frequency is reached. Measurement values of a
charge pumping current may be obtained for a plurality of
frequencies in this manner.
[0026] The measured charge pumping current value generally includes
a gate tunneling leakage current. Therefore, a "pure" charge
pumping current for each frequency may be calculated according to
Equation 1 below.
I.sub.cp(f.sub.2)-I.sub.cp(f.sub.1)=[I.sub.cp0(f.sub.2)+I.sub.tunneling]-
-[I.sub.cp0(f.sub.1)+I.sub.tunneling]=I.sub.cp0(f.sub.2-f.sub.1),
Equation 1
where I.sub.cp(f.sub.1) and I.sub.cp(f.sub.2) are charge pumping
currents measured for a first frequency and a second frequency,
respectively, I.sub.tunneling is a leakage current, and
I.sub.cp0(f.sub.1) and I.sub.cp0(f.sub.2) are pure charge pumping
currents for the first and second frequencies, respectively, where
an influence of a leakage current has been removed.
[0027] A pure charge pumping current is calculated by measuring
charge pumping currents at two frequencies, respectively, and
subtracting according to Equation 1. For example, a pure charge
pumping current value at a frequency of 1 MHz (e.g., a where a
tunneling current has been removed) may be obtained by subtracting
a charge pumping current value measured at a frequency of 1 MHz
from a charge pumping current value measured at a frequency of 2
MHz. The reason this calculation Equation 1 is possible is that a
charge pumping current is in proportion to a frequency, while the
tunneling current is generally constant.
[0028] Charge pumping currents for each frequency calculated in
this manner are illustrated in FIG. 2.
[0029] FIG. 2 is a graph illustrating a charge pumping current
versus a high level gate voltage for a plurality of frequencies
according to an embodiment of the present invention.
[0030] The interface trap density may be calculated from the "pure"
charge pumping current according to Equation 2 below.
N it = I cp f .times. A g .times. q , Equation 2 ##EQU00001##
where N.sub.it is the interface trap density, I.sub.cp is the
calculated pure charge pumping current, f is the frequency at which
the charge pumping current was measured, A.sub.g is an area of a
gate, and q is an amount of charge.
[0031] FIG. 3 illustrates interface trap densities calculating
according to Equation 2 for a plurality of frequencies.
[0032] FIG. 3 demonstrates that the interface trap density
calculated according the present invention is generally constant
even when the pulse frequency changes. In contrast, when
conventional measuring methods are applied to a transistor with a
thin gate oxide layer, the calculated interface trap density may
erroneously increase as the frequency decreases. In some cases,
measurement of the interface trap density for transistors with
thing gate oxide films may be impossible. On the other hand, the
present invention can obtain an accurate result value regardless of
the pulse frequency as illustrated in FIG. 3.
[0033] As described above, the present invention can obtain
accurate data of high reliability when measuring and calculating
interface trap density in a semiconductor device having a thin gate
oxide layer.
[0034] It will be apparent to those skilled in the art that various
modifications and variations can be made in the present invention.
Thus, it is intended that the present invention covers the
modifications and variations of this invention provided they come
within the scope of the appended claims and their equivalents.
* * * * *