U.S. patent application number 12/457586 was filed with the patent office on 2009-12-03 for method of fabricating poly-crystalline silicon thin film and method of fabricating transistor using the same.
Invention is credited to Se-young Cho, Min-koo Han, Sang-myeon Han, Ji-sim Jung, Do-young Kim, Jang-yeon Kwon, Min-cheol Lee, Takashi Noguchi, Kyung-bae Park, Young-soo Park.
Application Number | 20090298268 12/457586 |
Document ID | / |
Family ID | 34737861 |
Filed Date | 2009-12-03 |
United States Patent
Application |
20090298268 |
Kind Code |
A1 |
Kwon; Jang-yeon ; et
al. |
December 3, 2009 |
Method of fabricating poly-crystalline silicon thin film and method
of fabricating transistor using the same
Abstract
A method of fabricating a poly-Si thin film and a method of
fabricating a poly-Si TFT using the same are provided. The poly-Si
thin film is formed at a low temperature using ICP-CVD. After the
ICP-CVD, ELA is performed while increasing energy by predetermined
steps. A poly-Si active layer and a Si0.sub.2 gate insulating layer
are deposited at a temperature of about 150.degree. C. using
ICP-CVD. The poly-Si has a large grain size of about 3000 A or
more. An interface trap density of the Si02 can be as high as
lo.sup..parallel./cm.sup.2. A transistor having good electrical
characteristics can be fabricated at a low temperature and thus can
be formed on a heat tolerant plastic substrate.
Inventors: |
Kwon; Jang-yeon; (Seoul,
KR) ; Han; Min-koo; (Seoul, KR) ; Cho;
Se-young; (Seoul, KR) ; Park; Kyung-bae;
(Seoul, KR) ; Kim; Do-young; (Gyeonggi-do, KR)
; Lee; Min-cheol; (Seoul, KR) ; Han;
Sang-myeon; (Seoul, KR) ; Noguchi; Takashi;
(Gyeonggi-do, KR) ; Park; Young-soo; (Gyeonggi-do,
KR) ; Jung; Ji-sim; (Incheon-si, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Family ID: |
34737861 |
Appl. No.: |
12/457586 |
Filed: |
June 16, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11003326 |
Dec 6, 2004 |
7563659 |
|
|
12457586 |
|
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Current U.S.
Class: |
438/479 ;
257/E21.101; 257/E21.412 |
Current CPC
Class: |
H01L 29/78675 20130101;
H01L 21/02164 20130101; H01L 21/02595 20130101; H01L 21/02686
20130101; H01L 21/31608 20130101; H01L 21/02274 20130101; H01L
29/4908 20130101; H01L 29/66757 20130101; H01L 21/0262 20130101;
H01L 21/02354 20130101; H01L 21/02532 20130101; H01L 21/2026
20130101 |
Class at
Publication: |
438/479 ;
257/E21.101; 257/E21.412 |
International
Class: |
H01L 21/336 20060101
H01L021/336; H01L 21/205 20060101 H01L021/205 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 6, 2003 |
KR |
2003-88423 |
Claims
1. A method of fabricating a TFT which comprises a substrate, a
poly-Si active layer formed on the substrate, a gate insulating
layer formed on the poly-Si active layer, and a gate formed on the
gate insulating layer, the method comprising depositing a silicon
thin film on the substrate by ICP-CVD using a diluted He.
2. The method of claim 1, wherein the gate insulating layer is
formed by ICP-CVD.
3. The method of claim 1, further comprising: annealing at least
one of the silicon thin film and the gate insulating layer using
excimer laser annealing (ELA).
4. The method of claim 3, wherein the ELA is performed while
increasing energy by predetermined steps.
5. The method of claim 1, wherein the diluted He is an He/SiH4
composition and a ratio of He to SiH4 is in a range from 6 to
12.
6. The method of claim 1, wherein a deposition ratio of silicon by
the ICP-CVD is 2.8 A/sec.
Description
[0001] This is a divisional of and claims priority under 35 U.S.C.
.sctn. 120 to, U.S. application Ser. No. 11/003,326, filed Dec. 6,
2004 which claims priority under 35 U.S.C. .sctn. 119 to Korean
Patent Application No. 2003-88423, filed on Dec. 6, 2003, in the
Korean Intellectual Property Office, the disclosure of which is
incorporated herein in its entirety by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a method of fabricating
poly-Si thin film and a method of fabricating a transistor using
the same, and more particularly, to a method of fabricating a
poly-Si thin film having high mobility and a method of fabricating
a transistor using the same.
[0004] 2. Description of the Related Art
[0005] Poly-crystalline silicon (poly-Si) is applied to a variety
of electronic devices such as flat panel displays and solar cells
because it has greater mobility than amorphous silicon (a-Si).
Generally, poly-Si electronic devices are formed on a substrate of
a heat resistant material, such as glass. A method of fabricating a
poly-Si electronic device on a plastic substrate has been recently
developed. In order to prevent thermal deformations in the
electronic device, it is necessary to use a low temperature layer
forming process in which a poly-Si electronic device is formed at a
low temperature. Such a low temperature process is required in
order to prevent thermal shock to a substrate and to suppress
process defects that occur at a high temperature in the fabrication
process.
[0006] The use of a plastic substrate for a flat panel display has
been developed because the plastic substrate is lightweight,
flexible and firm.
[0007] A poly-Si thin film transistor (TFT) can be formed on a
plastic substrate. However, such a poly-Si TFT must be fabricated
at a low temperature because a plastic substrate is heat
intolerant.
[0008] For example, a method of depositing a material at a
temperature of about 400.degree. C. cannot be applied to the
plastic substrate, which is thermally deformed at a temperature of
200.degree. C. Methods proposed by Y. J Tung et. al and S. D.
Theiss et. al cannot obtain a poly-Si thin film having a large
grain size when using a process temperature below 200.degree. C.
and a silicon dioxide having a flat-band voltage close to 0 V. (Y.
J Tung, X. Meng. T. J. King. P. G. Carey, P. M. Smith, S. D.
Theiss, R. Weiss, G. A. Davis V. Aebi, Tech, Digest of SID98, pp.
887-890; D. D. Theiss, P. G. Carey, P. M. Smith, P. Wickboldt, T.
W. Sigmon, Y. J. Tung, T. J King, IEDM 98, pp. 257-260)
[0009] A conventional poly-Si fabricating method uses chemical
vapor deposition (CVD) or plasma enhanced CVD (PECVD). In such a
deposition method, a-Si is deposited and then a poly-Si is obtained
by annealing the a-Si. Thus, such a conventional method is
necessarily accompanied with an annealing process in order to
obtain the poly-Si.
SUMMARY OF THE INVENTION
[0010] The present invention provides a method of fabricating a
poly-Si thin film and a method of fabricating a TFT using the same,
in which a poly-Si having a large grain size can be formed without
depending on an annealing.
[0011] Also, the present invention provides a method of fabricating
a poly-Si thin film with high electron mobility and a method of
fabricating a TFT using the same. Further, the present invention
provides a method of fabricating at a low temperature a poly-Si TFT
having a poly-Si layer having a large grain size and a gate
insulating layer having a low flat-band voltage.
[0012] According to an aspect of the present invention, a method of
fabricating a poly-Si thin film includes a forming of a silicon
thin film on a substrate through ICP-CVD using a diluted He. In
another aspect of the present invention, there is provided a method
of fabricating a TFT, which includes a substrate, a poly-Si active
layer formed on the substrate, a gate insulating layer formed on
the poly-Si active layer, and a gate formed on the gate insulating
layer, wherein the method includes depositing a silicon thin film
on the substrate by ICP-CVD using a diluted He.
[0013] The diluted He may be an He/SiH4 composition and a ratio of
He to SiH4 may be in a range from 6 to 12, preferably 1.about.,''
that is, 20:2. A deposition ratio of silicon by the ICP-CVD may be
2.8 A/sec. The poly-Si can be annealed using ELA, thereby
increasing Si grain size. The ELA is performed while increasing
energy by predetermined steps. In the method of fabricating the
TFT, ICP-CVD is used to form the gate insulating layer, and an
annealing can be performed on the gate insulating layer. Also, ELA
is used to anneal the gate insulating layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The above and other features and advantages of the present
invention will become more apparent by describing in detail
exemplary embodiments thereof with reference to the attached
drawings in which:
[0015] FIG. 1 is a graph illustrating a Raman spectrum of a silicon
film according to an embodiment of the present invention;
[0016] FIG. 2 is an FT-IR spectrum of a silicon thin film grown at
a low temperature of 150.degree. C. using ICP-CVD;
[0017] FIG. 3 is a SEM photograph illustrating a poly-Si thin film
annealed using ELA according to an embodiment of the present
invention;
[0018] FIG. 4 illustrates a section of a poly-Si thin film
recrystallized by ELA;
[0019] FIG. 5 is a graph illustrating a breakdown field of a gate
insulating layer when RF power is 200 W, 400 W and 600 W;
[0020] FIG. 6 is a graph illustrating C-V characteristic (measured
with an LCR meter at 1 MHz) of an Si02 thin film formed by
ICP-CVD;
[0021] FIG. 7 is a graph illustrating C-V characteristic (measured
with an LCR meter at 1 MHz) of two Si02 thin films;
[0022] FIG. 8 is a graph illustrating C-V characteristic of an Si02
thin film before ELA and after ELA;
[0023] FIG. 9 is a flowchart illustrating a method of fabricating a
TFT according to an embodiment of the present invention;
[0024] FIG. 10 is a graph illustrating electrical characteristics
of a poly-Si TFT according to an embodiment of the present
invention; and
[0025] FIG. 11 is a graph illustrating a drain current with respect
to a drain bias when a gate-source voltage (VAS) of a TFT according
to an embodiment of the present invention is 1 V, 3 V and 5V.
DETAILED DESCRIPTION OF THE INVENTION
[0026] Hereinafter, a method of fabricating a poly-Si thin film and
a method of fabricating a TFT using the same according to the
present invention will be described in detail with reference to the
accompanying drawings.
1. Deposition of Silicon Thin Film
[0027] High density plasma generated by inductively coupled plasma
chemical vapor deposition (ICP-CVD) has a high deposition ratio.
ICP-CVD uses remote plasma, which can reduce ion damage in a
film-growth zone.
[0028] An active layer of a poly-Si TFT is formed by the ICP-CVD.
At this time, He/SiH4 gas diluted with He can be used. Also, a
substrate temperature of 150.degree. C. and a pressure of 22 mTorr
are maintained. A ratio of He to SiH4 is 10, that is, 20:2 [sccm],
and a deposition ratio is 2.8 A/sec.
[0029] FIG. 1 is a graph illustrating a Raman spectrum of a
deposited silicon film. Referring to FIG. 1, it can be seen that
the silicon film has a crystal structure, as indicated by a
dominant peak of 520 cm.sup.-1. An amorphous/intermediate phase is
observed in the deposited silicon film. About 60% crystal volume
fraction and crystal component are obtained. The successful
formation of the poly-Si film may be due to a reduction of ion
bombardment in a film-growth zone, in which strong ions can
obstruct crystal growth.
[0030] If hydrogen dilution is used when forming the silicon thin
film, the concentration of hydrogen in the silicon thin film can
reach 10-12%. However, due to high hydrogen concentration, an
explosive effusion phenomenon of hydrogen occurs during excimer
laser annealing (ELA). Therefore, it is necessary to reduce the
hydrogen concentration. Referring to FIG. 2, the hydrogen
concentration of the silicon film formed using the hydrogen
dilution is calculated using FT-IR. Most of the hydrogen is in the
form of dihydrides, that is, Si-H2 (2090 cm.sup.-1), and some of
the hydrogen is in the form of a monohydride, that is, Si-H.
However, the total hydrogen concentration is merely 4%. Such a
reduction of the hydrogen concentration is caused by an inert gas,
He, which reduces an energy barrier of a surface reaction.
2. Annealing Using ELA
[0031] The present embodiment involves the use of ELA instead of a
furnace. The silicon thin film formed using the ICP-CVD is annealed
by an XeCl (X=308 nm) excimer laser. In order to prevent an abrupt
effusion of hydrogen, excimer laser irradiation increases stepwise
from a low energy density (100 mJ/cm.sup.2) to a high energy
density (200 mJ/cm.sup.2). An energy density increment is 10
mJ/cm.sup.2 and thus the energy density can increase 10 steps from
100 mJ/cm.sup.2.
[0032] By increasing the energy density of excimer laser stepwise,
dehydrogenation in the silicon thin film is progressed and
recrystallization of silicon is progressed at the same time. FIG. 3
is a SEM photograph of an 800 A-thick poly-Si thin film with large
grains produced by the above-described ELA. Referring to FIG. 3,
the poly-Si obtained by the ICP-CVD is recrystallized with a larger
grain size by the ELA. FIG. 4 illustrates a section of the poly-Si
thin film recrystallized by the ELA. It can be observed in FIG. 4
that the poly-Si is sufficiently recrystallized and a grain
boundary formed by the ELA is clear.
[0033] The above two processes, that is, the deposition of the
silicon thin film using the ICP-CVD and the annealing using the
ELA, are associated with methods of fabricating a poly-Si thin film
according to an embodiment of the present invention.
[0034] Processes described below are performed before the above two
processes and are related to a method of fabricating a TFT, which
is widely used as a dynamic switching device.
3. Deposition of Gate Insulating Layer
[0035] In order to fabricate a TFT that uses the above-described
poly-Si as an active layer, an Si02 thin film is formed on the
poly-Si as a gate insulating layer by ICP-CVD using He gas, N20 gas
and SiH4 gas. At this time, a substrate temperature is maintained
at 150.degree. C. and a process pressure is set to 30 mTorr. A
contents ratio of He:N20:SIH4 is 100:20:5 [sccm].
[0036] FIG. 5 is a graph illustrating a breakdown field of the gate
insulating layer when RF power is 200 W, 400 W and 600 W. Referring
to FIG. 5, when the RF power is 400 W, a breakdown field is 6.2
MV/cm. Also, it can be seen that the breakdown field advantageously
increases as the RF power increases.
[0037] FIG. 6 is a graph illustrating C-V characteristic of the
Si02 thin film formed by ICP-CVD. The C-V characteristics were
measured with an LCR meter at 1 MHz. FIG. 6 illustrates the
characteristics of gate insulating layers deposited with RF powers
of 400 W, 450 W and 500 W under a process pressure of 25 mTorr, and
with a contents ratio of He:N20:SiH4 is 100:20:5 [sccm].
[0038] Referring to FIG. 6, a flat-band voltage is below -5 V due
to charges existing in the Si02 thin film and its surface. As the
RF power is increased, the flat-band voltage is shifted in a
negative direction. The charges that exist in the interface and the
Si0.sub.2 thin film are reduced as the RF power is reduced. An
effective density of an interface trap is on the order of
lo.sup..parallel./cm.sup.2. FIG. 7 is a graph illustrating C-V
characteristic (measured with an LCR meter at 1 MHz) of two
Si0.sub.2 thin films. A first Si0.sub.2 thin film (initial) is
deposited under conditions of 400 W of RF power, a contents ratio
of He:N20:SiH4=100:20:5, and a process pressure of 25 mTorr. A
second Si02 thin film is annealed on a hot plate at a temperature
of 200.degree. C. and 400.degree. C. Referring to FIG. 7, as the
annealing temperature is increased, the flat-band voltage and the
C-V characteristic are improved. Also, an interface trap density is
remarkably improved. In other words, the annealing of the Si02 thin
film used as the gate insulating layer is required in order to
obtain an excellent poly-Si TFT. However, if the substrate for the
TFT is composed of a plastic material, not a glass substrate, the
temperature of the annealing must be properly adjusted in order to
prevent the substrate from being deformed due to the heat generated
during the annealing of the Si0.sub.2 thin film.
[0039] Through various attempts to effectively anneal the Si02 thin
film and prevent thermal deformation of the plastic substrate, a
good result has been obtained by annealing the Si02 thin film using
ELA. For convenience, the Si02 thin film is deposited on a silicon
wafer under the above-described conditions using ICP-CVD, and then
the ELA is performed. Consequently, a Si02 thin film having
excellent C-V characteristic is obtained, as indicated by FIG.
8.
[0040] FIG. 8 is a graph illustrating the C-V characteristic of the
Si02 thin film before ELA and after ELA. During the ELA, 20 shots
of the laser were irradiated with an energy density of 430
mJ/cm.sup.2. As a result, the flat-band voltage shifted by +1.4 V.
Therefore, the charges existing in the interface or the Si02 thin
film were reduced.
4. Brief Description of Entire Process of Fabricating TFT
[0041] The above three processes are the most important processes
in TFT fabrication. The other processes are performed using
conventional methods. These methods will now be briefly
described.
[0042] In the TFT fabrication method according to an embodiment of
the present invention, a poly-Si film and a Si02 film are
fabricated at a low temperature of 150.degree. C.
[0043] Therefore, a TFT having excellent characteristics can be
obtained on a heat tolerant substrate, for example a plastic
substrate. In other words, the plastic can be used as the TFT
substrate.
[0044] Referring to FIG. 9, first, Si is deposited on the
substrate, which may be a glass substrate or plastic substrate
(operation 10). ICP-CVD is performed under the conditions described
above in Deposition of Silicon Thin Film, thereby forming the
poly-Si silicon on the substrate. One technical feature of the
present invention is the direct attainment of the poly-Si through
the deposition without any annealing. After the deposition of the
poly-Si, a source/drain impurity is implanted in the poly-Si to
form an active layer (operation 11), and then, step-by-step ELA is
performed under the conditions described above in Annealing Using
ELA (operation 12).
[0045] Then, the poly-Si is patterned in the form of the active
layer (operation 13). The patterning is performed by dry etching,
such as a reactive ion etching (RIE). After the active layer is
patterned, a Si0.sub.2 thin film to be used as a gate insulating
layer is formed under the conditions described above in Deposition
of Gate Insulating Layer (operation 14). During this process, the
ELA is performed on the Si02 thin film (operation 15). In the
annealing of the Si02 thin film, the laser is irradiated with an
energy density of 120-140 mJ/cm.sup.2.
[0046] After the Si02 gate insulating layer is formed, a metal film
such as an Al film is deposited at a temperature of 120.degree. C.
(operation 16) and then patterned to form the gate (electrode)
(operation 17).
[0047] Then, Si02 is deposited on the resultant structure as an
intermetal dielectric at a temperature of 150.degree. C. by ICP-CVD
(operation 18). Then, a contact hole is formed and a metallization
is performed, thereby forming the poly-Si TFT (operation 19).
[0048] Table 1 shows sheet resistances of the doped Si thin films
annealed under the different ELA conditions. A first row
illustrates a case when 10 shots of the excimer laser at 110
mJ/cm.sup.2 were irradiated. In this case, the sheet resistance was
1138 0/sq. A second row illustrates a case when 10 shots of the
excimer laser at 120 mJ/cm.sup.2 were irradiated. In this case, the
sheet resistance was 830 Q/sq. A third row illustrates a case when
the energy density is incrementally increased. In this case, the
excimer laser is irradiated ten times at an energy density of 110
mJ/cm.sup.2, five times at 140 mJ/cm.sup.2, and five times at 160
mJ/cm.sup.2. The sheet resistance in this case was 224 0/sq.
TABLE-US-00001 TABLE 1 Laser Energy Density (mJ/cm.sup.2) Number of
Shots Sheet Resistance (S2/sq) 110 10 1138 120 10 830 110 + 140 +
160 10 + 5 + 5 224
[0049] FIGS. 10 and 11 illustrate electrical characteristics of the
poly-Si TFT according to an embodiment of the present invention and
a prior art poly-Si TFT having a mobility of 100 cm.sup.2 Ns. The
electrical characteristics of the TFT according to an embodiment of
the present invention are summarized in Table 2 below.
TABLE-US-00002 TABLE 2 Typical Value (max. TFT Parameters or min.
value) Ion (VAS = 15 V, Vos = 5 V) [, um] 140 (200) Mobility
[cm{grave over ( )}Ns] 107 (140) Minimum off current [nA] (VDS = 5
V) 0.4 (0.1) Subthreshold Swing [V/dec] 0.76 (0.52) On/Off current
ratio 5 .times. 10' (1 .times. 10.sup.6)
[0050] As shown in Table 2, the maximum mobility of the TFT
according to an embodiment of the present invention is 140
cm.sup.2Ns, while the conventional mobility is 100 cm.sup.2Ns.
Also, the subthreshold swing is 0.52 V/dec. It is noted that an
annealing or post-annealing is not performed on the TFT according
to an embodiment of the present invention. According to the
analysis of the effect of the laser device on the gate insulating
layer, when an excimer laser irradiates light with an energy
density of 120-140 mJ/cm.sup.2, preferably 130 mJ/cm.sup.2, the
electrical characteristics of the TFT are improved, as illustrated
in FIG. 10. If the energy density is increased to 200 mJ/cm.sup.2,
the electrical characteristics are degraded, resulting in a large
reduction in the drain current. This may result from an occurrence
of a defect in the gate insulating layer resulting from the laser
irradiation with the excessive energy density.
[0051] FIG. 11 is a graph illustrating a drain current with respect
to a drain bias when a gate-source voltage (VAS) of the TFT
according to an embodiment of the present invention is 1 V, 3 V and
5V. In FIG. 11, three curves correspond to the gate-source voltages
(VAS) of 1 V, 3 V and 5 V from below, respectively. In this case,
width and length of the gate are 20, u m and 10 g m,
respectively.
[0052] As described above, the present invention can be used to
produce a ploy-Si instead of a-Si by forming a Si thin film at a
low temperature of 150.degree. C. using a He/S1H4 gas through
ICP-CVD. A grain size of the poly-Si is large by selectively and
additionally performing ELA, thereby improving electrical
characteristics. For example, mobility of a TFT fabricated
according to an embodiment of the present invention can be higher
than 100 cm.sup.2Ns.
[0053] The method of fabricating a poly-Si thin film according to
the present invention can be applied to a flat panel display,
particularly to an AMLCD, an AMOLED, a solar cell, or a
semiconductor memory, which uses a plastic substrate. Such a
poly-Si thin film is adapted for use in a TFT, which requires a
high mobility and fast response speed and uses a plastic substrate.
Such a TFT can be applied to any electronic device, including an
AMLCD, an AMOLED, a switching device and an amplifying device.
[0054] While the present invention has been particularly shown and
described with reference to exemplary embodiments thereof, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made therein without departing
from the spirit and scope of the present invention as defined by
the following claims.
* * * * *