U.S. patent application number 12/318856 was filed with the patent office on 2009-12-03 for thin film transistor, method of manufacturing the same and flat panel display device having the same.
Invention is credited to Jae-Kyeong Jeong, Jong-Han Jeong, Kwang-Suk Kim, Yeon-Gon Mo, Hui-Won Yang.
Application Number | 20090294772 12/318856 |
Document ID | / |
Family ID | 41378655 |
Filed Date | 2009-12-03 |
United States Patent
Application |
20090294772 |
Kind Code |
A1 |
Jeong; Jong-Han ; et
al. |
December 3, 2009 |
Thin film transistor, method of manufacturing the same and flat
panel display device having the same
Abstract
A thin film transistor is provided having an oxide semiconductor
as an active layer, a method of manufacturing the thin film
transistor and a flat panel display device having the thin film
transistor. The thin film transistor includes: a gate electrode
formed on a substrate; an oxide semiconductor layer isolated from
the gate electrode by a gate insulating layer and including
channel, source and drain regions; source and drain electrodes
coupled to the source and drain regions, respectively; and an ohmic
contact layer interposed between the source and drain regions and
the source and drain electrodes. In the TFT, the ohmic contact
layer is formed with the oxide semiconductor layer having a carrier
concentration higher than those of the source and drain
regions.
Inventors: |
Jeong; Jong-Han; (Suwon-si,
KR) ; Kim; Kwang-Suk; (Suwon-si, KR) ; Jeong;
Jae-Kyeong; (Suwon-si, KR) ; Yang; Hui-Won;
(Suwon-si, KR) ; Mo; Yeon-Gon; (Suwon-si,
KR) |
Correspondence
Address: |
ROBERT E. BUSHNELL & LAW FIRM
2029 K STREET NW, SUITE 600
WASHINGTON
DC
20006-1004
US
|
Family ID: |
41378655 |
Appl. No.: |
12/318856 |
Filed: |
January 9, 2009 |
Current U.S.
Class: |
257/59 ; 257/66;
257/E21.411; 257/E33.004; 313/504; 438/151 |
Current CPC
Class: |
H01L 27/3262 20130101;
H01L 29/7869 20130101; H01L 27/1225 20130101; H01L 29/66969
20130101; H01L 29/78618 20130101 |
Class at
Publication: |
257/59 ; 257/66;
313/504; 438/151; 257/E33.004; 257/E21.411 |
International
Class: |
H01L 33/00 20060101
H01L033/00; H01J 1/62 20060101 H01J001/62; H01L 21/336 20060101
H01L021/336 |
Foreign Application Data
Date |
Code |
Application Number |
May 30, 2008 |
KR |
10-2008-0050802 |
Claims
1. A thin film transistor (TFT), comprising: a substrate; a gate
electrode formed on the substrate; an oxide semiconductor layer
isolated from the gate electrode by a gate insulating layer and
including channel, source and drain regions; source and drain
electrodes coupled to the source and drain regions, respectively;
and an ohmic contact layer interposed between the source and drain
regions and the source and drain electrodes, the ohmic contact
layer being formed with the oxide semiconductor layer having a
carrier concentration higher than those of the source and drain
regions.
2. The TFT as claimed in claim 1, wherein the oxide semiconductor
layer and the ohmic contact layer comprise oxide zinc (ZnO) as a
main component.
3. The TFT as claimed in claim 2, wherein the oxide semiconductor
layer and the ohmic contact layer are doped with at least one ion
of indium (In), gallium (Ga) and stannum (Sn).
4. The TFT as claimed in claim 1, wherein the carrier concentration
of the oxide semiconductor layer is 1e+13 to 1e+17#/cm.sup.3, and
the carrier concentration of the ohmic contact layer is 1e+19 to
1e+21#/cm.sup.3.
5. A method of manufacturing a TFT, comprising: forming a gate
electrode on a substrate; forming a gate insulating layer on the
substrate having the gate electrode; forming an oxide semiconductor
layer including channel, source and drain regions on the gate
insulating layer so that an ohmic contact layer having a carrier
concentration higher than those of the source and drain regions is
formed on a surface of the oxide semiconductor layer; forming
source and drain electrodes respectively coupled to the source and
drain regions through the ohmic contact layer; and removing the
ohmic contact layer interposed between the source and drain
electrodes.
6. The method as claimed in claim 5, wherein the oxide
semiconductor layer is formed of zinc oxide (ZnO).
7. The method as claimed in claim 6, wherein at least one ion of
indium (In), gallium (Ga) and stannum (Sn) is doped into the oxide
semiconductor layer.
8. The method as claimed in claim 5, wherein the ohmic contact
layer is formed by decreasing oxygen partial pressure in the
process of forming the oxide semiconductor layer.
9. The method as claimed in claim 5, wherein the ohmic contact
layer is formed by performing plasma treatment with respect to the
surface of the oxide semiconductor layer.
10. The method as claimed in claim 5, wherein the carrier
concentration of the oxide semiconductor layer is 1e+13 to
1e+17#/cm.sup.3, and the carrier concentration of the ohmic contact
layer is 1e+19 to 1e+21#/cm.sup.3.
11. A flat panel display device having a TFT, comprising: a first
substrate having a plurality of pixels defined by a plurality of
first and second conductive lines, a TFT controlling a signal
supplied to each of the pixels, and a first electrode coupled to
the TFT; a second substrate having a second electrode; and a liquid
crystal layer injected into a sealed space between the first and
second electrodes, the TFT comprising: a gate electrode formed on
the first substrate; an oxide semiconductor layer isolated from the
gate electrode by a gate insulating layer and including channel,
source and drain regions; source and drain electrodes coupled to
the source and drain regions, respectively; and an ohmic contact
layer interposed between the source and drain regions and the
source and drain electrodes, the ohmic contact layer being formed
with the oxide semiconductor layer having a carrier concentration
higher than those of the source and drain regions.
12. The flat panel display device as claimed in claim 11, wherein
the oxide semiconductor layer and the ohmic contact layer comprise
oxide zinc (ZnO) as a main component.
13. The flat panel display device as claimed in claim 12, wherein
the oxide semiconductor layer and the ohmic contact layer are doped
with at least one ion of indium (In), gallium (Ga) and stannum
(Sn).
14. The flat panel display device as claimed in claim 11, wherein
the carrier concentration of the oxide semiconductor layer is 1e+13
to 1e+17#/cm.sup.3, and the carrier concentration of the ohmic
contact layer is 1e+19 to 1e+21#/cm.sup.3.
15. A flat panel display device having a TFT, comprising: a first
substrate having an organic light emitting device including a first
electrode, an organic thin film layer and a second electrode, and a
TFT controlling an operation of the organic light emitting device;
and a second substrate disposed opposite to the first substrate,
the TFT comprising: a gate electrode formed on the first substrate;
an oxide semiconductor layer isolated from the gate electrode by a
gate insulating layer and including channel, source and drain
regions; source and drain electrodes coupled to the source and
drain regions, respectively; and an ohmic contact layer interposed
between the source and drain regions and the source and drain
electrodes, the ohmic contact layer being formed with the oxide
semiconductor layer having a carrier concentration higher than
those of the source and drain regions.
16. The flat panel display device as claimed in claim 15, wherein
the oxide semiconductor layer and the ohmic contact layer comprise
oxide zinc (ZnO) as a main component.
17. The flat panel display device as claimed in claim 16, wherein
the oxide semiconductor layer and the ohmic contact layer are doped
with at least one ion of indium (In), gallium (Ga) and stannum
(Sn).
18. The flat panel display device as claimed in claim 16, wherein
the carrier concentration of the oxide semiconductor layer is 1e+13
to 1e+17#/cm.sup.3, and the carrier concentration of the ohmic
contact layer is 1e+19 to 1e+21#/cm.sup.3.
Description
CLAIM OF PRIORITY
[0001] This application makes reference to, incorporates the same
herein, and claims all benefits accruing under 35 U.S.C. .sctn.119
from an application for THIN FILM TRANSISTOR, METHOD OF
MANUFACTURING THE THIN FILM TRANSISTOR AND FLAT PANEL DISPLAY
DEVICE HAVING THE THIN FILM TRANSISTOR earlier filed in the Korean
Intellectual Property Office on May 30, 2008 and there duly
assigned Serial No. 10-2008-0050802.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a thin film transistor, a
method of manufacturing the same and a flat panel display device
having the same, and more particularly, to a thin film transistor
having an oxide semiconductor as an active layer, a method of
manufacturing the same and a flat panel display device having the
same.
[0004] 2. Discussion of Related Art
[0005] In general, a thin film transistor (TFT) includes an active
layer providing channel, source and drain regions, and a gate
electrode formed on the channel region and electrically insulated
from the active layer by a gate insulating layer.
[0006] The active layer of the TFT described above is generally
formed of a semiconductor material such as amorphous silicon or
poly-silicon. At this time, if the active layer is formed of
amorphous silicon, mobility is low, so that it is difficult to
realize a driving circuit operating at a high speed. If the active
layer is formed of poly-silicon, mobility is high while a threshold
voltage is not uniform. Therefore, a separate compensation circuit
should be added.
[0007] A conventional method of manufacturing a TFT using low
temperature poly-silicon (LTPS) involves a high-cost process such
as laser heat treatment, and is not easy to control
characteristics. Therefore, it is difficult to apply the
conventional method to a large-sized substrate.
[0008] In order to solve such a problem, studies on an oxide
semiconductor used as an active layer have recently been
conducted.
[0009] A TFT using a zinc oxide (ZnO) or oxide semiconductor
containing ZnO as a main component as an active layer has been
disclosed in Japanese Patent Publication No. 2004-273614.
[0010] An oxide semiconductor containing ZnO as a main component is
estimated to be an amorphous and stable material. If such an oxide
semiconductor is used as an active layer, a TFT can be manufactured
using a conventional LTPS process, which can be performed at a low
temperature of 300.degree. C. or less.
[0011] However, in order to apply the oxide semiconductor
containing ZnO as a main component to a device, it is required to
develop a process satisfying electrical characteristics and improve
characteristics in general. In addition, it is difficult to form an
ohmic contact between a source/drain region and a metal
electrode.
[0012] The above information disclosed in this Background section
is only for enhancement of understanding of the background of the
invention and therefore it may contain information that does not
form the prior art that is already known to a person of ordinary
skill in the art.
SUMMARY OF THE INVENTION
[0013] Accordingly, it is an object of the present invention to
provide a TFT in which an ohmic contact is formed between an oxide
semiconductor layer and a metal electrode, a method of
manufacturing the same, and a flat panel display device having the
same.
[0014] It is another object of the present invention to provide a
TFT in which an ohmic contact layer is formed without adding a mask
and a process, a method of manufacturing the same and a flat panel
display device having the same.
[0015] According to an aspect of the present invention, the present
invention provides a thin film transistor (TFT), which includes: a
substrate; a gate electrode formed on the substrate; an oxide
semiconductor layer isolated from the gate electrode by a gate
insulating layer and including channel, source and drain regions;
source and drain electrodes coupled to the source and drain
regions, respectively; and an ohmic contact layer interposed
between the source and drain regions and the source and drain
electrodes, wherein the ohmic contact layer is formed with the
oxide semiconductor layer having a carrier concentration higher
than those of the source and drain regions.
[0016] According to another aspect of the present invention, the
present invention provides a method of manufacturing a TFT, which
includes: forming a gate electrode on a substrate; forming a gate
insulating layer on the substrate having the gate electrode;
forming an oxide semiconductor layer including channel, source and
drain regions on the gate insulating layer so that an ohmic contact
layer having a carrier concentration higher than those of the
source and drain regions is formed on a surface of the oxide
semiconductor layer; forming source and drain electrodes
respectively coupled to the source and drain regions through the
ohmic contact layer; and removing the ohmic contact layer
interposed between the source and drain electrodes.
[0017] According to still another aspect of the present invention,
the present invention provides a flat panel display device having a
TFT, which includes: a first substrate having a plurality of pixels
defined by a plurality of first and second conductive lines, a TFT
controlling a signal supplied to each of the pixels, and a first
electrode coupled to the TFT; a second substrate having a second
electrode; and a liquid crystal layer injected into a sealed space
between the first and second electrodes, wherein the TFT includes:
a gate electrode formed on the first substrate; an oxide
semiconductor layer isolated from the gate electrode by a gate
insulating layer and including channel, source and drain regions;
source and drain electrodes coupled to the source and drain
regions, respectively; and an ohmic contact layer interposed
between the source and drain regions and the source and drain
electrodes, wherein the ohmic contact layer is formed with the
oxide semiconductor layer having a carrier concentration higher
than those of the source and drain regions.
[0018] According to still another aspect of the present invention,
the present invention provides a flat panel display device having a
TFT, which includes: a first substrate having an organic light
emitting device including a first electrode, an organic thin film
layer and a second electrode, and a TFT controlling an operation of
the organic light emitting device; and a second substrate disposed
opposite to the first substrate, wherein the TFT includes: a gate
electrode formed on the first substrate; an oxide semiconductor
layer isolated from the gate electrode by a gate insulating layer
and including channel, source and drain regions; source and drain
electrodes coupled to the source and drain regions, respectively;
and an ohmic contact layer interposed between the source and drain
regions and the source and drain electrodes, wherein the ohmic
contact layer is formed with the oxide semiconductor layer having a
carrier concentration higher than those of the source and drain
regions.
[0019] The contact resistance of a silicon (Si) semiconductor and a
metal electrode is in inverse proportion to the carrier
concentration of the silicon semiconductor. Therefore, in a process
of manufacturing a TFT having the silicon semiconductor as an
active layer, the depletion width of the semiconductor layer is
decreased by doping an ion of a high concentration, so that
carriers can easily pass through an energy barrier. However, if a
doping method is used, the number of masks and processes is
increased, and therefore, manufacturing costs may be increased.
Recently, a process of manufacturing a TFT using an oxide
semiconductor as an active layer has been developed, but a method
of forming an ohmic contact between an oxide semiconductor layer
and a metal electrode have not been proposed yet.
[0020] According to the present invention, in a process of forming
an oxide semiconductor layer, oxygen partial pressure is increased,
or plasma treatment is performed with respect to a surface of the
oxide semiconductor layer, thereby forming an ohmic contact layer
having a high carrier concentration on the surface of the oxide
semiconductor layer. Since the ohmic contact layer is formed by
controlling the carrier concentration using a relatively simple
method, the number of masks and processes can be decreased, and
electrical characteristics of a device can be improved by a
low-resistance ohmic contact.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] A more complete appreciation of the invention, and many of
the attendant advantages thereof, will be readily apparent as the
same becomes better understood by reference to the following
detailed description when considered in conjunction with the
accompanying drawings in which like reference symbols indicate the
same or similar components, wherein:
[0022] FIG. 1 is a cross-sectional view of a thin film transistor
(TFT) showing according to the present invention.
[0023] FIGS. 2A to 2E are cross-sectional views illustrating a
method of fabricating the TFT according to the present
invention.
[0024] FIG. 3 is a graph showing a change in carrier concentration
of an oxide semiconductor layer depending on an oxygen partial
pressure.
[0025] FIG. 4 is a perspective view showing an embodiment of a flat
panel display device having the TFT according to the present
invention.
[0026] FIGS. 5A and 5B are respectively plan and cross-sectional
views showing another embodiment of a flat panel display device
having a TFT according to the present invention.
[0027] FIG. 6 is a cross-sectional view of an organic light
emitting element of FIG. 5A.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0028] In the following detailed description, only certain
exemplary embodiments of the present invention have been shown and
described, simply by way of illustration. As those skilled in the
art would realize, the described embodiments may be modified in
various different ways, all without departing from the spirit or
scope of the present invention. Accordingly, the drawings and
description are to be regarded as illustrative in nature and not
restrictive. In addition, when an element is referred to as being
"on" another element, it can be directly on the element or be
indirectly on the another element with one or more intervening
elements interposed therebetween. Also, when an element is referred
to as being "connected to" another element, it can be directly
connected to the element or be indirectly connected to the element
with one or more intervening elements interposed therebetween.
Hereinafter, like reference numerals refer to like elements.
[0029] FIG. 1 is a cross-sectional view of a thin film transistor
(TFT) showing according to the present invention.
[0030] A buffer layer 12 is formed on a substrate 10 formed of an
insulating material, and a gate electrode 14 is formed on the
buffer layer 12. An oxide semiconductor layer 18a is formed above
the substrate 10 having the gate electrode 14. The oxide
semiconductor layer 18a is electrically isolated from the gate
electrode 14 by a gate insulating layer 16 and provides channel,
source and drain regions. An ohmic contact layer 18b is interposed
between the oxide semiconductor layer 18a of the source and drain
regions and source and drain electrodes 20a and 20b.
[0031] The oxide semiconductor layer 18a and the ohmic contact
layer 18b may be formed of a semiconductor material containing zinc
oxide (ZnO) as a main component, or InZnO (IZO), GaInZO (GIZO) or
the like, which is formed by doping at least one ion of indium
(In), gallium (Ga) and stannum (Sn) into the semiconductor material
containing ZnO as a main component. At this time, the ohmic contact
layer 18b has a carrier concentration higher than the oxide
semiconductor layer 18a of the source and drain regions so as to
form an ohmic contact between the oxide semiconductor layer 18a of
the source and drain regions and the source and drain electrodes
20a and 20b. For example, the oxide semiconductor layer 18a has a
carrier concentration of 1e+13 to 1e+17#/cm.sup.3, and the ohmic
contact layer 18b has a carrier concentration of 1e+19 to
1e+21#/cm.sup.3.
[0032] FIGS. 2A to 2E are cross-sectional views illustrating a
method of fabricating the TFT according to the present invention.
The TFT of the present invention will be described in detail
through the following manufacturing process.
[0033] Referring to FIG. 2A, a buffer layer 12 is formed on a
substrate 10 made of an insulating material. A gate electrode 14 is
formed on the buffer layer 12, and a gate insulating layer 16 is
formed above the substrate 10 having the gate electrode 14. The
gate electrode 14 is formed of a metal such as Mo, MoW or Al, and
the gate insulating layer 16 is formed of a silicon oxide layer
(SiO.sub.2) or silicon nitride layer (SiNx).
[0034] Referring to FIG. 2B, an oxide semiconductor layer 18a
including channel, source and drain regions is formed on the gate
insulating layer 16 to overlap with the gate electrode 14. The
oxide semiconductor layer 18a is formed of a semiconductor material
containing zinc oxide (ZnO) as a main component, or InZnO (IZO),
GaInZO (GIZO) or the like, which is formed by doping at least one
ion of indium (In), gallium (Ga) and stannum (Sn) into the
semiconductor material containing ZnO as a main component.
[0035] In one embodiment, a GIZO layer may be formed using a
co-sputtering method using two or more targets or a pulse laser
deposition method. GaInZnO, InZnO, Ga.sub.2O.sub.3 or the like is
used as the target, and ions including In, Ga and Zn are deposited
from the target, thereby forming a GIZO layer having a carrier
concentration of about 1e+13 to 1e+17#/cm.sup.3. At this time, the
carrier concentration may be controlled by a percentage of oxygen
occupying the GIZO layer, i.e., oxygen partial pressure. At this
time, if the carrier concentration is controlled to have
1e+17#/cm.sup.3 or more, mobility increases while leakage current
occurs in an off-state due to the decrease of specific
resistivity.
[0036] FIG. 3 is a graph showing a change in carrier concentration
of an oxide semiconductor layer depending on an oxygen partial
pressure. The oxygen partial pressure is controlled to be, for
example, 30 to 90% in a deposition process, thereby forming an
amorphous oxide semiconductor layer (IZO or GIZO) having a carrier
concentration of 1e+13 to 1e+17#/cm.sup.3. The change in carrier
concentration depending on an oxygen partial pressure may refer to
the paper (H. Hosono, "Non-crystalline solids", 2006).
[0037] Referring to FIG. 2C, an ohmic contact layer 18b having a
carrier concentration higher than that of the oxide semiconductor
layer 18a of the source and drain regions is formed on a surface of
the oxide semiconductor layer 18a.
[0038] In one embodiment, the ohmic contact layer 18b may be
simultaneously formed with the oxide semiconductor layer 18a. In
the process of forming the oxide semiconductor layer 18a a shown in
FIG. 2B, the oxygen partial pressure is decreased, thereby forming
the ohmic contact layer 18b having a carrier concentration higher
than that of the oxide semiconductor layer 18a of the source and
drain regions.
[0039] If the oxygen partial pressure is increased, the content of
oxygen atoms (O.sub.2) in a thin film is increased by reactive
sputtering. Since one oxygen atom is coupled with two electrons in
the thin film, the carrier concentration is decreased. Therefore,
the oxygen partial pressure is decreased using such a principle,
thereby increasing the carrier concentration. The semiconductor
characteristic of GIZO may be changed into the conductor
characteristic of GIZO by controlling the carrier concentration of
GIZO, or the carrier concentration of GIZO may be changed depending
on the depth of GIZO.
[0040] In another embodiment, the oxide semiconductor layer 18a is
formed, and the ohmic contact layer 18b is then formed. After the
oxide semiconductor layer 18a is formed as shown in FIG. 2B, the
ohmic contact layer 18b is formed by performing plasma treatment
with respect to the surface of the oxide semiconductor layer 18a as
shown in FIG. 2D.
[0041] If the surface of the oxide semiconductor layer 18a is
exposed to plasma such as argon (Ar), surface lattice is broken.
Accordingly, oxygen deficiency occurs to increase the carrier
concentration, thereby forming the ohmic contact layer 18b of a
conductor characteristic having a carrier concentration of about
1e+19 to 1e+21#/cm.sup.3.
[0042] Referring to FIG. 2E, a conductive layer is formed with a
metal such as Mo, MoW, Al, AlAd, or AlLiLa on the entire surface of
the substrate 10 and then patterned, thereby forming source and
drain electrodes 20a and 20b connected to the oxide semiconductor
layer 18a of the source drain regions through the ohmic contact
layer 18b. Then, the ohmic contact layer 18b exposed between the
source and drain electrodes 20a and 20b is removed. The ohmic
contact layer 18b exposed between the source and drain electrodes
20a and 20b may be removed through over-etching in an etching
process for patterning the source and drain electrodes 20a and 20b.
If the ohmic contact layer 18b exposed as described above is
removed through over-etching, the number of masks and processes can
be decreased.
[0043] The TFT of the present invention may be applied to a flat
panel display device such as a liquid crystal display device or an
organic light emitting display device.
[0044] FIG. 4 is a perspective view showing an embodiment of a flat
panel display device having the TFT according to the present
invention. A display panel 100 displaying images will be
schematically described.
[0045] The display panel 100 includes two substrates 110 and 120
disposed opposite to each other, and a liquid crystal layer 130
interposed between the two substrates 110 and 120. Pixel regions
113 are defined by a plurality of gate and data lines 111 and 112
arranged in a matrix form. A TFT 114 controlling a signal supplied
to each pixel and a pixel electrode 115 coupled to the transistor
114 are formed at each intersection portion of the gate and data
lines 111 and 112 on the substrate 110.
[0046] The TFT 114 has a structure shown in FIG. 1, and may be
manufactured using the manufacturing method described with
reference to FIGS. 2A to 2E.
[0047] A color filter 121 and a common electrode 122 are formed on
the substrate 120. Polarizing plates 116 and 123 are formed at rear
surfaces of the substrates 110 and 120, respectively, and a
backlight (not shown) is disposed below the polarizing plate
116.
[0048] Meanwhile, an LCD drive IC (not shown) driving the display
panel 100 is mounted at a side of the pixel regions 113 of the
display panel 100. The LCD drive IC converts electric signals
provided from the outside of the display panel 100 into scan and
data signals, and then supplies the converted scan and data signals
to the gate and data lines 111 and 112.
[0049] FIGS. 5A and 5B are respectively plan and cross-sectional
views showing another embodiment of a flat panel display device
having a TFT according to the present invention. A display panel
200 displaying images will be schematically described.
[0050] Referring to FIG. 5A, a substrate 210 is divided into a
pixel region 220 and a non-pixel region 230 surrounding the pixel
region 220. A plurality of organic light emitting devices 300
connected in a matrix form between scan and data lines 224 and 226
are formed on the substrate 210 of the pixel region 220. On the
substrate 210 of the non-pixel region 230 are formed the scan and
data lines 224 and 226 extended from the pixel region 220, a power
supply line (not shown) operating the organic light emitting
devices 300, and scan and data drivers 234 and 236 respectively
supplying signals provided from the outside of the display panel
200 to the scan and data lines 224 and 226.
[0051] Referring to FIG. 6, the organic light emitting device 300
includes an anode electrode 317, a cathode electrode 320 and an
organic thin film layer 319 formed between the anode and cathode
electrodes 317 and 320. The organic thin film layer 319 is formed
into a structure in which a hole transfer layer, an organic light
emitting layer and an electron transfer layer are laminated. A hole
injection layer and an electron injection layer may be further
included in the organic thin film layer 319. The organic light
emitting device 300 may further include a TFT controlling an
operation of the organic light emitting device 300 and a capacitor
maintaining signals.
[0052] The TFT has a structure shown in FIG. 1, and may be
manufactured using the manufacturing method described with
reference to FIGS. 2A to 2E.
[0053] Hereinafter, the organic light emitting element 300
including the TFT configured as described above will be described
in detail with reference to FIGS. 5A and 6.
[0054] A buffer layer 12 is formed on a substrate 210, and a gate
electrode 14 is formed on the buffer layer 12 of a pixel region
220. At this time, a scan line 224 coupled to the gate electrode 14
is formed in the pixel region 220. The scan line 224 extended from
the pixel region and a pad 228 receiving signals provided from the
outside may be formed in a non-pixel region 230.
[0055] An oxide semiconductor layer 18a electrically isolated from
the gate electrode 14 by a gate insulating layer 16 and providing
channel, source and drain regions is formed above the 5 substrate
210 having the gate electrode 14, and an ohmic contact layer 18b is
formed in the source and drain regions of the oxide semiconductor
layer 18a. The oxide semiconductor layer 18a and the ohmic contact
layer 18b are formed of a semiconductor material containing zinc
oxide (ZnO) as a main component, or InZnO (IZO), GaInZO (GIZO) or
the like, which is formed by doping at least one ion of indium
(In), gallium (Ga) and stannum (Sn) into the semiconductor material
containing ZnO as a main component. At this time, the ohmic contact
layer 18b has a carrier concentration higher than the oxide
semiconductor layer 18a of the source and drain regions so as to
form an ohmic contact between the oxide semiconductor layer 18a of
the source and drain regions and the source and drain electrodes
20a and 20b. For example, the oxide semiconductor layer 18a has a
carrier concentration of 1e+13 to 1e+17#/cm.sup.3, and the ohmic
contact layer 18b has a carrier concentration of 1e+19 to
1e+21#/cm.sup.3.
[0056] Source and drain electrodes 20a and 20b are formed to be
coupled to the oxide semiconductor layer 18a of the source and
drain regions through the ohmic contact layer 18b. At this time, a
data line 226 coupled to the source and drain electrodes 20a and
20b is formed in the pixel region 220, and the data line 226
extended from the pixel region 220 and the pad 228 receiving
signals provided from the outside are formed in the non-pixel
region.
[0057] A planarization layer 316 is formed above the substrate 210
having the source and drain electrodes 20a and 20b. A via hole
through which the source or drain electrode 20a or 20b is exposed
and an anode electrode 317 coupled to the source or drain electrode
20a or 20b through the via hole are formed in the planarization
layer 316.
[0058] A pixel defining layer 318 is formed on the planarization
layer 316 so that a region (light emitting region) of the anode
electrode 317 is exposed.
[0059] Referring to FIG. 5B, a sealing substrate 400 sealing the
pixel region 220 is disposed above the substrate 210 having the
organic light emitting device 300, and the sealing substrate 400 is
joined with the substrate 210 by a sealing member 410, thereby
completing the display panel 200.
[0060] While the present invention has been described in connection
with certain exemplary embodiments, it is to be understood that the
invention is not limited to the disclosed embodiments, but, on the
contrary, is intended to cover various modifications and equivalent
arrangements included within the spirit and scope of the appended
claims, and equivalents thereof.
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