U.S. patent application number 12/472206 was filed with the patent office on 2009-11-26 for semiconductor device and method of fabricating the same.
This patent application is currently assigned to HYNIX SEMICONDUCTOR INC.. Invention is credited to Kwang Seok Jeon.
Application Number | 20090289295 12/472206 |
Document ID | / |
Family ID | 41341443 |
Filed Date | 2009-11-26 |
United States Patent
Application |
20090289295 |
Kind Code |
A1 |
Jeon; Kwang Seok |
November 26, 2009 |
Semiconductor Device and Method of Fabricating the same
Abstract
The invention relates to semiconductor devices and a method of
fabricating the same. In accordance with a method of fabricating a
semiconductor device according to an aspect of the invention, a
tunnel insulating layer, a first conductive layer, a dielectric
layer, a second conductive layer, and a gate electrode layer are
sequentially stacked over a semiconductor substrate. The gate
electrode layer, the second conductive layer, the dielectric layer,
and the first conductive layer are patterned so that the first
conductive layer partially remains to prevent the tunnel insulating
layer from being exposed. Sidewalls of the gate electrode layer are
etched. A first passivation layer is formed on the entire surface
including the sidewalls of the gate electrode layer. At this time,
a thickness of the first passivation layer formed on the sidewalls
of the gate electrode layer is thicker than that of the first
passivation layer formed in other areas. A cleaning process is
performed to thereby remove byproducts occurring in the etch
process. A gate pattern is formed by etching the first passivation
layer, the first conductive layer, and the tunnel insulating
layer.
Inventors: |
Jeon; Kwang Seok;
(Icheon-Si, KR) |
Correspondence
Address: |
MARSHALL, GERSTEIN & BORUN LLP
233 SOUTH WACKER DRIVE, 6300 SEARS TOWER
CHICAGO
IL
60606-6357
US
|
Assignee: |
HYNIX SEMICONDUCTOR INC.
Gyeonggi-do
KR
|
Family ID: |
41341443 |
Appl. No.: |
12/472206 |
Filed: |
May 26, 2009 |
Current U.S.
Class: |
257/321 ;
257/E21.209; 257/E21.422; 257/E29.3; 438/594 |
Current CPC
Class: |
H01L 29/513 20130101;
H01L 29/66825 20130101; H01L 29/7881 20130101 |
Class at
Publication: |
257/321 ;
438/594; 257/E29.3; 257/E21.422; 257/E21.209 |
International
Class: |
H01L 29/788 20060101
H01L029/788; H01L 21/28 20060101 H01L021/28 |
Foreign Application Data
Date |
Code |
Application Number |
May 26, 2008 |
KR |
10-2008-0048634 |
Claims
1. A semiconductor device, comprising: a gate pattern comprising a
tunnel insulating layer, a conductive layer for a floating gate, a
dielectric layer, a conductive layer for a control gate, and a gate
electrode layer sequentially stacked over a semiconductor
substrate, the gate electrode layer defining sidewalls; a first
passivation layer formed on the sidewalls of the gate electrode
layer; and a second passivation layer formed on the entire surface
along a surface of the first passivation layer and the gate
pattern, wherein a critical dimension of the gate electrode layer
is smaller than that of the conductive layer for the control
gate.
2. The semiconductor device of claim 1, wherein the first
passivation layer is formed on the sidewalls of the gate electrode
layer and on the same line as that of the sidewalls of the gate
pattern.
3. The semiconductor device of claim 1, wherein: the first
passivation layer comprises a nitride layer, and the second
passivation layer comprises an oxide layer.
4. The semiconductor device of claim 1, wherein the second
passivation layer comprises a high-temperature oxide (HTO) layer, a
low-pressure tetraethyl orthosilicate (LP-TEOS) layer, or an atomic
layer depostion (ALD) oxide layer.
5. A method of fabricating a semiconductor device, comprising:
sequentially stacking a tunnel insulating layer, a first conductive
layer, a dielectric layer, a second conductive layer, and a gate
electrode layer over a semiconductor substrate, the gate electrode
layer defining sidewalls; patterning the gate electrode layer, the
second conductive layer, the dielectric layer, and the first
conductive layer, wherein the first conductive layer partially
remains to prevent the tunnel insulating layer from being exposed;
etching the sidewalls of the gate electrode layer; forming a first
passivation layer on the entire surface including the sidewalls of
the gate electrode layer, wherein the first passivation layer
formed on the sidewalls of the gate electrode layer is thicker than
the first passivation layer formed in other areas; performing a
cleaning process to remove byproducts resulting from the etch
process of the gate electrode layer; and forming a gate pattern by
etching the first passivation layer, the first conductive layer,
and the tunnel insulating layer.
6. The method of claim 5, further comprising, after forming the
gate pattern, oxidizing a part of the first passivation layer and
sidewalls of the second conductive layer by performing an
oxidization process, thus forming a second passivation layer.
7. The method of claim 6, comprising forming the second passivation
layer by oxidizing the first passivation layer formed on the
sidewalls of the second conductive layer and the dielectric layer,
and a part of the first passivation layer formed on the sidewalls
of the gate conductive layer.
8. The method of claim 6, comprising performing the oxidization
process to oxidize 30% to 80% of the first passivation layer formed
on the sidewalls of the gate conductive layer to form the second
passivation layer.
9. The method of claim 5, comprising in etching the sidewalls of
the gate electrode layer, etching the sidewalls of the gate
electrode layer by 1 nm to 10 nm.
10. The method of claim 5, comprising etching the sidewalls of the
gate electrode layer using a dry etch process or a wet etch
process, wherein the wet etch process comprises using
H.sub.2SO.sub.4, NH.sub.4OH, H.sub.2O, HF, HCl, or H.sub.2O.sub.2,
either alone or in combination.
11. The method of claim 5, wherein the first passivation layer
comprises a nitride layer.
12. The method of claim 5, comprising forming the first passivation
layer to fill convex portions that have been generated in the
process of etching the sidewalls of the gate conductive layer, so
that a layer formed on the sidewalls of a conductive layer for a
gate is thicker than a layer formed in the remaining areas.
13. The method of claim 5, comprising forming the first passivation
layer using SiH.sub.4, Si.sub.2H.sub.6, Si.sub.2HCl.sub.2,
NH.sub.3, N.sub.2, Ar, He, or PH.sub.3 gas in a pressure range of
0.05 Torr to 50 Torr.
14. The method of claim 5, comprising forming the first passivation
layer to a thickness of 1 nm to 15 nm.
15. The method of claim 6, wherein the second passivation layer is
formed to a thickness of 1 nm to 12 nm.
16. The method of claim 6, comprising forming the second
passivation layer using a radical oxidization process.
17. The method of claim 6, further comprising forming a third
passivation layer over the semiconductor substrate including the
second passivation layer, wherein the third passivation layer
comprises a high-temperature oxide (HTO) layer, a low-pressure
tetraethyl orthosilicate (LP-TEOS) layer, or an atomic layer
deposition (ALD) oxide layer.
18. The method of claim 5, comprising performing the cleaning
process using a wet cleaning process or a dry cleaning process in
either case employing HF, NH.sub.4OH, or H.sub.2SO.sub.4, either
alone or in combination.
19. A method of fabricating a semiconductor device, comprising:
sequentially stacking a tunnel insulating layer, a first conductive
layer, a dielectric layer, a second conductive layer, and a gate
electrode layer over a semiconductor substrate, the gate electrode
layer defining sidewalls; patterning the gate electrode layer and
the second conductive layer, wherein the second conductive layer
partially remains to prevent the dielectric layer from being
exposed; etching the sidewalls of the gate electrode layer; forming
a first passivation layer on the entire surface including the
sidewalls of the gate electrode layer; performing a cleaning
process to thereby remove byproducts resulting from the etch
process of the gate electrode layer; and forming a gate pattern by
etching the first passivation layer, the second conductive layer,
and the dielectric layer, the first conductive layer, and the
tunnel insulating layer.
20. The method of claim 19, further comprising, after forming the
gate pattern, forming a second passivation layer over the
semiconductor substrate including the gate pattern.
21. The method of claim 19, comprising in etching the sidewalls of
the gate conductive layer, etching the sidewalls of the gate
electrode layer by 1 nm to 13 nm.
22. The method of claim 19, comprising etching the gate electrode
layer using a dry or wet etch process, wherein the wet etch process
is performed using H.sub.2SO.sub.4, NH.sub.4OH, H.sub.2O, HF, HCl,
or H.sub.2O.sub.2, either alone or in combination.
23. The method of claim 19, wherein the first passivation layer
comprises a nitride layer or a dual layer of a nitride layer and an
oxide layer.
24. The method of claim 19, comprising forming the first
passivation layer using SiH.sub.4, Si.sub.2H.sub.6,
Si.sub.2HCl.sub.2, NH.sub.3, N.sub.2, Ar, He, or PH.sub.3 gas and
in a pressure range of 0.05 Torr to 50 Torr.
25. The method of claim 19, further comprising forming a second
passivation layer over the semiconductor substrate including the
first passivation layer from a high-temperature oxide (HTO) layer,
a low-pressure tetraethyl orthosilicate (LP-TEOS) layer, or an
atomic layer deposition (ALD) oxide layer.
26. The method of claim 19, comprising performing the cleaning
process using a wet cleaning process or a dry cleaning process in
either case employing HF, NH.sub.4OH, or H.sub.2SO.sub.4, either
alone or in combination.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] Priority to Korean patent application number
10-2008-0048634, filed May 26, 2008, the entire disclosure of which
is incorporated by reference, is claimed.
BACKGROUND OF THE INVENTION
[0002] The invention relates generally to semiconductor devices and
a method of fabricating the same and, more particularly, to
semiconductor devices and a method of fabricating the same, in
which gate patterns are formed.
[0003] In general, in a flash memory semiconductor device, gate
patterns are formed by patterning a conductive layer for a floating
gate, a dielectric layer, a conductive layer for a control gate,
and a gate electrode.
[0004] FIG. 1 is a sectional view of a semiconductor device for
forming gate patterns of the device in the prior art.
[0005] Referring to FIG. 1, a tunnel insulating layer 11, a
conductive layer for a floating gate 12, a dielectric layer 13, a
conductive layer for a control gate 14, a gate electrode layer 15,
and a hard mask layer 16 are sequentially stacked over a
semiconductor substrate 10. The hard mask layer 16 is patterned and
the gate electrode layer 15 is then patterned by an etch process
using the patterned hard mask layer.
[0006] Generally, in the case in which a tungsten silicide
(WSi.sub.x) layer is used as a gate electrode layer in
semiconductor devices of 50 nm or less, resistance (Rs) of word
lines is increased due to a high resistivity of the tungsten
silicide (WSi.sub.x) layer itself, resulting in low program and
read speeds. To solve the problem, the thickness of the tungsten
silicide (WSi.sub.x) layer must be increased. However, this method
makes the process of patterning the word lines more difficult and
may cause voids within isolation layers that electrically isolate
the word lines. Accordingly, research has been done on a method of
forming a gate electrode layer using a tungsten (W) layer having
lower resistivity than the tungsten silicide (WSi.sub.x) layer.
[0007] However, the tungsten layer is easily oxidized by a thermal
process and easily corroded or oxidized and dissolved by a cleaning
agent in a cleaning process. Accordingly, this method also greatly
limits subsequent processes.
BRIEF SUMMARY OF THE INVENTION
[0008] The invention is directed to a semiconductor device and a
method of fabricating the same, wherein in a gate pattern formation
process using a tungsten (W) layer as a gate conductive layer,
sidewalls of the tungsten layer are etched and a passivation layer
is then formed on the tungsten layer to protect the sidewalls of
the tungsten layer in a subsequent cleaning process, wherein the
passivation layer is formed on etched portions of the tungsten
layer, so that a distance between gates can be secured and process
margin can be secured in a subsequent gap-fill process of
insulating materials.
[0009] A semiconductor device according to an aspect of the
invention includes a gate pattern in which a tunnel insulating
layer, a conductive layer for a floating gate, a dielectric layer,
a conductive layer for a control gate, and a gate electrode layer
are sequentially stacked over a semiconductor substrate, a first
passivation layer formed on sidewalls of the gate electrode layer,
and a second passivation layer formed on the entire surface along a
surface of the first passivation layer and the gate pattern. The
critical dimension of the gate electrode layer is smaller than that
of the conductive layer for the control gate.
[0010] The first passivation layer is formed on the sidewalls of
the gate electrode layer and formed on the same line as that of the
sidewalls of the gate pattern. The first passivation layer is
formed from a nitride layer, and the second passivation layer is
formed from an oxide layer. The second passivation layer includes a
high-temperature oxide (HTO) layer, a low-pressure tetraethyl
orthosilicate (LP-TEOS) layer, or an atomic layer deposition (ALD)
oxide layer.
[0011] A method of fabricating a semiconductor device according to
an aspect of the invention includes sequentially stacking a tunnel
insulating layer, a first conductive layer, a dielectric layer, a
second conductive layer, and a gate electrode layer over a
semiconductor substrate, patterning the gate electrode layer, the
second conductive layer, the dielectric layer, and the first
conductive layer, wherein the first conductive layer partially
remains to prevent the tunnel insulating layer from being exposed,
etching sidewalls of the gate electrode layer, forming a first
passivation layer on the entire surface including the sidewalls of
the gate electrode layer, wherein first passivation layer formed on
the sidewalls of the gate electrode layer is thicker than the first
passivation layer formed in other areas, to prevent abnormal
oxidization of the gate electrode layer, performing a cleaning
process to remove byproducts resulting from the etch process of the
gate electrode layer, and forming a gate pattern by etching the
first passivation layer, the first conductive layer, and the tunnel
insulating layer.
[0012] After the gate pattern is formed, a part of the first
passivation layer and sidewalls of the second conductive layer
preferably are oxidized by performing an oxidization process to
form a second passivation layer.
[0013] The second passivation layer preferably is formed by
oxidizing the first passivation layer formed on the sidewalls of
the second conductive layer and the dielectric layer, and a part of
the first passivation layer formed on the sidewalls of the gate
conductive layer. The oxidization process preferably is performed
to oxidize 30% to 80% of the first passivation layer formed on the
sidewalls of the gate conductive layer to form the second
passivation layer.
[0014] In the etching of the sidewalls of the gate electrode layer,
the sidewalls of the gate electrode layer preferably are etched by
1 nm to 10 nm. The etching of the sidewalls of the gate electrode
layer is performed using a dry etch process or a or wet etch
process, wherein the wet etch process preferably is performed using
H.sub.2SO.sub.4, NH.sub.4OH, H.sub.2O, HF, HCl, or H.sub.2O.sub.2,
either alone or in combination.
[0015] The first passivation layer preferably is formed from a
nitride layer. The first passivation layer preferably is formed to
fill convex portions that have been generated in the process of
etching the sidewalls of the gate conductive layer, so that a layer
formed on the sidewalls of a conductive layer for a gate is thicker
than a layer formed in the remaining areas. The first passivation
layer preferably is formed using SiH.sub.4, Si.sub.2H.sub.6,
Si.sub.2HCl.sub.2, NH.sub.3, N.sub.2, Ar, He, or PH.sub.3 gas,
preferably in a pressure range of 0.05 Torr to 50 Torr. The first
passivation layer preferably is formed to a thickness of 1 nm to 15
nm.
[0016] The second passivation layer preferably is formed to a
thickness of 1 nm to 12 nm. The second passivation layer preferably
is formed using a radical oxidization process.
[0017] A third passivation layer preferably is further formed over
the semiconductor substrate including the second passivation layer.
The third passivation layer preferably comprises an HTO layer, an
LP-TEOS layer, or an ALD oxide layer.
[0018] A method of fabricating a semiconductor device according to
another aspect of the invention includes sequentially stacking a
tunnel insulating layer, a first conductive layer, a dielectric
layer, a second conductive layer, and a gate electrode layer over a
semiconductor substrate, patterning the gate electrode layer and
the second conductive layer, wherein the second conductive layer
partially remains to prevent the dielectric layer from being
exposed, etching sidewalls of the gate electrode layer, forming a
first passivation layer on the entire surface including the
sidewalls of the gate electrode layer, to prevent abnormal
oxidization of the gate electrode layer, performing a cleaning
process to thereby remove byproducts occurring in the etch process
of the gate electrode layer, and forming a gate pattern by etching
the first passivation layer, the second conductive layer, and the
dielectric layer, the first conductive layer, and the tunnel
insulating layer.
[0019] After the gate pattern is formed, a second passivation layer
preferably is formed over the semiconductor substrate including the
gate pattern.
[0020] In etching of the sidewalls of the gate conductive layer,
the sidewalls of the gate electrode layer preferably are etched by
1 nm to 13 nm. The etching of the gate electrode layer preferably
is performed using a dry etch process or a wet etch process,
wherein the wet etch process preferably is performed using
H.sub.2SO.sub.4, NH.sub.4OH, H.sub.2O, HF, HCl, or H.sub.2O.sub.2,
either alone or in combination.
[0021] The first passivation layer preferably comprises a nitride
layer or a dual layer of a nitride layer and an oxide layer. The
first passivation layer preferably is formed using SiH.sub.4,
Si.sub.2H.sub.6, Si.sub.2HCl.sub.2, NH.sub.3, N.sub.2, Ar, He, or
PH.sub.3 gas, preferably in a pressure range of 0.05 Torr to 50
Torr.
[0022] A second passivation layer preferably is further formed over
the semiconductor substrate including the first passivation layer,
wherein the second passivation layer preferably comprises an HTO
layer, an LP-TEOS layer, or an ALD oxide layer.
[0023] The cleaning process preferably is performed using a wet
cleaning process or a dry cleaning process employing HF,
NH.sub.4OH, H.sub.2SO.sub.4, either alone or in combination.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIG. 1 is a sectional view of a semiconductor device for
forming gate patterns of the device in the prior art;
[0025] FIGS. 2A to 2D are sectional views illustrating a method of
fabricating a semiconductor device in accordance with a first
embodiment of the invention; and
[0026] FIGS. 3A to 3D are sectional views illustrating a method of
fabricating a semiconductor device in accordance with a second
embodiment of the invention.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0027] Hereinafter, the invention is described in detail in
connection with specific embodiments with reference to the
accompanying drawings. The disclosed embodiments are provided to
complete the disclosure of the invention and to allow those having
ordinary skill in the art to understand the scope of the invention.
When it is said that any part, such as a layer, film, area, or
plate, is positioned on another part, it means the part is directly
on the other part or above the other part with at least one
intermediate part. To clarify multiple layers and regions, the
thickness of the layers is enlarged in the drawings.
[0028] FIGS. 2A to 2D are sectional views illustrating a method of
fabricating a semiconductor device in accordance with a first
embodiment of the invention.
[0029] Referring to FIG. 2A, a tunnel insulating layer 101, a
conductive layer for a floating gate 102, a dielectric layer 103, a
conductive layer for a control gate 104, a gate electrode layer
105, and a hard mask layer 106 are sequentially stacked over a
semiconductor substrate 100.
[0030] The conductive layer for the floating gate 102 and the
conductive layer for the control gate 104 each preferably comprises
a polysilicon layer. The dielectric layer 103 preferably has an ONO
structure comprising a first oxide layer 103a, a nitride layer
103b, and a second oxide layer 103c. The gate electrode layer 105
preferably comprises a tungsten (W) layer.
[0031] The conductive layer for the floating gate 102 preferably
comprises a dual layer structure, including an amorphous
polysilicon layer not containing an impurity and a polysilicon
layer containing an impurity.
[0032] Although not shown in the drawings, after the conductive
layer for the control gate 104 is formed, a diffusion-prevention
layer preferably is formed before the gate electrode layer 105 is
formed.
[0033] The hard mask layer 106 preferably has a stack structure of
an SiON layer, an oxide layer, a nitride layer, and an amorphous
carbon layer.
[0034] Referring to FIG. 2B, after a photoresist pattern is formed
on the hard mask layer 106, an etch process using the photoresist
pattern is performed. That is, the hard mask layer 106 is
patterned.
[0035] The gate electrode layer 105, the conductive layer for the
control gate 104, the dielectric layer 103, and a part of the
conductive layer for the floating gate 102 are patterned by an etch
process using the patterned hard mask layer 106 as an etch mask,
thus forming primary gate patterns 103, 104, 105 and 106. Here, a
part of the conductive layer for the floating gate 102 may remain
so that the tunnel insulating layer 101 is not exposed.
[0036] Referring to FIG. 2C, an etch process is performed to etch
exposed sidewalls of the gate electrode layer 105.
[0037] The above etch process preferably is controlled in such a
manner that the sidewalls of the gate electrode layer 105 are
etched 1 nm to 10 nm. The etch process may be carried out using a
dry or wet etch process. The wet etch process preferably is
performed using H.sub.2SO.sub.4, NH.sub.4OH, H.sub.2O, HF, HCl, or
H.sub.2O.sub.2, either alone or in combination. Accordingly, the
width of the gate electrode layer 105 becomes narrower than that of
the conductive layer for the control gate 104.
[0038] A first passivation layer 107 is formed on the conductive
layer for the floating gate 102, including the primary gate
patterns 103, 104, 105 and 106. The first passivation layer 107
preferably comprises a nitride layer. The first passivation layer
107 is formed to fill convex portions, which have been formed in
the process of etching the sidewalls of the gate conductive layer
105, and is thicker than the first passivation layer 107 formed on
other parts of the primary gate patterns 103, 104, 105 and 106 (for
example, the sidewalls of the conductive layer for the control gate
104). The first passivation layer 107 preferably is formed using
SiH.sub.4, Si.sub.2H.sub.6, Si.sub.2HCl.sub.2, NH.sub.3, N.sub.2,
Ar, He, or PH.sub.3 gas, preferably in a pressure range of 0.05
Torr to 50 Torr. The first passivation layer 107 preferably is
formed to a thickness of 1 nm to 15 nm.
[0039] Next, a cleaning process preferably is performed to remove
byproducts, which occur in (i.e., result from) the etch process for
forming the primary gate patterns 103, 104, 105, and 106. The
cleaning process preferably is performed using a wet or dry
cleaning process employing HF, NH.sub.4OH, H.sub.2SO.sub.4, either
alone or in combination. Byproducts are removed through the
cleaning process, which can prohibit the occurrence of a bird's
beak phenomenon of the dielectric layer 103 and the tunnel
insulating layer 101. At the time of the cleaning process, the gate
electrode layer 105 is protected by the first passivation layer
107, thus prohibiting an abnormal oxidization phenomenon.
[0040] Referring to FIG. 2D, the first passivation layer 107 formed
on the remaining conductive layer for the floating gate 102, the
conductive layer for the floating gate 102, and the tunnel
insulating layer 101 are etched by an etch process, thus forming
secondary gate patterns 101, 102, 103, 104, 105, and 106. The first
passivation layer formed on the hard mask pattern 106 is removed by
the above etch process.
[0041] The first passivation layer formed on the sidewalls of the
secondary gate patterns 101, 102, 103, 104, 105, and 106, and the
sidewalls of the conductive layer for the floating gate 102 are
oxidized by performing an oxidization process, thus forming a
second passivation layer 108. At this time, the first passivation
layer 107 formed on the sidewalls of the gate conductive layer 105
is thicker than the first passivation layer formed on other areas
(that is, the hard mask pattern 106, the sidewalls of the
conductive layer for the control gate 104, and the sidewalls of the
dielectric layer 103). Accordingly, only a part of the first
passivation layer (refer to 107 of FIG. 2C) is oxidized through the
oxidization process, thereby forming the second passivation layer
108. The second passivation layer 108 preferably is formed by
oxidizing 30% to 80% of the total thickness of the first
passivation layer (refer to 107 of FIG. 2C). The second passivation
layer 108 preferably is formed to a thickness of 1 nm to 12 nm. The
oxidization process preferably employs a radical oxidization
process and preferably is performed in such a manner that a uniform
second passivation layer 108 is formed on the sidewalls of the gate
patterns by controlling the degree of oxidation of a nitride layer
and a polysilicon layer to be 1:0.7 to 1:1.3.
[0042] A third passivation layer 109 is formed on the entire
surface of the semiconductor substrate 100 including the second
passivation layer 108. The third passivation layer 109 may be
formed from an HTO layer, an LP-TEOS layer, or an ALD oxide layer.
In the case in which the third passivation layer 109 is formed from
the HTO layer, it may be preferred that a mixed gas of silane-based
gas, such as SiH.sub.4, Si.sub.2H.sub.6 or SiH.sub.2Cl.sub.2, and
O.sub.2 gas be used.
[0043] The first to third passivation layers 107, 108, and 109
function to prohibit oxidization of the gate electrode layer 105
due to heat occurring in subsequent processes, thus improving
device characteristics.
[0044] FIGS. 3A to 3D are sectional views illustrating a method of
fabricating a semiconductor device in accordance with a second
embodiment of the invention.
[0045] Referring to FIG. 3A, a tunnel insulating layer 201, a
conductive layer for a floating gate 202, a dielectric layer 203, a
conductive layer for a control gate 204, a gate electrode layer
205, and a hard mask layer 206 are sequentially stacked over a
semiconductor substrate 200.
[0046] Each of the conductive layer for the floating gate 202 and
the conductive layer for the control gate 204 preferably comprises
a polysilicon layer. The dielectric layer 203 preferably has an ONO
structure comprising a first oxide layer 203a, a nitride layer
203b, and a second oxide layer 203c. The gate electrode layer 205
preferably comprises a tungsten (W) layer.
[0047] The conductive layer for the floating gate 202 preferably
comprises a dual layer structure, including an amorphous
polysilicon layer not containing an impurity and a polysilicon
layer containing an impurity.
[0048] Although not shown in the drawings, after the conductive
layer for the control gate 204 is formed, a diffusion-prevention
layer may be formed before the gate electrode layer 205 is
formed.
[0049] The hard mask layer 206 preferably has a stack structure of
an SiON layer, an oxide layer, a nitride layer, and an amorphous
carbon layer.
[0050] Referring to FIG. 3B, after a photoresist pattern is formed
on the hard mask layer 206, an etch process using the photoresist
pattern is performed. That is, the hard mask layer 206 is
patterned.
[0051] The gate electrode layer 205 and the conductive layer for
the control gate 204 are patterned by an etch process using the
patterned hard mask layer 206 as an etch mask, thus forming primary
gate patterns 206 and 205. Here, a part of the conductive layer for
the control gate 204 preferably remains to prevent the dielectric
layer 203 from being exposed.
[0052] An etch process is then performed to etch exposed sidewalls
of the gate electrode layer 205.
[0053] The above etch process preferably is controlled in such a
manner that the sidewalls of the gate electrode layer 205 are
etched 1 nm to 13 nm. The etch process preferably is carried out
using a dry etch process or a wet etch process. The wet etch
process preferably is performed using H.sub.2SO.sub.4, NH.sub.4OH,
H.sub.2O, HF, HCl, or H.sub.2O.sub.2, either alone or in
combination. Accordingly, the width of the gate electrode layer 205
becomes narrower than that of the conductive layer for the control
gate 204.
[0054] Referring to FIG. 3C, a first passivation layer 207 is
formed on the conductive layer for the control gate 204, including
the primary gate patterns 206 and 205. The first passivation layer
207 preferably comprises a nitride layer or a dual layer of a
nitride layer and an oxide layer. The first passivation layer 207
preferably is formed using SiH.sub.4, Si.sub.2H.sub.6,
Si.sub.2HCl.sub.2, NH.sub.3, N.sub.2, Ar, He, or PH.sub.3 gas,
preferably in a pressure range of 0.05 Torr to 50 Torr.
[0055] Next, a cleaning process preferably is performed to remove
byproducts, which result from the etch process for forming the
primary gate patterns 206 and 205. The cleaning process preferably
is performed using a wet or dry cleaning process employing HF,
NH.sub.4OH, or H.sub.2SO.sub.4, either alone or in combination.
Byproducts are removed through the cleaning process, which can
prohibit the occurrence of a bird's beak phenomenon of the
dielectric layer 203 and the tunnel insulating layer 201 in
subsequent processes. At the time of the cleaning process, the gate
electrode layer 205 is protected by the first passivation layer
207, thus prohibiting an abnormal oxidization phenomenon.
[0056] The first passivation layer 207, the conductive layer for
the control gate 204, the dielectric layer 203, the conductive
layer for the floating gate 202, and the tunnel insulating layer
201 are etched to thereby form secondary gate patterns 206, 205,
204, 203, 202, and 201.
[0057] A selective oxidization process preferably is performed to
mitigate etch damage occurring at the time of the etch process. The
selective oxidization process preferably is performed using a mixed
O.sub.2, H.sub.2 gas.
[0058] A second passivation layer 208 is formed over the
semiconductor substrate 100, including the secondary gate patterns
206, 205, 204, 203, 202, and 201. The second passivation layer 208
preferably comprises an HTO layer, an LP-TEOS layer, or an ALD
oxide layer. In the case in which the second passivation layer 208
comprises an HTO layer, it may be preferred that a mixed gas of
silane-based gas, such as SiH.sub.4, Si.sub.2H.sub.6 or
SiH.sub.2Cl.sub.2, and O.sub.2 gas be used. The second passivation
layer 208 preferably comprises a nitride layer.
[0059] The first and second passivation layers 207, 208 function to
prohibit oxidization of the gate electrode layer 205 due to heat
occurring in subsequent processes, thus improving device
characteristics.
[0060] In accordance with the embodiments of the invention, in a
gate pattern formation process using a tungsten (W) layer as a gate
conductive layer, sidewalls of the tungsten layer are etched and a
passivation layer is then formed on the tungsten layer to protect
the sidewalls of the tungsten layer in a subsequent cleaning
process. Here, the passivation layer is formed on etched portions
of the tungsten layer. Accordingly, a distance between gates can be
secured and process margin can be secured in a subsequent gap-fill
process of insulating materials.
[0061] The embodiments disclosed herein have been proposed to allow
a person skilled in the art to easily implement the invention, and
the person skilled in the part may implement the invention by a
combination of these embodiments. Therefore, the scope of the
invention is not limited by or to the embodiments as described
above, and should be construed to be defined only by the appended
claims and their equivalents.
* * * * *