U.S. patent application number 12/114124 was filed with the patent office on 2009-11-05 for methods of forming capacitors.
Invention is credited to Vishwanath Bhat, Brett Busch, Farrell Good, Kevin Shea, Irina Vasilyeva.
Application Number | 20090275185 12/114124 |
Document ID | / |
Family ID | 41257382 |
Filed Date | 2009-11-05 |
United States Patent
Application |
20090275185 |
Kind Code |
A1 |
Shea; Kevin ; et
al. |
November 5, 2009 |
METHODS OF FORMING CAPACITORS
Abstract
A method of forming a capacitor includes providing material
having an opening therein over a node location on a substrate. A
shield is provided within and across the opening, with a void being
received within the opening above the shield and a void being
received within the opening below the shield. The shield comprises
a nitride. Etching is conducted within the opening through the
nitride-comprising shield. After the etching, a first capacitor
electrode is formed within the opening in electrical connection
with the node location. A capacitor dielectric and a second
capacitor electrode are formed operatively adjacent the first
capacitor electrode. Other aspects and implementations are
contemplated.
Inventors: |
Shea; Kevin; (Boise, ID)
; Busch; Brett; (Boise, ID) ; Good; Farrell;
(Meridian, ID) ; Vasilyeva; Irina; (Boise, ID)
; Bhat; Vishwanath; (Boise, ID) |
Correspondence
Address: |
WELLS ST. JOHN P.S.
601 W. FIRST AVENUE, SUITE 1300
SPOKANE
WA
99201
US
|
Family ID: |
41257382 |
Appl. No.: |
12/114124 |
Filed: |
May 2, 2008 |
Current U.S.
Class: |
438/381 ; 216/6;
257/E21.008; 427/79 |
Current CPC
Class: |
Y10T 156/10 20150115;
H01L 28/91 20130101; H01L 27/10852 20130101; H01L 27/10894
20130101 |
Class at
Publication: |
438/381 ; 216/6;
427/79; 257/E21.008 |
International
Class: |
H01L 21/02 20060101
H01L021/02 |
Claims
1. A method of forming a capacitor, comprising: providing material
having an opening therein over a node location on a substrate;
providing a shield within and across the opening with a void being
received within the opening above the shield and a void being
received within the opening below the shield, the shield comprising
a nitride-comprising material; etching within the opening through
the nitride-comprising shield; after the etching, forming a first
capacitor electrode within the opening in electrical connection
with the node location; and forming a capacitor dielectric and a
second capacitor electrode operatively adjacent the first capacitor
electrode.
2. The method of claim 1 wherein the nitride-comprising material
comprises at least one of silicon nitride, boron nitride, silicon
oxynitride, silicon boron nitride, and silicon carbon nitride.
3. A method of forming a capacitor, comprising: providing base
material having an opening therein over a node location on a
substrate; forming bridging material across the base material
opening, the base material opening comprising a void beneath the
bridging material, the bridging material comprising a
nitride-comprising material; forming covering material over the
base material and the nitride-comprising bridging material; etching
an opening through the covering material to the nitride-comprising
bridging material received across the base material opening;
etching through the nitride-comprising bridging material through
the covering material opening; forming a first capacitor electrode
within the covering material opening and within the base material
opening in electrical connection with the node location; and
forming a capacitor dielectric and a second capacitor electrode
operatively adjacent the first capacitor electrode.
4. The method of claim 3 comprising depositing the
nitride-comprising bridging material over the base material, and
forming the covering material over the nitrogen-comprising bridging
material which is received over the base material.
5. The method of claim 4 comprising after forming the first
capacitor electrode and before forming the capacitor dielectric and
the second capacitor electrode, etching the covering material to
expose the nitride-comprising bridging material received over the
base material, and forming the capacitor dielectric and the second
capacitor electrode over the nitride-comprising bridging
material.
6. The method of claim 5 comprising forming the capacitor
dielectric on the nitride-comprising bridging material.
7. The method of claim 5 comprising after etching the covering
material to expose the nitride-comprising bridging material
received over the base material and before forming the capacitor
dielectric and the second capacitor electrode, etching the base
material.
8. A method of forming a capacitor, comprising: providing base
material having an opening therein over a node location on a
substrate; depositing a bridging material over the base material
and across the base material opening, the base material opening
comprising a void beneath the bridging material; depositing
covering material over the bridging material that is received over
the base material and across the base material opening; etching an
opening through the covering material to the bridging material
received across the base material opening; etching through the
bridging material through the covering material opening; forming a
first capacitor electrode within the covering material opening and
within the base material opening in electrical connection with the
node location; and forming a capacitor dielectric and a second
capacitor electrode operatively adjacent the first capacitor
electrode.
9. The method of claim 8 wherein the bridging material is deposited
to be received partially within the base material opening.
10. The method of claim 8 wherein the bridging material comprises
silicon dioxide.
11. The method of claim 10 wherein the silicon dioxide is undoped
silicon dioxide.
12. The method of claim 10 wherein the base material comprises a
nitride received over doped silicon dioxide-comprising
material.
13. The method of claim 12 wherein the silicon dioxide-comprising
bridging material is received on the nitride.
14. The method of claim 8 wherein the bridging material comprises a
nitride comprising at least one of silicon nitride, boron nitride,
silicon oxynitride, silicon boron nitride, and silicon carbon
nitride.
15. The method of claim 14 wherein the bridging material comprises
silicon nitride.
16. The method of claim 14 wherein the bridging material comprises
boron nitride.
17. The method of claim 14 wherein the bridging material comprises
silicon oxynitride.
18. The method of claim 14 wherein the bridging material comprises
silicon boron nitride.
19. The method of claim 14 wherein the bridging material comprises
silicon carbon nitride.
20. The method of claim 8 wherein the etching an opening through
the covering material comprises using an etching chemistry to
extend the opening to the bridging material, the etching through
the bridging material comprising continuing without ceasing
processing of the substrate with the etching chemistry at the
conclusion of the etching of the opening through the covering
material effective to etch through the bridging material.
21. The method of claim 8 wherein the etching an opening through
the covering material comprises using an etching chemistry and
using etching conditions to extend the opening to the bridging
material, the etching through the bridging material consisting
essentially of continuing without ceasing processing of the
substrate with the etching chemistry and with the etching
conditions at the conclusion of the etching of the opening through
the covering material effective to etch through the bridging
material.
22. The method of claim 8 wherein the etching the bridging material
comprises changing one of etching chemistry and etching conditions
from those used in etching the covering material opening.
23. The method of claim 22 comprising changing etching
chemistry.
24. The method of claim 22 comprising changing etching
conditions.
25. The method of claim 22 comprising changing etching chemistry
and etching conditions.
26. A method of forming a capacitor, comprising: providing base
material having an opening therein over a node location on a
substrate, the base material comprising silicon dioxide doped with
at least one of boron and phosphorus; depositing a bridging
material over the base material and across the base material
opening, the base material opening comprising a void beneath the
bridging material, the bridging material comprising undoped silicon
dioxide; depositing covering material over the bridging material
that is received over the base material and across the base
material opening, the covering material comprising silicon dioxide
doped with at least one of boron and phosphorus; etching an opening
through the covering material to the bridging material received
across the base material opening using an etching chemistry, and
etching through the bridging material through the covering material
opening by continuing without ceasing processing of the substrate
with the etching chemistry at the conclusion of the etching of the
opening through the covering material; forming a first capacitor
electrode within the covering material opening and within the base
material opening in electrical connection with the node location;
and forming a capacitor dielectric and a second capacitor electrode
operatively adjacent the first capacitor electrode.
27. The method of claim 26 wherein the undoped silicon dioxide is
deposited on the silicon dioxide doped with at least one of boron
and phosphorus of the base material.
28. The method of claim 26 comprising after forming the first
capacitor electrode and before forming the capacitor dielectric and
the second capacitor electrode, etching the covering material and
the bridging material to expose the base material.
29. The method of claim 28 comprising after exposing the base
material, etching the base material before forming the capacitor
dielectric and the second capacitor electrode.
Description
TECHNICAL FIELD
[0001] Embodiments disclosed herein pertain to methods of forming
capacitors.
BACKGROUND
[0002] Capacitors are one type of component commonly used in the
fabrication of integrated circuits, for example in DRAM circuitry.
A capacitor is comprised of two conductive electrodes separated by
a non-conducting dielectric region. As integrated circuitry density
has increased, there is a continuing challenge to maintain
sufficiently high storage capacitance despite typical decreasing
capacitor area. The increase in density of integrated circuitry has
typically resulted in greater reduction in the horizontal dimension
of capacitors as compared to the vertical dimension. In many
instances, the vertical dimension of capacitors has increased.
[0003] One manner of fabricating capacitors is to initially form an
insulative material within which a capacitor storage node electrode
is formed. For example, an array of capacitor electrode openings
for individual capacitors may be fabricated in such insulative
capacitor electrode-forming material, with an example insulative
electrode-forming material being silicon dioxide doped with one or
both of phosphorus and boron. The capacitor electrode openings may
be formed by etching. It can be difficult to etch the capacitor
electrode openings within the insulative material, particularly
where the openings have high aspect ratio.
[0004] One manner of reducing such difficulty is to split the
deposition and etch of such openings into two or more combinations
of deposition and etch steps. For example, the material within
which the capacitor electrode openings are to be formed can be
deposited to an initial deposition thickness which is one half or
less of the desired ultimate deposition thickness. Shallower
capacitor electrode openings can then be etched to the underlying
node location. Such openings are subsequently completely
filled/plugged, and another material within which capacitor
electrode openings will be formed is deposited over the material in
which the first openings were formed and filled. Individual
capacitor electrode openings are then formed through the overlying
layer to the plugging material. Such can be repeated if desired.
Regardless, the plugging material is at some point etched from the
capacitor electrode openings to enable contact to be made to a node
location on the substrate.
[0005] One common plugging material used in such instances is
polysilicon. A native oxide can form on the outermost surfaces
thereof that can be difficult to remove. Such oxide can be removed
by etching prior to etching the polysilicon within the openings
from the substrate. The native oxide etch is usually conducted
using an HF wet etching solution. However, the material within
which the capacitor electrode openings are usually formed is a
doped silicon dioxide, such as borophosphosilicate glass or
phosphosilicate glass. The HF will etch such material, thereby
undesirably widening the capacitor electrode openings above the
plugging material while removing the native oxide received
thereover. Further and regardless, it can be difficult to remove
the polysilicon plugging material from the openings. Example
techniques in accordance with the above are described in U.S. Pat.
No. 6,365,453 and 6,204,143.
[0006] Further and regardless, it is often desirable to etch away
most if not all of the capacitor electrode-forming material after
individual capacitor electrodes have been formed within the
openings. Such enables outer sidewall surfaces of the electrodes to
provide increased area and thereby increased capacitance for the
capacitors being formed. However, the capacitor electrodes formed
in deep openings are often correspondingly much taller than they
are wide. This can lead to toppling of the capacitor electrodes,
either during the etching to expose the outer sidewalls surfaces,
during transport of the substrate, and/or during deposition of the
capacitor dielectric layer or outer capacitor electrode layer. U.S.
Pat. No. 6,667,502 teaches the provision of a brace or retaining
structure intended to alleviate such toppling. Other aspects
associated in the formation of a plurality of capacitors, some of
which include bracing structures, are also disclosed and are:
[0007] U.S. Published Application No. 2005/0051822; [0008] U.S.
Published Application No. 2005/0054159; [0009] U.S. Published
Application No. 2005/0158949; [0010] U.S. Published Application No.
2005/0287780; [0011] U.S. Published Application No. 2006/0014344;
[0012] U.S. Published Application No. 2006/0051918; [0013] U.S.
Published Application No. 2006/0046420; [0014] U.S. Published
Application No. 2006/0121672; [0015] U.S. Published Application No.
2006/0211211; [0016] U.S. Published Application No. 2006/0263968;
[0017] U.S. Published Application No. 2006/0261440; [0018] U.S.
Published Application No. 2007/0032014; [0019] U.S. Published
Application No. 2006/0063344; [0020] U.S. Published Application No.
2006/0063345.
[0021] Fabrication of capacitors in integrated circuitry such as
memory circuitry may form an array of capacitors within a capacitor
array area. Control or other circuitry area is often displaced from
the capacitor array area, with the substrate including an
intervening area between the capacitor array area and the control
or other circuitry area. In some instances, a trench is formed in
the intervening area between the capacitor array area and the other
circuitry area. Such trench can be formed commensurate with the
fabrication of the openings within the capacitor array area within
which the isolated capacitor electrodes will be received.
[0022] While the invention was motivated in addressing the
above-identified issues, it is no way so limited. The invention is
only limited by the accompanying claims as literally worded, and in
accordance with the doctrine of equivalence.
BRIEF DESCRIPTION OF THE DRAWINGS
[0023] FIG. 1 is a diagrammatic cross section of a substrate
fragment in process in accordance with an aspect of the
invention.
[0024] FIG. 2 is a diagrammatic top plan view of a larger scale
portion of the FIG. 1 substrate.
[0025] FIG. 3 is a view of the FIG. 1 substrate at a processing
step subsequent to that shown by FIG. 1, and taken through line 3-3
in FIG. 4.
[0026] FIG. 4 is a diagrammatic top plan view of the FIG. 3
substrate fragment.
[0027] FIG. 5 is a view of the FIG. 3 substrate at a processing
step subsequent to that shown by FIG. 3.
[0028] FIG. 6 is a view of an alternate embodiment substrate to
that shown by FIG. 5.
[0029] FIG. 7 is a view of the FIG. 5 substrate at a processing
step subsequent to that shown by FIG. 5.
[0030] FIG. 8 is a view of the FIG. 7 substrate at a processing
step subsequent to that shown by FIG. 7.
[0031] FIG. 9 is a view of the FIG. 8 substrate at a processing
step subsequent to that shown by FIG. 8.
[0032] FIG. 10 is a view of the FIG. 9 substrate at a processing
step subsequent to that shown by FIG. 9.
[0033] FIG. 11 is a view of the FIG. 10 substrate at a processing
step subsequent to that shown by FIG. 10.
[0034] FIG. 12 is a view of the FIG. 11 substrate at a processing
step subsequent to that shown by FIG. 11, and taken through line
12-12 in FIG. 13.
[0035] FIG. 13 is a diagrammatic top plan view of the FIG. 12
substrate fragment.
[0036] FIG. 14 is a view of the FIG. 12 substrate at a processing
step subsequent to that shown by FIG. 12.
[0037] FIG. 15 is a view of an alternate embodiment substrate to
that shown by FIG. 14.
[0038] FIG. 16 is a view of the FIG. 15 substrate at a processing
step subsequent to that shown by FIG. 15.
[0039] FIG. 17 is a diagrammatic representation of DRAM
circuitry.
DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS
[0040] Example methods of forming capacitors, including pluralities
of capacitors, are described with reference to FIGS. 1-17.
Referring initially to FIGS. 1 and 2, a substrate, for example a
semiconductor substrate, is indicated generally with reference
numeral 10. In the context of this document, the term
"semiconductor substrate" or "semiconductive substrate" is defined
to mean any construction comprising semiconductive material,
including, but not limited to, bulk semiconductive materials such
as a semiconductive wafer (either alone or in assemblies comprising
other materials thereon), and semiconductive material layers
(either alone or in assemblies comprising other materials). The
term "substrate" refers to any supporting structure, including, but
not limited to, the semiconductive substrates described above.
Accordingly, and by way of example only, FIG. 1 might comprise a
bulk semiconductor material (not shown), for example bulk
monocrystalline, and/or comprise semiconductor-on-insulator
layers.
[0041] Substrate 10 can be considered as comprising a capacitor
array area 25, a circuitry area 75 other than capacitor array area
25, and an intervening area 50 between capacitor array area 25 and
circuitry area 75. In the depicted example embodiment, intervening
area 50 completely surrounds and encircles capacitor array area 25
(FIG. 2), and circuitry area 75 comprises a peripheral circuitry
area to that of capacitor array area 25. Alternate constructions
are contemplated, of course, for example whereby neither
intervening area 50 nor circuitry area 75 completely or partially
encircles a capacitor array area 25.
[0042] FIG. 1 depicts an insulative material 12 having electrically
conductive storage node pillars 14 formed therethrough. Materials
12 and 14 may be fabricated over some suitable underlying material,
for example bulk monocrystalline and/or underlying circuitry.
Example insulative materials 12 include doped and undoped silicon
dioxides, for example silicon dioxide deposited by the
decomposition of tetraethylorthosilicate (TEOS) and/or
borophosphosilicate glass (BPSG) and/or silicon nitride. In the
context of this document, "doped silicon dioxide" or "silicon
dioxide doped" requires at least 0.5 atomic percent concentration
of one or a combination of boron or phosphorus in silicon dioxide.
Further, an undoped silicon dioxide requires less than 0.5 atomic
percent of any of boron and phosphorous. Alternately by way of
example only, material 12 might comprise anisotropically etched
insulative sidewall spacers, for example formed about transistor
gate lines (not shown). An example material 14 is conductively
doped polysilicon. Conductive material 14 can be considered as
comprising or defining a plurality of capacitor storage node
locations 15, 16, 17 and 18 on substrate 10. Storage node locations
15, 16, 17 and 18 are examples only, and regardless, may be
conductive at this point in the process, or made conductive
subsequently.
[0043] A material 22 has been formed over material 12 and capacitor
storage node locations 15, 16, 17 and 18. Examples for material 22
comprise silicon nitride and/or undoped silicon dioxide deposited
to an example thickness range of from about 100 Angstroms to about
2,000 Angstroms. Material 22 might be included to provide an etch
stop, or other function.
[0044] Some material 24 is received over capacitor array area 25
and circuitry area 75, and also in the depicted embodiment over
intervening area 50. Such might be homogeneous or comprise multiple
different compositions and/or layers. An example material is doped
silicon dioxide, for example comprising at least one of phosphorus
and boron, such as BPSG, borosilicate glass (BSG), and/or
phosphosilicate glass (PSG). An example thickness range for
material 24 is from 5,000 Angstroms to 10 microns, with 2 microns
being a specific example. Thinner and greater thicknesses are, of
course, contemplated. Regardless and in one embodiment, layers 22
and 24 comprise example base material 27 received over node
locations 15, 16, 17 and 18.
[0045] Referring to FIGS. 3 and 4, a plurality of openings 28 has
been etched into base material 27 over individual node locations
15, 16, 17 and 18. Further, a trench 30 has been formed in
intervening area 50 within base material 27. In one embodiment,
trench 30 completely surrounds capacitor area 25, an example
technique for forming capacitor electrode openings 28 and trench 30
comprises photolithographic patterning and selective anisotropic
dry etch to produce the example FIGS. 3 and 4 constructions. An
example minimum width of trench opening 30 is from about 200
Angstroms to about 5,000 Angstroms, while an example minimum width
for capacitor electrode openings 28 is also from about 200
Angstroms to about 5,000 Angstroms. Trench 30 may or may not be
formed at this point in the process, or at all. Regardless, the
processing depicted by FIGS. 1-4 depicts but one example method of
providing a material (i.e. material 27) having an opening therein
(i.e. any of openings 28) over a node location (i.e. any of
locations 15, 16, 17 and 18) on a substrate. The opening(s) may or
may not extend completely to the node locations at this point in
the process. Regardless in one embodiment, the processing depicted
by FIGS. 3 and 4 can occur in a suitable processing tool which for
convenience in description can be considered as a "first processing
tool". In one embodiment the first processing tool may be a plasma
etcher. By way of example only, a LAM.TM. Exelan.TM. oxide etch
tool is an example such tool.
[0046] Referring to FIG. 5, bridging material 32 has been formed
across base material openings 28, with such openings 28 comprising
voids 33 therebeneath. In one embodiment, such occurs by depositing
bridging material 32 over base material 27 and across base material
openings 28, and in one embodiment to partially within base
material openings 28 as shown. In one embodiment, such occurs in
the very same first processing tool within which the etching to
produce openings 28 in FIGS. 3 and 4 occurred, and in one
embodiment before removing substrate 10 from such processing tool
after such etching to produce openings 28. By way of examples only,
example bridging materials include nitride-comprising material, for
example one or more of silicon nitride, boron nitride, silicon
oxynitride, silicon boron nitride, and silicon carbon nitride.
Further additionally or alternately and by way of examples only,
the bridging material might comprise silicon dioxide, including
doped and undoped silicon dioxide. In one embodiment, the base
material comprises doped silicon dioxide with a nitride received
thereover, and silicon dioxide-comprising bridging material
received over the nitride of the base material. Such is shown by
way of example only with respect to a substrate fragment 10a in
FIG. 6. Like numerals form the first described embodiment are
utilized where appropriate, with differences being indicated with
different numerals or the suffix "a". In FIG. 6, substrate 10a
comprises a nitride layer 19 (for example any of the above stated
nitrides) received over layer 24 as constituting part of base
material 27a. In the depicted embodiment, nitride layer 19 is
received "on" (with "on" meaning herein in at least some direct
physical touching contact with) layer 24. In one embodiment, such
as shown in FIG. 5 and where an outermost portion of material 24
comprises doped silicon dioxide and an innermost portion of
bridging material 32 comprises undoped silicon dioxide, undoped
silicon dioxide of bridging material 32 is formed on doped silicon
dioxide of base material 27.
[0047] Regardless, these and/or other materials can be deposited by
any existing or yet-to-be developed techniques. Example
silicon-containing precursors for chemical or atomic layer
deposition include SiH.sub.4, SiCl.sub.4, SiCl.sub.2H.sub.2, and
SiF.sub.4. Example nitrogen-containing precursors include NH.sub.3,
NO.sub.x, and N.sub.2. An example boron-containing precursor is
B.sub.2H.sub.6. Example carbon-containing precursors include
CH.sub.4, CF.sub.4, CH.sub.2F.sub.2, CHF.sub.3, CH.sub.3F,
C.sub.4F.sub.6, C.sub.4F.sub.8, C.sub.2F.sub.4, and C.sub.6.
Example conditions during deposition within a plasma etcher or a
plasma deposition tool include a chuck temperature of from
300.degree. C. to 500.degree. C., pressure from 10 mTorr to 10
Torr, total power of from 500 watts to 2,000 watts and frequencies
at one or a combination of 2 MHz and 27 MHz. Regardless, quantity
of the atomic components of the composition of bridging material 32
can be controlled by quantity of precursor gases depending on the
ultimate desired composition of bridging material 32. Bridging
material 32 might be homogenous or non-homogenous.
[0048] Referring to FIG. 7 and in one embodiment, covering material
34 has been formed over those portions of bridging material 32 that
are received over base material 27 and across base material
openings 28. Such might be homogenous or non-homogenous, and
regardless may comprise multiple layers. FIG. 7 depicts covering
material 34 as comprising four layers 36, 37, 38, and 39. Any of
such materials may be the same or different in composition as one
or more components of base material 27. An example material 36 is
doped silicon dioxide, an example material 37 comprises silicon
nitride, and example materials for layers 38 and 39 include one or
more different organic and/or inorganic antireflective coating
layers.
[0049] Referring to FIG. 8, openings 40 have been etched through
covering material 34 to bridging material 32 received across
openings 28. First capacitor electrodes will ultimately be formed
therein as is described below. A trench 42, corresponding in
general outline to trench 30, is also shown as having been etched
through covering material 34 to bridging material 32. Openings 40
and trench 42 are shown as being the same size, shape, and exactly
aligned with the respective openings 28 and trench 30 over which
such lie. However, such may be of different such size and shape,
and regardless may not exactly align over the underlying openings
and trench.
[0050] Referring to FIG. 9, bridging material 32 has been etched
through, through the covering material openings 40 and 42.
[0051] In one embodiment, the depicted etching of covering material
openings 40 in FIG. 8 is conducted in a suitable processing tool
which for convenience in description can be considered as a "second
processing tool". In one embodiment, the second processing tool may
be a plasma etcher, for example and by way of example only the LAM
Exelan etcher referred to above. Regardless in one embodiment, the
FIG. 9 etching is conducted within the very same processing tool
used to form covering material openings 40 in FIG. 8, and in one
embodiment before removing substrate 10 therefrom after etching
such covering material openings 40. In one embodiment, the second
processing tool may be the very same first processing tool as
described above in the one example embodiment where the FIGS. 3, 4,
and 5 processing occurred in the same processing tool. Alternately
and by way of example only, the first and second processing tools
might be different tools, and whether of the same make and model or
of different makes and/or models.
[0052] In one embodiment, etching of openings 40 through covering
material 34 will comprise some suitable etching chemistry which
extends the openings to bridging material 32, for example as is
shown in FIG. 8. Where, for example, covering material 34 comprises
multiple different compositions, some suitable etching chemistry
will be used to extend openings 40 to bridging material 32 through
the last portion of such covering material 34, for example through
depicted layer 36. Different chemistries and/or etching conditions
might be used for etching the materials received above layer 36.
Regardless, where portion 36 of covering material 34 comprises PSG,
an example etching chemistry to etch portion 36 and to produce the
FIG. 8 construction includes a combination of C.sub.4F.sub.8,
O.sub.2 and Ar. Regardless, in one embodiment, the act of etching
through bridging material 32 as depicted in FIG. 9 comprises
continuing, without ceasing, the processing of substrate 10 with
the etching chemistry at the conclusion of the etching of openings
40 through covering material 34 as depicted in FIG. 8 effective to
etch through bridging material 32 as shown by way of example in
FIG. 9. Such may can occur in one embodiment when bridging material
32 is of the same or similar composition to that of material 36,
and/or where bridging material 32 is sufficiently thin that
punching therethrough can occur without necessarily changing
etching chemistry. In one embodiment, such etching also consists
essentially of continuing the processing, without ceasing, (for
example of the substrate of FIG. 8) to produce the example
substrate of FIG. 9 also using the very same etching conditions
(meaning the combination of pressure, temperature, and any applied
power) that were in use at the conclusion of the etching to produce
the example FIG. 8 construction. Alternately, materials 36 and 32
may be of different inherent compositions, but capable of being
etched with the same etching chemistry.
[0053] Alternately and likely where bridging material 32 comprises
a material etchably different in composition from that of material
36, etching of bridging material 32 can comprise changing one or
more of etching chemistry and etching conditions from those used in
etching covering material openings 40.
[0054] Referring to FIG. 10, a conductive layer 52, for example
titanium nitride, has been deposited to within covering material
openings 40 and within base material openings 28 in electrical
connection with node locations 15, 16, 17 and 18.
[0055] Referring to FIG. 11, conductive layer 52 and layers 38 and
39 have been etched or polished back to layer 37. Such provides, by
way of example only, one manner of forming respective first
capacitor electrodes 55 within covering material openings 40 and
within the base material openings in electrical connection with
node locations 15, 16, 17 and 18. The depicted first capacitor
electrodes 55 are shown as being container in shape, but could of
course be of other configurations whether existing or yet-to-be
developed, including for example completely plugging the depicted
capacitor openings.
[0056] Referring to FIGS. 12 and 13, etch access openings 45 have
been formed through masking layer 37 within capacitor array area 25
effective to expose material 36 of the covering material within
capacitor array area 25. Such leaves elevationally outermost
surfaces of material 36 within circuitry area 75 completely covered
by masking layer 37. Etch openings 45 provide access for etchant to
subsequently etch materials 36 and 34 within capacitor array area
25, if such is desired. Alternately by way of example only, it
might be decided/desired to not etch material 36 in which event
openings 45 might not be formed and masking layer 37 might not be
used.
[0057] Referring to FIG. 14, materials 36, 32, and 24 within
capacitor array area 25 have been etched, for example with a liquid
etching solution. FIG. 14 depicts but one embodiment wherein one of
more etching chemistries has etched all of materials 36, 32 and 24
from within capacitor array area 25. Alternately, less than all or
only some of one or more of materials 36, 32 and 24 might be
etched. Further and regardless, any etching thereof might be
conducted dry or with liquid. An example liquid etchant solution is
aqueous, and regardless for example comprising HF, where one or
more of materials 36, 32, and 24 is an oxide. One example solution
comprises 5:1 to 20:1 water to HF by volume, wherein said HF is a
42 weight percent solution of HF in water. An example etching
temperature is room ambient, with an example etching pressure also
being room ambient. An example wet etching chemistry that will etch
nitride-comprising materials includes H.sub.3PO.sub.4. Further and
accordingly where for example materials 36 and 24 are predominantly
silicon dioxide-comprising and bridging material 32 is
predominantly silicon nitride-comprising, etching chemistry might
be changed one or more times to completely remove materials 36, 32,
and 24 where such removal is desired. Regardless, compositions of
material 32 and material 37 may be selected to be etchably
different and/or of different thicknesses where it is desired that
material 37 mask material 36 within periphery circuitry area 75
from being etched.
[0058] FIG. 15 illustrates an alternate embodiment to that of FIG.
14 with respect to a substrate fragment 10b. Like numerals from the
above described embodiments are utilized where appropriate, with
differences being indicated with different numerals or the suffix
"b". In FIG. 15, at least some of bridging material 32 remains
between adjacent capacitor electrodes 55. Material 24 is also shown
as having been etched away within array area 25, but alternately
some or all of such may remain. Regardless, bridging material 32
might function as a supporting bracing or lattice structure if such
remains in the finished circuitry construction. Where it is desired
to keep some or all of bridging material 32 and remove some or all
of material 24 within array area 25, portions of bridging material
may be etched through to provide etch access to material 24, for
example much like formation of etch openings 45 in layer 37.
[0059] Referring to FIG. 16, a capacitor dielectric and a second
capacitor electrode are formed operatively adjacent the first
capacitor electrode with respect to individual capacitors. For
example and by way of example only, FIG. 16 depicts the deposition
of a capacitor dielectric layer 60. By way of example only, example
materials are silicon dioxide, silicon nitride, silicon dioxide and
silicon nitride composite, or any suitable high-k dielectric, and
whether existing or yet-to-be developed. By way of example only,
high-k dielectrics include Ta.sub.2O.sub.5 and barium strontium
titanate.
[0060] An outer capacitor electrode layer 70 has been deposited
over capacitor dielectric layer 60, thereby defining capacitors 81,
82, 83 and 84. Such are depicted as comprising a common cell
capacitor plate to all of the depicted capacitors, for example as
might be utilized in DRAM or other circuitry. For example and by
way of example only, FIG. 17 depicts an example DRAM cell
incorporating capacitor 81. Such comprises an example transistor
gate word line 87 having insulative sidewall spacers, and
insulative cap, and a conductive region under the cap such as
silicide, a conductive polysilicon region under the silicide, and a
gate dielectric region under the polysilicon. Source/drain regions
80 are shown formed within semiconductive material operatively
proximate word line 87. One of such electrically connects with
capacitor 81, and another of such electrically connects with
bitline 85.
[0061] Regardless and by way of example only, in one embodiment
where bridging material 32 comprises nitride, covering material 34
can be etched to expose the nitride-comprising bridging material,
with capacitor dielectric 60 and second capacitor electrode 70
being formed thereover. In one embodiment and as shown, capacitor
dielectric 60 is formed on nitride-comprising bridging material 32.
Regardless in one embodiment, after etching covering material 34 to
expose nitride-comprising bridging material 32 received over base
material 27 and before forming capacitor dielectric 60 and second
capacitor electrode 70, the base material 27 may be etched, for
example in whole or in part.
[0062] In one embodiment, a method of forming a capacitor comprises
providing material having an opening therein over a node location
on a substrate. A shield comprising nitride-comprising material is
provided within and across the opening, with a void being received
within the opening above the shield and a void being received
within the opening below the shield. By way of example only, FIG. 8
is an example such opening if considering a single of one of the
covering material openings 40 in combination with a single of one
of the base material openings 28 immediately therebelow, with
material 32 being provided within and across such opening. The
space depicted above material 32 constitutes one example void
received within the opening above a shield, and the space within
the opening below shield material 32 constitutes another example
void.
[0063] Etching is conducted within such opening through the shield,
with FIG. 9 in but one example depicting an example such etching.
After such etching, a first capacitor electrode is formed within
the opening in electrical connection with the node location. A
capacitor dielectric and a second capacitor electrode are formed
operatively adjacent the first capacitor electrode, for example as
described above. Any of the above described processing might be
utilized in the context of such a method of forming a
capacitor.
[0064] In compliance with the statute, the subject matter disclosed
herein has been described in language more or less specific as to
structural and methodical features. It is to be understood,
however, that the claims are not limited to the specific features
shown and described, since the means herein disclosed comprise
example embodiments. The claims are thus to be afforded full scope
as literally worded, and to be appropriately interpreted in
accordance with the doctrine of equivalents.
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