U.S. patent application number 12/268281 was filed with the patent office on 2009-10-15 for programmable array logic circuit employing non-volatile ferromagnetic memory cells.
This patent application is currently assigned to ESTANCIA LIMITED. Invention is credited to Richard M. LIENAU.
Application Number | 20090256588 12/268281 |
Document ID | / |
Family ID | 34748652 |
Filed Date | 2009-10-15 |
United States Patent
Application |
20090256588 |
Kind Code |
A1 |
LIENAU; Richard M. |
October 15, 2009 |
PROGRAMMABLE ARRAY LOGIC CIRCUIT EMPLOYING NON-VOLATILE
FERROMAGNETIC MEMORY CELLS
Abstract
A programmable array logic circuit whose temporary memory
circuitry employs single bit non-volatile ferromagnetic memory
cells. The ferromagnetic memory cells or bits store data even when
there is no power provided to the circuitry, thus saving power
during operation of the programmable logic circuitry, and ensuring
that there is no loss of the data should there be a temporary power
shut down. Additionally, the ferromagnetic cells provide for
indefinite number of switching actions on the data without
degradation to the capacity to store data therein. The invention
provides an integrated circuit, comprising a programmable logic
circuit array having product lines and input lines therein, and a
storage register circuit. The storage register circuit has a
ferromagnetic bit and sensor coupled to store a remnant control
signal and an output transistor, coupled to be responsive to the
remnant control signal on its gate, and coupled between an input
and product line. Additionally, the integrated circuit may further
include a logical AND array and a logical OR array.
Inventors: |
LIENAU; Richard M.; (Pecos,
NM) |
Correspondence
Address: |
MORGAN LEWIS & BOCKIUS LLP
1111 PENNSYLVANIA AVENUE NW
WASHINGTON
DC
20004
US
|
Assignee: |
ESTANCIA LIMITED
Toronto
CA
PAGEANT TECHNOLOGIES, INC.
|
Family ID: |
34748652 |
Appl. No.: |
12/268281 |
Filed: |
November 10, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11889908 |
Aug 17, 2007 |
7463058 |
|
|
12268281 |
|
|
|
|
11580064 |
Oct 13, 2006 |
7285983 |
|
|
11889908 |
|
|
|
|
11037696 |
Jan 18, 2005 |
7123050 |
|
|
11580064 |
|
|
|
|
10239133 |
Sep 19, 2002 |
6864711 |
|
|
PCT/US01/01793 |
Jan 20, 2001 |
|
|
|
11037696 |
|
|
|
|
60177533 |
Jan 21, 2000 |
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Current U.S.
Class: |
326/38 ;
326/41 |
Current CPC
Class: |
H03K 17/6871 20130101;
G11C 7/22 20130101; G11C 11/18 20130101; H03K 19/177 20130101; H03K
19/17736 20130101; H03K 19/17772 20130101; H03K 19/17784 20130101;
G11C 11/15 20130101; G11C 2207/2227 20130101; H03K 19/1776
20130101; H03K 19/1778 20130101 |
Class at
Publication: |
326/38 ;
326/41 |
International
Class: |
H03K 19/173 20060101
H03K019/173 |
Claims
1-2. (canceled)
3. An integrated circuit, comprising: a) A programmable logic
circuit array having product lines and input lines therein; and b)
a storage register circuit, having i) a ferromagnetic bit and
sensor coupled to store a remnant control signal; ii) a write drive
coil; and iii) an output switch.
4. The integrated circuit of claim 1, wherein the ferromagnetic bit
is at least partially surrounded by the write drive coil to set the
polarity of the ferromagnetic bit.
5. The integrated circuit of claim 1 wherein the output switch is
coupled to be responsive to the remnant control signal, and coupled
between an input line and a product line.
6. The integrated circuit of claim 1, wherein the storage register
circuit further includes a sensor positioned proximate to the
ferromagnetic bit, to sense the polarity of the ferromagnetic hit
and to create the remnant control signal therefrom.
7. The integrated circuit of claim 4, wherein the output switch is
a transistor having a gate controlled by the remnant control
signal.
8. The integrated circuit of claim 4, wherein the programmable
logic array further comprises a logical AND array.
9. The integrated circuit of claim 4, wherein the programmable
logic array further comprises a logical OR array.
10. The integrated circuit of claim 4, wherein the ferromagnetic
bit has a height that is greater than its width.
11. The integrated circuit of claim 8, wherein the storage register
circuit has a supporting substrate to support the ferromagnetic bit
to have the height oriented perpendicular thereto.
12. The integrated circuit of claim 9, wherein the sensor is
located below the ferromagnetic bit and above the substrate.
13. The integrated circuit of claim 1, wherein the storage register
circuit has a set and reset input to program the remnant control
signal that is to be stored in the ferromagnetic bit.
14. The integrated circuit of claim 1, wherein the write drive coil
is bi-directional.
Description
[0001] This application is a continuation of co-pending U.S.
application Ser. No. 11/889,908, which was filed Aug. 17, 2007, and
is allowed, which is a continuation of U.S. application Ser. No.
11/580,064, which was filed Oct. 13, 2006 and issued as U.S. Pat.
No. 7,285,983, which is a continuation of U.S. application Ser. No.
11/037,696, which was filed on Jan. 18, 2005 and issued as U.S.
Pat. No. 7,123,050, which is a divisional of U.S. application Ser.
No. 10/239,133, which was filed Jan. 20, 2001 and issued as U.S.
Pat. No. 6,864,711, which was a U.S. national phase of
International Application Number PCT/US01/01793, which was filed
Jan. 20, 2001, which claims the benefit of No. 60/177,533 filed
Jan. 21, 2000.
BACKGROUND OF THE INVENTION
[0002] 1. The Field of the Invention
[0003] The present invention relates generally to a programmable
array logic circuit employing non-volatile ferromagnetic memory
cells. More particularly, the present invention uses a non-volatile
ferromagnetic memory cell to temporarily store binary data.
[0004] 2. The Background Art
[0005] Programmable logic devices have any number product sets,
usually in groups of four (4), eight (8), sixteen (16) or more
bits, although of ten in groups often (10). The arrays are
programmed for application-specific tasks to be performed within
digital electronic circuits. The fusible link types cannot be
re-programmed, but those employing EEPROM and Flash can. For those
PALs which use fusible links, the data in the "D" registers is lost
at power off. For those that use EEPROM and Flash as replacements
for the "D" registers, data is not lost at power off time.
[0006] Up to the present, traditional PALs have used "D" type
flip-flops for product registers. Lately, however, some fabricators
have begun using EEPROM and Flash technology to replace these.
These last two technologies have draw-backs, however. EEPROMs are
cumbersome to re-program, both are slow to re-program, exhibit
"write fatigue," thereby limiting their useful life, and must be
mass-written to re-program.
SUMMARY OF THE INVENTION
[0007] It has been recognized that it would be advantageous to
develop a programmable array logic circuit whose temporary memory
circuitry employs single bit non-volatile ferromagnetic memory
cells.
[0008] It is an advantage of the invention to have the
ferromagnetic memory cells or bits to store data even when there is
no power provided to the circuitry. Thus, saving power during
operation of the programmable logic circuitry, and ensuring that
there is no loss of the data should there be a temporary power shut
down.
[0009] Additionally, the ferromagnetic cells provide for indefinite
number of switching actions on the data without degradation to the
capacity to store data therein.
[0010] The invention provides an integrated circuit, comprising a
programmable logic circuit array having product lines and input
lines therein, and a storage register circuit. The storage register
circuit has a ferromagnetic bit and sensor coupled to store a
remnant control signal, and an output transistor, coupled to be
responsive to the remnant control signal on its gate, and coupled
between an input and product line.
[0011] Additionally, the integrated circuit may further include a
logical AND array and a logical OR array.
[0012] Additional features and advantages of the invention will be
set forth in the detailed description which follows, taken in
conjunction with the accompanying drawing, which together
illustrate by way of example, the features of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a schematic of a preferred embodiment of the
present invention.
[0014] FIG. 2 is a schematic of a preferred embodiment of the
present invention.
[0015] FIG. 3 is a cross sectional view of a single ferromagnetic
memory bit.
[0016] FIG. 4 is a schematic of a field programmable logic device
capable of utilizing the present invention.
DETAILED DESCRIPTION
[0017] For the purposes of promoting an understanding of the
principles of the invention, reference will now be made to the
exemplary embodiments illustrated in the drawings, and specific
language will be used to describe the same. It will nevertheless be
understood that no limitation of the scope of the invention is
thereby intended. Any alterations and further modifications of the
inventive features illustrated herein, and any additional
applications of the principles of the invention as illustrated
herein, which would occur to one skilled in the relevant art and
having possession of this disclosure, are to be considered within
the scope of the invention.
[0018] For the purpose of providing background material which may
in some respects illustrate the state of the art, the following
books are herein incorporated by reference for non-essential
material: "Programmable Logic Handbook," fourth edition, by
Monolithic Memories Inc., 2175 Mission College Blvd., Santa Clara,
Calif.; and "Practical Design Using Programmable Logic," by D.
Pellerin and M. Holley, Prentice Hall, library of Congress no.
TK7872.L64 1991.
[0019] The following United States patents are herein incorporated
by reference for their supporting teachings:
[0020] U.S. Pat. No. 5,300,830, is a programmable logic device
macrocell with an exclusive feedback and exclusive external input
lines for registered and combinatorial modes using a dedicated
product term for control.
[0021] U.S. Pat. No. 5,287,017, is a programmable logic device
macrocell with two OR array inputs.
[0022] U.S. Pat. No. 5,324,998, is a zero power re-programmable
flash cell for a programmable logic device.
[0023] U.S. Pat. No. 5,295,097, is a nonvolatile random access
memory.
[0024] U.S. Pat. No. 5,867,049, is a zero setup time flip flop.
[0025] U.S. Pat. No. 5,298,803, is a programmable logic device
having low power microcells with selectable registered and
combinatorial output signals.
[0026] The invention is used in the normal arena in which PALs are
employed, but where it may be advantageous to retain the last data
stored after removal of power to the circuit as well as the
simplicity of random re-programming. This PAL circuit could be in
all manner of digital circuitry, including computers, robotics,
telephonics, automotive circuits, security devices, and so on. The
advantages over prior art lie principally in that PAL devices using
ferromagnetic digital memory cells for product registers would
enjoy non-volatility, high-speed in situ random re-programmability
and indefinite long life span.
[0027] A PAL having product registers (flip flops) that use
non-volatile ferromagnetic memory/storage cells for product storage
registers is described wherein the non-volatile ferromagnetic
memory cells, comprised of single stick-like ferromagnets whose
aspect ratio is greater than 1:1 (height to width), are fabricated
normal to the plane of the substrate with a sensor centered
intimate to, and at one end of the ferromagnets are used for these
functions. The magnetic polarity of each ferromagnetic memory cell
bit is coerced into reversal using write, or state change
circuitry, comprised of a coil which surrounds, up to and including
270.degree., and is intimate to, the ferromagnetic stick. The write
current in each coil is bi-directional, depending on the desired
magnetic movement, or polarity, of the bit. The output of the
sensor reflects the binary condition of the bit, and is used as
binary data output for product registers.
[0028] FIG. 1 is a schematic of a dual output storage register 9,
or flip-flop, which is comprised of a ferromagnetic memory cell
consisting of micron or sub-micron-sized ferromagnetic bit whose
aspect ratio is greater than 1:1 (i.e., 2:1, etc.), deposited
normal to the plane of the substrate with its attendant support
circuitry. Uniquely, there is a ferromagnetic stick (bit) 1, which
is at least partially, but not necessarily completely, surrounded
by a write drive coil 2. The bi-directional current in the write
drive coil sets the polarity of the bit and is switched by two sets
of transistor pairs, or switches. The first transistor pair being
Q3 and Q6, having reference number 4a, and the second pair being Q4
and Q5 having reference number 4b. These switches are in turn gated
by Q1 and Q2, having reference number 8, both of which are "on"
when either of the SET 25 or RESET 26 lines are inactive, or
positive in polarity. Q7 and Q8, reference number 7, are the SET
and RESET switches. When one or the other of the SET or RESET lines
is appropriately pulsed, the associated gate is opened to allow
ground to be coupled to line 20 or 21 and thus pulling them
low.
[0029] On a second portion of the flip-flop 9, or storage register
circuit, there is a ferromagnetic bit field sensor 3, which is
capable of sensing remnant polarity stored in the bit 1. It is
noted that the dashed line is meant to illustrate the fact the
sensor 3 is to be physically located proximate the top or bottom of
the ferromagnetic bit 1, but is illustrated at a spaced
relationship for schematic purposes only and not meant to
illustrate physical layout as is shown in FIG. 3. Wherein,
amplifier U1, having reference number 5, responds to the signal
based on the Hall voltage that appears across the sensor 3. The
outputs are fed to an output transistor Q9, having reference number
6, which in turn allows input line 22 to be coupled to product line
23 when the output of the storage register 9 opens the gate on the
output transistor Q9.
[0030] Since the ferromagnetic bit does not change state when power
to the circuit is off, when power has thereafter been restored
subsequent to a power off, the storage registers will have retained
their critical data. Additionally, even while there is power to the
programmable logic device, it is noted that additional power is not
required to maintain the stored state in the flip-flop 9, thus,
saving overall power consumption.
[0031] FIG. 2 is a representation of the "SR" type register or
flip-flop 9 of FIG. 1 and is connected to the product circuitry of
a typical PAL product array 24. It is noted that one skilled in the
art will easily realize that the bit 1 will store a remnant
polarity in the material that the sensor 3 will sense. Thus,
creating a remnant control signal that will cause the amplifier 5
to constantly open or close the gate of output transistor 6. Where
the polarity of the bit will exist even after the power to the
circuitry has been turned off. Thus, to read the product line
signal, it is only needed to provide power to the amplifier 5.
Where to change the remnant polarity, the SET and RESET control
circuitry is needed to be activated.
[0032] FIG. 3 depicts, for example, a potential cross-section of a
micron or sub-micron scale ferromagnetic memory cell with the
sensor shown on the bottom; however, the sensor can be on the top
as well. There is no functional difference between these
configurations. They demonstrate that either construction can be
employed. There is a ferromagnetic storage element 11, or "bit," a
sensor 12, a sample drive line 14, which is made of Al, Cu or any
other suitable conductor material. Additionally there is a cutaway
of the set (write) drive coil 13 that wraps around bit 1. In this
depiction, matrix interconnects are not shown for the sake of
clarity. The entire memory cell rests on substrate 19, which can be
silicon, glass, GaAs, or other suitable material. Insulation layer
15 resides between the ferromagnetic bit 11 and the set coil 13.
Insulation layer 15 can be of a material such as SiO 2 or Si3N4,
etc. There is an overall insulation sections 16, 17 and 18, again
made of SiO2, Si3N4, or other suitable material.
[0033] It is noted that there are currently several designs that
are currently being developed by the current inventive entity
regarding the layout of the ferromagnetic bit and its accompanying
sensing circuitry that will be functionally equivalent to the
circuitry disclosed in FIG. 3.
[0034] Several methods may be employed to make this cell,
including, but not limited to, electroplating, sputtering, E-beam
deposition, chemical vapor deposition and molecular beam
epitaxy.
[0035] Referring to FIG. 4, there is an embodiment of the invention
being utilized in a field programmable logic device. One skilled in
the art will recognize that there is a programmable AND array with
inputs and outputs. Similarly, there are two programmable OR arrays
that route signals through various levels or numbers of logical OR
gates before the sum of products are sent to designated macrocells.
It is noted that the intersections of the AND and OR arrays (the
lines) will have one of the flip-flops 9 located thereat to allow
for product calculation as illustrated in FIG. 2.
[0036] It is understood that the above-described arrangements are
only illustrative of the application of the principles of the
present invention. Numerous modifications and alternative
arrangements may be devised by those skilled in the art without
departing from the spirit and scope of the present invention and
the appended claims are intended to cover such modifications and
arrangements. Thus, while the present invention has been shown in
the drawings and fully described above with particularity and
detail in connection with what is presently deemed to be the most
practical and preferred embodiment(s) of the invention, it will be
apparent to those of ordinary skill in the art that numerous
modifications, including, but not limited to, variations in size,
materials, shape, form, function and manner of operation, assembly
and use may be made, without departing from the principles and
concepts of the invention as set forth in the claims.
* * * * *