U.S. patent application number 12/407386 was filed with the patent office on 2009-09-24 for electrolytic plating solution, electrolytic plating method, and method for manufacturing semiconductor device.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Tsuyoshi KANKI.
Application Number | 20090236232 12/407386 |
Document ID | / |
Family ID | 41087813 |
Filed Date | 2009-09-24 |
United States Patent
Application |
20090236232 |
Kind Code |
A1 |
KANKI; Tsuyoshi |
September 24, 2009 |
ELECTROLYTIC PLATING SOLUTION, ELECTROLYTIC PLATING METHOD, AND
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Abstract
An electrolytic plating solution includes a polar solvent,
copper sulfate dissolved in the polar solvent, an accelerator
including a sulfur compound, and a reducing agent having a smaller
molecular weight than the accelerator.
Inventors: |
KANKI; Tsuyoshi; (Kawasaki,
JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW, SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki-shi
JP
|
Family ID: |
41087813 |
Appl. No.: |
12/407386 |
Filed: |
March 19, 2009 |
Current U.S.
Class: |
205/157 ;
205/291; 257/E21.575 |
Current CPC
Class: |
C25D 3/38 20130101; C25D
7/123 20130101; H01L 21/76877 20130101; H01L 21/2885 20130101 |
Class at
Publication: |
205/157 ;
205/291; 257/E21.575 |
International
Class: |
C25D 7/12 20060101
C25D007/12; C25D 3/38 20060101 C25D003/38 |
Foreign Application Data
Date |
Code |
Application Number |
Mar 24, 2008 |
JP |
2008-076681 |
Claims
1. An electrolytic plating solution, comprising: a polar solvent,
copper sulfate dissolved in the polar solvent, an accelerator
including a sulfur compound, and a reducing agent having a smaller
molecular weight than the accelerator.
2. The electrolytic plating solution according to claim 1, wherein
the reducing agent is a compound having a water-soluble aldehyde
group or ketone group.
3. The electrolytic plating solution according to claim 1, wherein
the reducing agent has a molecular weight of 300 or less.
4. The electrolytic plating solution according to claim 1, wherein
the reducing agent is a monosaccharide.
5. The electrolytic plating solution according to claim 1, wherein
the reducing agent comprises glucose.
6. The electrolytic plating solution according to claim 1, wherein
the accelerator comprises disulfide propanesulfonic acid.
7. The electrolytic plating solution according to claim 1, further
comprising polyethylene glycol as a suppressor.
8. An electrolytic plating method, comprising: immersing a treated
substrate, on which a copper seed layer is formed, in an
electrolytic plating solution, and depositing a copper layer on the
treated substrate immersed in the electrolytic plating solution by
electrolytic plating, wherein the electrolytic plating solution
comprises: a polar solvent, copper sulfate dissolved in the polar
solvent, an accelerator including a sulfur compound, and a reducing
agent having a smaller molecular weight than the accelerator.
9. The electrolytic plating method according to claim 8, wherein
energization is started after the treated substrate is immersed in
the electrolytic plating solution.
10. A method for manufacturing a semiconductor device, comprising:
forming a recess in an insulating film on a treated substrate,
forming a barrier metal film, in a shape conforming to a shape of
the recess, on the insulating film so as to continuously cover a
side wall surface and bottom surface of the recess, forming a
copper seed layer, in a shape conforming to the shape of the
recess, on the insulating film, covering the barrier metal film,
filling the recess with a copper layer by electrolytic plating
using the copper seed layer as an electrode, and removing the
copper layer on the insulating film by a chemical mechanical
polishing method until a surface of the insulating film is exposed,
wherein an electrolytic plating solution used for forming the
copper layer comprises: a polar solvent, copper sulfate dissolved
in the polar solvent, an accelerator including a sulfur compound,
and a reducing agent having a smaller molecular weight than the
accelerator.
11. The method for manufacturing a semiconductor device according
to claim 10, wherein the electrolytic plating method comprises:
immersing the treated substrate in the electrolytic plating
solution, and performing energization in the electrolytic plating
solution, using the copper seed layer as an electrode, wherein the
energization is started after the treated substrate is immersed in
the electrolytic plating solution.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is based upon and claims the benefit of
priority from the prior Japanese Patent Application No. 2008-76681
filed on Mar. 24, 2008, the entire contents of which, are
incorporated herein by reference.
BACKGROUND
[0002] 1. Field
[0003] The present invention generally relates to a semiconductor
device and particularly to an electrolytic plating method, and a
method for manufacturing a semiconductor device using the
electrolytic plating method.
[0004] 2. Description of Related Art
[0005] In today's ultrafine semiconductor integrated circuit
devices, a multilayer wiring structure using a low resistance metal
for its wiring pattern is used to interconnect a vast number of
semiconductor elements formed on the substrate. Particularly, in a
multilayer wiring structure using copper (Cu) for its wiring
pattern, wiring grooves or via holes are previously formed in an
interlayer insulating film made up of a silicon oxide film, or a
material having a lower relative dielectric constant, the so-called
low dielectric constant (low-k) material. A damascene method or a
dual damascene method is generally used in which a Cu layer having
low resistivity and high resistance to electromigration is formed
to fill these via holes, and the surplus portions of the Cu layer
are removed by chemical mechanical polishing (CMP).
[0006] In the damascene method or the dual damascene method, the
surfaces of the wiring grooves or the via holes formed in the
interlayer insulating film are covered with a barrier metal film
made up of a high melting point metal or nitride thereof, typically
Ta, TaN, or the like. By forming a thin Cu seed layer on the
barrier metal film by a PVD method or a CVD method and performing
electrolytic plating using such a Cu seed layer as an electrode, a
Cu layer is formed to fill the wiring grooves or the via holes.
[0007] In the electrolytic plating step fox the Cu layer,
generally, an electrolytic plating solution, such as an aqueous
copper sulfate solution in which copper salt, such as copper
sulfate, is dissolved in a polar solvent, such as water, is used.
Generally, several types of additives are added in combination to
the electrolytic plating solution to fill fine wiring grooves and
via holes. For these additives, an accelerator (also referred to as
a brightener) made up of a sulfur compound, and a suppressor (also
referred to as an inhibitor) made up of a polymer having a
molecular weight of about 1000 to 6000, such as polyethylene glycol
and polypropylene glycol, are added to positively fill (bottom-up
fill) the wiring grooves and the via holes from the bottom portions
toward the upper portions. Further, a leveler made up of polymers
having a molecular weight of more than 10000, many of which have a
cyclic structure, may also be added. If either of the accelerator
and the suppressor is absent, the desired bottom-up filling is not
obtained.
[0008] FIGS. 1A to 1E depict the steps of forming a Cu wiring
pattern by a typical damascene method, and FIG. 2 depicts an
example of ideal bottom-up filling in forming such a Cu wiring
pattern.
[0009] In FIG. 1A, recesses 12 constituting wiring grooves or via
holes are formed in an insulating film 11. Next, depicted as FIG.
1B, a barrier metal film 13 typically made up of a high melting
point metal, such as Ta and Ti, or conductive nitride thereof, such
as TaN and TiN, is formed, in a shape conforming to the recesses
12, on the side wall surfaces and bottom, surfaces of the recesses
12.
[0010] Further, depicted as FIG. 1C, a Cu seed layer 14 is formed,
in a shape conforming to the recesses 12, on the surface of the
barrier metal film 13 by a PVD method or a CVD method. Further,
depicted as FIG. 1D, a Cu layer 15 is formed to fill the recesses
12 by electrolytic plating using the Cu seed layer 14 as an
electrode.
[0011] At the time, the previously described accelerator and
suppressor are added to an electrolytic plating solution used.
Thus, depicted as FIG. 2, filling with the Cu layer 15 occurs
upwardly from the bottom portions of the recesses 12 (bottom-up
filling).
[0012] Further, depicted as FIG. 1E, the unnecessary Cu layer 15 on
the surface of the interlayer insulating film 11 is removed by a
CMP method. Thus, a Cu wiring pattern 15A that has few voids and
high resistance to stress migration and electromigration is
obtained.
[0013] However, in recent semiconductor devices having an ultrafine
multilayer wiring structure having a minimum via or groove diameter
of 90 nm or less, a strongly acidic solution having a pH of 1 or
less is generally used as an electrolytic plating solution. In this
case, it is known that the problem that the thin Cu seed layer 14
is dissolved by the action of the plating solution occurs.
[0014] FIGS. 4A to 4C depict the state of the seed layer 14
depicted, in FIGS. 3A and 38, in the early stage of the
electrolytic plating step depicted in FIG. 1D. However, FIGS, 4A to
4C are views in which the seed layer 14 covering the side wall
surface of the recess 12 in the structure in FIG. 3A is seen in the
direction depicted by the arrow in FIG. 3B. In FIGS. 4A to 4C, a
thin Cu layer is formed on the seed layer 14 by a 10-second
electrolytic plating step.
[0015] Referring to FIGS. 4A to 4C, in FIGS. 4A and 4B, the seed
layer 14 is dissolved in the lower portion of the recess 12. Also,
it is seen that in the view of FIG. 4(C), the seed layer 14 in the
center portion is dissolved. In FIGS. 4A to 4C, a light portion
seen in the lower portion of the recess 12 depicts a cross section
of the seed layer 14 covering the bottom portion of the recess 12.
It is seen that as a result of cleavage during sample making, the
seed layer 14 is plastically deformed.
[0016] If the seed layer 14 is partly dissolved, in the structure
in FIG. 1C, in this manner, the formation of the Cu layer 15 does
not occur in portions lacking the seed layer 14 when electrolytic
plating is performed in the step in FIG. 1D, using such a seed
layer 14 as an electrode. Therefore, depicted as FIG. 5, defects,
such as voids, occur in the Cu wiring pattern 15A filling the
recesses 12.
[0017] Conventionally, in order to suppress the dissolution of the
plating seed layer 14 in the electrolytic plating step, when the
treated substrate is immersed in the electrolytic plating solution,
voltage is previously applied to the treated substrate. On the
other hand, when the treated substrate is immersed in the
electrolytic plating solution, the treated substrate is immersed,
obliquely tilted with respect to the liquid surface of the
electrolytic plating solution to suppress the occurrence of
bubbles. Then, when the treated substrate to which bias voltage is
applied is immersed, obliquely tilted with respect to the liquid
surface, in this manner, the deposition of a Cu layer immediately
starts from the immersed portion. As a result, it is difficult to
optimally control the formation of the Cu layer 15 depicted FIG.
1B. This problem is remarkable particularly in the manufacture of
an ultrafine semiconductor device having a via diameter of 70 nm or
less.
[0018] Also, conventionally, in order to suppress the dissolution
of such a plating seed layer 14 in the electrolytic plating step,
JP-A-2002-146585 proposes using a weakly acidic plating solution
having a large pH value, or an alkaline plating solution. However,
in such a technique, it is necessary to use a special plating
solution. Also, optimal film formation conditions are limited.
Therefore, it is difficult to generally use such a technique for
the manufacture of an ultrafine semiconductor device.
[0019] Also, in order to suppress the dissolution of the above Cu
seed layer in the electrolytic plating step, a technique of adding
a high concentration of a suppressor to the electrolytic plating
solution is proposed.
[0020] FIG. 6A is a view depicting the state of the Cu seed layer
14 when the formation of the Cu layer 15 is performed on the
structure in FIG. 1C for about 10 seconds, using an electrolytic
plating solution (a virgin makeup solution: VMS) made up of an
aqueous copper sulfate solution containing neither an accelerator
nor a suppressor.
[0021] FIG. 8B is a view depicting the state of the Cu seed layer
14 when similar electrolytic plating is performed on the structure
in FIG. 1C for short time by adding to the VMS only disulfide
propanesulfonic acid (SPS) generally used as an accelerator.
[0022] FIG. 6C is a view depicting the state of the Cu seed layer
14 when similar electrolytic plating is performed on the structure
in FIG. 1C for short time by adding to the VMS only polyethylene
glycol (PEG) generally used as a suppressor.
[0023] FIGS, 6A to 6C are views of the state of the side wail
surface of the recess 12 seen, as in the FIGS. 4A to 4C.
[0024] Referring to FIGS. 6A to 6C, it is seen that in the case in
FIG. 6A in which the VMS is used, the dissolution of the Cu seed
layer 14 in the lower portion of the recess 12 is noted, and that
in the case in FIG. 6B in which the accelerator is added to the
VMS, the dissolution of the Cu seed layer 14 is further promoted.
On the other hand, it is seen that in the case depicted in FIG. 6C
in which only the suppressor is added, the dissolution of the Cu
seed layer 14 decreases. However, the problem of dissolution is not
completely solved even in the case in FIG. 6C. Then, it is
considered that a high concentration of the suppressor is added
into the electrolytic plating to solve only the problem of the
dissolution of the Cu seed layer 14. However, when only the
suppressor is added, the bottom-up filling of the recesses 12 with
the Cu layer as previously described in FIG. 2 is impossible. Also,
if the width of the recesses 12 is 70 nm or less, the dissolution
of the Cu seed layer 14 in the bottom potions of the recesses 12
cannot be avoided even if the suppressor is added to the
electrolytic plating solution, depicted as FIGS. 7A and 7B.
However, FIGS. 7A and 78 depict, at different magnification, the
state of the Cu seed layer 14 when the electrolytic plating of the
Cu layer 15 is performed for short time in the step in FIG. 1D,
SUMMARY
[0025] According to an aspect of an embodiment, an electrolytic
plating solution includes a polar solvent, copper sulfate dissolved
in the polar solvent, an accelerator including a sulfur compound,
and a reducing agent having a smaller molecular weight than the
accelerator.
[0026] The object and advantages of the invention will be realised
and attained by means of the elements and combinations particularly
pointed out in the claims.
[0027] It is to be understood that both the foregoing general
description and the following detailed description are exemplary
and explanatory and are not restrictive of the invention, as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIGS. 1A to 1E are views explaining the steps of forming a
Cu wiring pattern by a damascene method;
[0029] FIG. 2 is a view showing an example of ideal bottom-up
filling;
[0030] FIGS. 3A and 3B are views explaining the problem;
[0031] FIGS. 4A to 4C are views explaining the problem;
[0032] FIG. 5 is a view explaining the problem;
[0033] FIGS. 6A to 6C are views explaining the problem;
[0034] FIGS. 7A and 7B are views explaining the problem;
[0035] FIG. 8 is a view showing the configuration of an
electrolytic plating apparatus used in an embodiment;
[0036] FIGS. 9A to 9D are views explaining experiment performed in
a first embodiment;
[0037] FIGS. 10A and 10B are views showing the result of the
experiment;
[0038] FIGS. 11A and 11B are views showing the interpretation of
the experiment;
[0039] FIG. 12 is a view showing the interpretation of the
experiment;
[0040] FIG. 13 is a view further explaining the experiment;
[0041] FIG. 14 is a view further explaining the experiment;
[0042] FIGS. 15A to 15E are views explaining the steps of forming a
Cu wiring pattern by a damascene method according to a second
embodiment;
[0043] FIGS. 16A to 16L are views explaining the steps of forming a
Cu wiring pattern by a dual damascene method according to a third
embodiment; and
[0044] FIG. 17 is a view showing the configuration of a
semiconductor device according to a fourth, embodiment.
DESCRIPTION OF EMBODIMENTS
First Embodiment
[0045] The effect of the accelerator and the suppressor on the
problem of the dissolution of the Cu seed layer 14 previously
described has been examined. As a result, it has been found that
when a compound having a smaller molecular weight than a compound
used as the accelerator, for example, glucose is further added as a
reducing agent to the electrolytic plating solution, the
dissolution of the Cu seed layer 14 is very effectively
suppressed.
[0046] FIG. 8 shows the schematic configuration of an electrolytic
plating apparatus 1 used in experiment, and FIGS. 9A to 9D show the
outline of the experiment performed by the inventor.
[0047] First, FIG. 8 is referred to.
[0048] The electrolytic plating apparatus 1 has a container 2 in
which an anode 2B is held in an electrolyte 2A, and a treated
substrate W is immersed in the electrolyte 2A.
[0049] A tank 3 is connected to the container 2 via pipes 3A and
38, and the electrolyte 2A is circulated between the container 2
and the tank 3 through the pipes 3A and 38.
[0050] Further, a VMS supplying unit 4A, an accelerator supplying
unit 4B, a suppressor supplying unit 4C, a leveler supplying unit
4D, and a reducing agent supplying unit 4E are connected to the
tank 3 via respective lines. Also, a concentration measurement
apparatus 5 that measures the concentration of the electrolyte 2A
in the tank 3 is coupled to the tank 3. Further, in electrolytic
plating treatment, a direct current power source DC is connected to
the treated substrate W and the anode 28.
[0051] Referring to FIG. 9A, recesses 22 constituting wiring
grooves or via holes are formed, with a width and depth of 70 nm,
in an insulating film 21. Further, a barrier metal film 23 made up
of a Ta film is formed, in a shape conforming to the recesses 22
and with a film thickness of 5 to 6 nm, on the side wall surfaces
and bottom surfaces of the recesses 22, as shown in FIG. 9B.
Further, as shown in FIG. 9C, a Cu seed layer 24 is formed, in a
shape conforming to the recesses 22 and with a film thickness of 40
to 100 nm, on the surface of the barrier metal film 23 by a PVD
method.
[0052] Further, in a step in FIG. 90, electrolytic plating using
the Cu seed layer 24 as an electrode is performed for short time,
typically 10 seconds, using the electrolytic plating apparatus 1.
Thus, a Cu layer 25 is formed, with a film thickness of about 10
nm, on the surface of the Cu seed layer 24. By forming the thin Cu
layer 25 on the surface of the Cu seed layer 24 in this manner,
defects in the Cu seed layer 24 can be more clearly detected.
[0053] In Example 1, as the electrolyte 2A, an aqueous copper
sulfate solution containing Cu ions at a concentration of 60 g/L,
also sulfuric acid (H.sub.2SO.sub.4) at a concentration of 10 g/L,
and further chlorine (Cl) at a concentration of 50 ppm was made as
a VMS. At the time, in Example 1, further, disulfide
propanesulfonic acid (SPS) having the chemical formula
HO.sub.3S--CH.sub.2CH.sub.2CH.sub.2--S--S--CH.sub.2CH.sub.2CH.sub.2--SO.s-
ub.3H and a molecular weight M of 310 was added to the VMS as an
accelerator at a concentration of 20 mg/L, and also polyethylene
glycol (PEG) having a molecular weight of 400, 2000, and 6000 was
added as a suppressor to make three types of electrolytic plating
solutions in which the polymerization degree of the suppressor was
different. On the other hand, in the example of Example 1, a
leveler was not used because the embedding of the Cu layer in the
recesses 22 was not much affected.
[0054] Further, in Example 1, D (+) glucose having a molecular
weight of 180 was added to the electrolyte 2A as the reducing agent
at a rate of 10 to 20 ppm.
[0055] FIGS. 10A and 108 show views of samples, in which the Cu
layer 25 was formed, with a film thickness of about 10 nm, on the
structure in FIG. 9C in the electrolytic plating apparatus 1 in
FIG. 8, observed in the direction of the arrow as shown in FIG. 9D.
Here, the sample in FIG. 10A shows a control standard in which
glucose was not added, while the sample in FIG. 10B shows the
sample of Example 1 in which glucose was added. However, in either
of the samples in FIGS. 10A and 10B, polyethylene glycol having a
molecular weight of 2000 was added as a suppressor at a rate of 300
g/L.
[0056] Also, in the experiment in FIGS. 10A and 10B, in the
apparatus 1 in FIG. 8, bias voltage was not applied when the
treated substrate W was immersed in the electrolytic plating
solution 2A, and after the treated substrate w was immersed,
energization was performed at a current density of 5 to 10
mA/cm.sup.2. The temperature of the plating solution was set at
25.degree. C. (ordinary temperature; room temperature).
[0057] When FIGS. 10A and 10B are compared, it is seen that the
dissolution of the Cu seed layer 24 occurred in a manner similar to
that previously described in FIGS. 4A to 4C, when glucose was not
added, while the dissolution of such a Cu seed layer 24 completely
stopped by adding glucose.
[0058] The result in FIGS. 10A and 10B suggests the following
mechanism for the dissolution of the Cu seed layer.
[0059] As schematically shown in FIG. 11A, when a reducing agent,
such as glucose, is not included in the electrolytic plating
solution 2A, the Cu seed layer 24 is oxidized by dissolved oxygen
in the electrolytic plating solution 2A, and formed copper oxide,
such as CuO or Cu.sub.2O, is dissolved by the electrolytic plating
solution 2A. At the time, when an accelerator is included in the
electrolytic plating solution 2A, the oxidation of the Cu seed
layer 24 is promoted, and as a result, the dissolution of the Cu
seed layer 24 is promoted.
[0060] However, when a reducing agent, such as glucose, is present
in the electrolytic plating solution 2A, copper oxide formed by
dissolved oxygen in the electrolytic plating solution is
immediately reduced to Cu, as schematically shown in FIG. 11B.
Therefore, even if an accelerator is included in the electrolytic
plating solution 2A, the dissolution of the Cu seed layer 24 is
suppressed.
[0061] In view of such a mechanism, it is considered that the
reducing agent is not limited to glucose and may be saccharides,
aldehyde groups, or ketone groups that include an aldehyde group or
a ketone group and exhibit the action of reduction.
[0062] Then, from the consideration in FIGS. 11A and 11B, it is
considered that the dissolution of the Cu seed layer 24 by the
electrolytic plating solution is suppressed by adding the reducing
agent, in addition to the accelerator, into the electrolytic
plating solution 2A.
[0063] However, when the case where a fine recess, for example, the
recess 22 having a minimum line width W of 70 nm or less shown in
FIG. 12 is filled by the electrolytic plating of a Cu layer is
considered, it is desirable that in the above-described mechanism,
the reducing agent is transported to the bottom portion 22A of the
recess 22, which is surrounded by the broken line, with efficiency
equal to or higher than that of the accelerator. For this, it is
desirable that the reducing agent is a compound having a molecular
weight equal to or less than that of the accelerator. In the
example in FIG. 12, a lower-layer insulating film 31 is formed
under the insulating film 21 via a barrier metal film 32. The
accelerator SPS used in this example has a molecular weight of
about 310. Therefore, it is desirable that the reducing agent has a
molecular weight of, for example, 300 or less. Glucose has a
molecular weight of about 180 and satisfies the above
conditions.
[0064] Such a reducing agent having an aldehyde group or a ketone
group and having a molecular weight of 300 or less includes, in
addition to glucose having a molecular weight of 180,
monosaccharides, such as glyceraldehyde having a molecular weight
of 90, erythrose having a molecular weight of 120, threose having a
molecular weight of 120, ribose having a molecular weight of 150,
arabinose having a molecular weight of 150, xylose having a
molecular weight of 150, lyxose having a molecular weight of 150,
allose having a molecular weight of 180, altrose having a molecular
weight of 180, mannose having a molecular weight of 180, gulose
having a molecular weight of 180, idose having a molecular weight
of 180, galactose having a molecular weight of 180, and talose
having a molecular weight of 180.
[0065] Further, the reducing agent includes aldehyde groups, such
as formaldehyde having a molecular weight of 30, acetaldehyde
having a molecular weight of 44, propionaldehyde having a molecular
weight of 58, vinyl aldehyde having a molecular weight of 55,
benzaldehyde having a molecular weight of 106, cinnamaldehyde
having a molecular weight of 132, and perillaldehyde having a
molecular weight of 150, and further ketone groups, such as acetone
having a molecular weight of 59, methyl ethyl ketone having a
molecular weight of 72, and diethyl ketone having a molecular
weight of 86.
[0066] Particularly when mercaptopropanesulfonic acid (MPS) having
a molecular weight of 155 is used as the accelerator, instead of
SPS, effect similar to that previously described can be obtained by
using the above reducing agents having a molecular weight of 155 or
less.
[0067] Next, in order to confirm the action and effect of the above
reducing agents, polyethylene glycol that does not have reduction
properties was added, instead of the glucose, to the electrolytic
plating solution 27A at various molecular weights (400, 2000, and
6000) and concentrations (300 mg/L and 3000 mg/L), and whether the
effect of suppressing the dissolution of the Cu seed layer 24
occurred or not was examined by experiment under the same
conditions as the previous experiment in FIGS. 10A and 10B. The
result is shown in FIG. 13.
[0068] Referring to FIG. 13, it is seen that remarkable dissolution
occurred in the Cu seed layer 2 4 in any of the cases.
[0069] According to FIG. 13, it is concluded that even if simply an
additive having a smaller molecular weight than the accelerator is
added to the electrolytic plating solution 2A, the effect of
suppressing the dissolution of the Cu seed layer 24 that is
previously obtained in FIGS. 10A and 10B is not obtained if the
additive does not exhibit reduction action.
[0070] Further, in order to confirm the action and effect of the
above reducing agents, the electrolytic plating solution 2A, in
which polyethylene glycol having a molecular weight of 2000 or 6000
was used as a suppressor, and to which polyethylene glycol having a
molecular weight of 200 was further added, instead of the reducing
agent, was used, and whether the effect of suppressing the
dissolution of the Cu seed layer 24 occurred or not was examined by
experiment under the same conditions as the previous experiment in
FIGS. 10A and 10B. The result is shown in FIG. 14.
[0071] FIG. 14A shows a control standard in which the polyethylene
glycol having a molecular weight of 200 was not added, and FIG. 14B
shows an example in which the polyethylene glycol having a
molecular weight of 200 was added.
[0072] Referring to FIGS. 14A and 14B, it is shown that even if
polyethylene glycol having a molecular weight of 200 was added,
holes were formed in the Cu seed layer 24, and dissolution by the
electrolytic plating solution could not be sufficiently
suppressed,
[0073] From the above, the findings are shown that the problem, of
the dissolution of the Cu seed layer by the electrolytic plating
solution to which the accelerator is added can be solved by further
adding a reducing agent to the electrolytic plating solution and,
at the time, selecting and using as the reducing agent a reducing
agent having a molecular weight equal to or less than the molecular
weight of the accelerator.
[0074] When the reducing agent is added to the electrolytic plating
solution in this manner to perform, for example, the electrolytic
plating step in FIG. 9D, using the electrolytic plating apparatus 1
in FIG. 8, it is not necessary to perform voltage application to
the treated substrate W before immersion into the electrolytic
plating solution 2A, which is conventionally performed to suppress
the dissolution of the Cu seed layer 24. In other words, it is
possible to start the energization of the treated substrate W after
the treated substrate w is immersed in the electrolytic plating
solution 2A. As a result, it is possible to perform the filling of
the recesses 22 with the Cu layer 25 under optimal current
conditions. As a result, it is possible to form fine via holes or
wiring grooves having a minimum line width of 70 nm or less without
defects by the bottom-up process as shown in FIG. 2.
[0075] In the electrolytic plating solution 2A in this example, the
solvent that dissolves copper sulfate is not limited to water, and
other polar solvents, for example, alcohols, such as methanol and
ethanol, cyclic carbonates, such as ethylene carbonate and
propylene carbonate, and linear carbonates, such as dimethyl
carbonate, ethyl methyl carbonate, and diethyl carbonate, or mixed
solvents thereof can also be used.
Second Embodiment
[0076] FIGS. 15A to 15E show a method for forming a Cu wiring
pattern according to a second embodiment.
[0077] FIG. 15A is referred to.
[0078] Recesses 42 constituting wiring grooves or via holes are
formed, with a width and depth of 70 nm, in an insulating film 41.
A barrier metal film 43 made up of a Ta film is formed, in a shape
conforming to the recesses 42 and with a film thickness of, for
example, 5 to 6 nm, on the side wall surfaces and bottom surfaces
of the recesses 42, as shown in FIG. 15B. Further, as shown in FIG.
15C, a Cu seed layer 44 is formed, in a shape conforming to the
recesses 42 and with a film thickness of 40 to 100 nm, on the
surface of the barrier metal film 43 by a PVD method,
[0079] Further, in a step in FIG. 15D, electrolytic plating using
the Cu seed layer 44 as an electrode is performed in the
electrolytic plating apparatus 1 to bottom-up fill the recesses 42
from the surface of the Cu seed layer 44 with a Cu layer 45. At the
time, as the electrolytic plating solution 2A, one in which SPS as
an accelerator, polyethylene glycol as a suppressor, and further
glucose as a reducing agent are added to an aqueous copper sulfate
solution, as described in the previous embodiment, is used.
[0080] Further, in a step in FIG. 15E, by removing the unnecessary
Cu layer 45 on the surface of the interlayer insulating film 41 by
a CMP method, a Cu wiring pattern 45A that has few voids and
therefore has high resistance to stress migration and
electromigration is obtained.
[0081] In this embodiment, glucose is added as a reducing agent to
the electrolytic plating solution 2A. Therefore, even if an
accelerator, such as SPS, is added to the electrolytic plating
solution 2A, the dissolution of the Cu seed layer 44 is suppressed.
As a result, in the electrolytic plating step in FIG. 15D, the
recesses 42 can be bottom-up filled with the Cu layer 45, and the
occurrence of defects, such as voids, in the Cu wiring pattern 45A
can be effectively suppressed.
[0082] Also, as previously described, when, the electrolytic
plating step in FIG. 15D is performed using the electrolytic
plating apparatus 1 in FIG. 8, it is not necessary to perform
voltage application to the treated substrate W before immersion
into the electrolytic plating solution 2A, which is conventionally
performed to suppress the dissolution of the Cu seed layer 44. In
other words, it is possible to start the energization of the
treated substrate W after the treated substrate W is immersed in
the electrolytic plating solution 2A. As a result, it is possible
to perform the filling of the recesses 42 with the Cu layer 45
under optimal current conditions. Therefore, it is possible to form
fine via holes or wiring grooves having a minimum line width of 70
nm or less without defects by the bottom-up process as shown in
FIG. 2.
[0083] In this embodiment, for example, a leveler commercially
available from ATMI under the trade name Viaform Leveler may be
added, as required, to the electrolytic plating solution 2A.
Third Embodiment
[0084] Next, the steps of manufacturing a semiconductor device
having a multilayer wiring structure according to a third
embodiment will be described referring to FIG. 16A to FIG. 16L.
[0085] Referring to FIG. 16A, an interlayer insulating film 303
made up of SiO.sub.2 or the like is formed on an insulating film
301 on a silicon substrate (not shown) via a SIN film 302. A resist
pattern R1 corresponding to the desired wiring pattern is formed on
the interlayer insulating film 303.
[0086] Next, in a step in FIG. 16B, the interlayer insulating film
303 is patterned using the resist pattern R1 as a mask. As a
result, wiring grooves corresponding to the desired wiring
patterning are formed in the interlayer insulating film 303.
Further, the interlayer insulating film 303 patterned in this
manner is covered with a Ta barrier metal film 304, and then, the
steps in FIGS. 15A to 15D are executed. Thus, a copper layer CL1 is
formed by the electrolytic plating method so as to fill the wiring
grooves. In this electrolytic plating method, an electrolytic
plating solution in which SPS as an accelerator, polyethylene
glycol as a suppressor, and glucose as a reducing agent are added
to an aqueous copper sulfate solution is used.
[0087] Further, in a step in FIG. 16C, the copper layer CL1 and the
barrier metal film 304 under the copper layer CL1 are polished and
removed by a CMP method until the surface of the interlayer
insulating film 303 is exposed. Further, a next interlayer
insulating film 306 made up of SiO.sub.2 or the like is formed on
the structure formed in this manner, via a SiN barrier film
CL1.
[0088] In the step in FIG. 16C, further, a next interlayer
insulating film 308 made up of SiO.sub.2 or the like is formed on
the interlayer insulating film 306 via a SiN barrier film 307.
Further, a resist pattern R2 corresponding to the desired contact
hole is formed on the interlayer insulating film 308.
[0089] Next, in a step in FIG. 16D, the interlayer insulating film
303, the barrier film 307, and the interlayer insulating film 306
are sequentially patterned using the resist pattern R2 as a mask to
form a contact hole 308C in such a manner that the SiN barrier film
305 is exposed in the bottom portion. Then, a non-photosensitive
resin film is applied to fill the contact hole 308C with the resin
film. Further, the resin film on the interlayer insulating film 308
is dissolved and removed to leave a resin protective portion 308R
in the contact hole 308C.
[0090] Further, in the step in FIG. 16D, a resist pattern R3
corresponding to wiring grooves desired to be formed in the
interlayer insulating film 308 is formed on the interlayer
insulating film 308.
[0091] Next, in a step in FIG. 16E, with the inner wall surface of
the contact hole 308C protected by the resin protective portion
308R, the interlayer insulating film 308 is patterned using the
resist pattern R3 as a mask until the SiN barrier film 307 is
exposed. Thus, the desired wiring grooves 308G are formed in the
interlayer insulating film 308.
[0092] Further, in the step in FIG. 16E, after the interlayer
insulating film 308 is patterned, the resin protective portion 308R
is removed by an ashing process.
[0093] Further, in a step in FIG. 16F, using the interlayer
insulating film 308 as a self-alignment mask, the SiN barrier films
307 and 305 are respectively removed from, the bottom, portions of
the wiring grooves 308G and the contact hole 308C. Further, the
surface of the structure obtained in this manner is covered with a
Ta barrier metal film 309, and then, the previous steps in FIGS.
15A to 15D are executed for a copper layer CL2 so that the copper
layer CL2 fills the contact hole 308C and the wiring grooves 308G.
Thus, the copper layer CL2 is formed by the electrolytic plating
method using an electrolytic plating solution in which SPS as an
accelerator, polyethylene glycol as a suppressor, and glucose as a
reducing agent are added to an aqueous copper sulfate solution.
[0094] Next, in a step in FIG. 16G, the copper layer CL2 and the Ta
barrier metal film 309 under the copper layer CL2 in FIG. 10F are
removed by the CMP method until the surface of the interlayer
insulating film 308 is exposed. Further, a SiN barrier film 311,
and an interlayer insulating film 312 made up of SiO.sub.2 or the
like, are formed on the structure obtained in this manner.
[0095] Further, in the step in FIG. 16G, a resist pattern R4
corresponding to via holes desired to be formed in the interlayer
insulating film 312 is formed on the interlayer insulating film
312.
[0096] Further, in a step in FIG. 16H, the interlayer insulating
film 312 and the SiN barrier film 311 under the interlayer
insulating film 312 are patterned using the resist pattern R4 as a
mask. As a result, the desired via holes 312V are formed in the
interlayer insulating film 312.
[0097] Further, in a step in FIG. 16I, for the structure in FIG.
16H, a barrier metal layer 313 made up of a TaN film is formed on
the interlayer insulating film 312 by reactive sputtering so as to
continuously cover the side wall surfaces and bottom surfaces of
the via holes 312V. Further, a TiN barrier metal film 314 is formed
on the TaN barrier metal film 313 also by reactive sputtering.
Further, in a step in FIG. 16J, a tungsten film 315 is formed on
the structure in FIG. 16I by the CVD method so that the tungsten
film 315 fills the via holes 312V.
[0098] Further, in a step in FIG. 16K, the tungsten film 315, and
the TiN film 314 and the TaN 313 under the tungsten film 315 are
polished and removed by the CMP method, until the surface of the
interlayer insulating film 312 is exposed, to form tungsten via
plugs 315W in the via holes 312V.
[0099] Further, in the step in FIG. 16K, a conductor film 316b made
up of aluminum or an aluminum-copper alloy is formed on the
interlayer insulating film 312 via a TiN barrier metal film 316a.
Further, another TiN barrier metal film 316c is formed on the
conductor film 316b. The conductor film 316b, together with the TiN
barrier metal films 316a and 316c, forms a wiring layer 316.
[0100] In the state in FIG. 16K, a resist pattern R5 corresponding
to a wiring pattern desired to be further formed is formed on the
wiring layer 316. Further, in a step in FIG. 16L, the wiring layer
316 is patterned by dry etching or the like, using the resist
pattern R5 as a mask, so that wiring patterns 316A and 316B are
formed on the tungsten plugs 315W.
[0101] Further, in the step in FIG. 16L, an interlayer insulating
film 317 of SiO.sub.2 or the like is deposited on the interlayer
insulating film 312 so as to cover the wiring patterns 316A and
316B, and a passivation film 318 of SiN or the like is formed on
the surface of the interlayer insulating film 317.
[0102] In this embodiment, the electrolytic, plating step for the
Cu layer CL1 or CL2 in FIG. 16B or FIG. 16F is executed using an
electrolytic plating solution made up of an aqueous copper sulfate
solution to which SPS as an accelerator, polyethylene glycol as a
suppressor, and further glucose as a reducing agent are added, as
previously described in FIGS. 15A to 15D. Thus, the wiring grooves
can be bottom-up filled with the Cu layer CL1 or CL2 without
dissolving the Cu seed layer not shown. As a result, the occurrence
of defects, such as voids, can be effectively suppressed.
[0103] Also in this embodiment, when the electrolytic plating step
in FIG. 16B or FIG. 16F is performed using the electrolytic plating
apparatus 1 in FIG. 8, it is not necessary to perform voltage
application to the treated substrate W before immersion into the
electrolytic plating solution 2A, which is conventionally performed
to suppress the dissolution of the Cu seed layer. Therefore, it is
possible to start the energization of the treated substrate W after
the treated substrate W is immersed in the electrolytic plating
solution 2A. As a result, it is possible to perform the filling of
the recesses with the Cu layer CL1 or CL2 under optimal current
conditions. Thus, it is possible to form fine via holes or wiring
grooves having a minimum line width of 70 nm or less without
defects by the bottom-up process as shown in FIG. 2.
Fourth Embodiment
[0104] FIG. 17 is a view showing the configuration of a
semiconductor device having a multilayer wiring structure formed in
this manner, according to a fourth embodiment.
[0105] Referring to FIG. 17, an element region 401A is defined on a
silicon substrate 401 by a STI structure 402. In the element region
401A, a gate electrode 403 is formed on the silicon substrate 401
via a gate insulating film 403A.
[0106] A side wall insulating film is formed on both side wall
surfaces of the gate electrode 403. Further, in the silicon
substrate 401, LDD regions 401a and 401b are formed on both sides
of the gate electrode 403. Also, in the silicon substrate 401,
diffusion regions 401c and 401d forming a source region or a drain
region are formed outside the side wail insulating films. Also, the
surface of the silicon substrate 401 is uniformly covered with a
SiN film 404, except the gate electrode 403 and portions where its
side wall insulating films are formed.
[0107] Further, an interlayer insulating film 405 made up of
SiO.sub.2 or the like is formed on the SiN film 404 so as to cover
the gate electrode 403 and the side wail insulating films. Contact
holes 405A and 405B exposing the diffusion regions 401c and 401d
are formed in the interlayer insulating film 405.
[0108] The side wall surfaces and bottom surfaces of the contact
holes 405A and 4053 are covered with a barrier metal film 406 in
which a TaN film and a TiN film are laminated. Further, the contact
holes 405A and 405B are filled with tungsten plugs 407 via the
barrier metal film.
[0109] Further, copper wiring structures 408, 409, and 410 in which
copper wiring patterns are embedded in an interlayer insulating
film are sequentially formed on the interlayer insulating film 405
by the damascene method or dual damascene method as described in
the previous example. Conductive plugs 413 made up of tungsten are
formed in via holes, whose side wall surfaces and bottom surfaces
are continuously covered with a barrier metal film 412 made up of a
conductive nitride film in which a TaN film and a TiN film are
laminated, in an interlayer insulating film 411 on the copper
wiring structure 410.
[0110] Further, wiring patterns 414A and 414B having a
configuration in which a conductor film made up of aluminum or an
aluminum alloy is sandwiched between TiN barrier metal films are
formed on the interlayer insulating film 411. Further, an
interlayer insulating film 415 is formed on the interlayer
insulating film 411 so as to cover the wiring patterns 414A and
414B.
[0111] Further, the surface of the interlayer insulating film 415
is covered with a passivation film 416 made up of SiN or the
like.
[0112] The problem of dissolution occurring in the copper seed
layer used as an electrode in the electrolytic plating step for the
copper layer, using the electrolytic plating solution, is
effectively suppressed by the reducing agent having a smaller
molecular weight than the accelerator that is added to the
electrolytic plating solution. As a result, it is possible to
sequentially fill fine recesses with the copper layer from the
lower portions to the upper portions,
[0113] The foregoing is considered as illustrative only of the
principles of the present invention. Further, since numerous
modifications and changes will readily occur to those skilled in
the art, it is not desired to limit the invention to the exact
construction and applications shown and described, and accordingly,
all suitable modifications and equivalents may be regarded as
failing within the scope of the invention in the appended claims
and their equivalents.
* * * * *