U.S. patent application number 12/320913 was filed with the patent office on 2009-09-10 for semiconductor device.
This patent application is currently assigned to FUJITSU MICROELECTRONICS LIMITED. Invention is credited to Toru Anezaki, Taiji Ema, Hideyuki Kojima, Tomohiko Tsutsumi.
Application Number | 20090224332 12/320913 |
Document ID | / |
Family ID | 35908857 |
Filed Date | 2009-09-10 |
United States Patent
Application |
20090224332 |
Kind Code |
A1 |
Tsutsumi; Tomohiko ; et
al. |
September 10, 2009 |
Semiconductor device
Abstract
An n-type embedded layer is formed in an N-LV region of a SRAM
cell region after an element isolation insulating film is formed on
a p-type Si substrate. Thereafter, a p-well and an n-well are
formed. In formation of a channel-doped layer, ion implantation is
also performed into the N-LV region of the SRAM cell region in
parallel with ion implantation into an N-LV of a logic circuit
region. Ion-implantation is further performed into the N-LV region
of the SRAM cell region in parallel with ion implantation into an
N-MV of an I/O region.
Inventors: |
Tsutsumi; Tomohiko;
(Kawasaki, JP) ; Anezaki; Toru; (Kawasaki, JP)
; Kojima; Hideyuki; (Kawasaki, JP) ; Ema;
Taiji; (Kawasaki, JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW, SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU MICROELECTRONICS
LIMITED
Tokyo
JP
|
Family ID: |
35908857 |
Appl. No.: |
12/320913 |
Filed: |
February 9, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11020257 |
Dec 27, 2004 |
7521765 |
|
|
12320913 |
|
|
|
|
Current U.S.
Class: |
257/392 ;
257/500; 257/E21.645; 257/E27.098; 438/275; 438/527 |
Current CPC
Class: |
H01L 27/1104 20130101;
H01L 27/11546 20130101; H01L 27/115 20130101; H01L 27/11526
20130101; H01L 27/11 20130101 |
Class at
Publication: |
257/392 ;
438/275; 257/500; 438/527; 257/E27.098; 257/E21.645 |
International
Class: |
H01L 27/11 20060101
H01L027/11; H01L 21/8239 20060101 H01L021/8239 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 17, 2004 |
JP |
2004-237696 |
Claims
1. A semiconductor device, comprising: a semiconductor substrate of
a first conductivity type; a first well of the first conductivity
type formed on a surface of said semiconductor substrate; a second
well of a second conductivity type formed on the surface of said
semiconductor substrate; a first transistor for a memory with a
channel of the first conductivity type, formed in said first well;
a second transistor for the memory with a channel of the second
conductivity type, formed in said second well; and an embedded well
of the second conductivity type formed directly under said first
well.
2. The semiconductor device according to claim 1, further
comprising: a first transistor for a peripheral circuit with a
channel of the first conductivity type, formed on the surface of
said semiconductor substrate; and a second transistor for the
peripheral circuit with a channel of the first conductivity type,
formed on the surface of said semiconductor substrate, operating
voltage of said first transistor for the memory and that of said
first transistor for the peripheral circuit being equal to each
other, and the operating voltage of said first transistor for the
memory and said second transistor for the peripheral circuit are
different from each other.
3. A manufacturing method of a semiconductor device, comprising the
step of forming a first transistor for a memory with a channel of a
first conductivity type, a first transistor for a peripheral
circuit with a channel of the first conductivity type and a second
transistor for the peripheral circuit with a channel of the first
conductivity type, on a surface of a semiconductor substrate, an
impurity profile of the channel of the first transistor for the
memory being made a total of that of the first transistor for the
peripheral circuit and that of the second transistor for the
peripheral circuit.
4. The manufacturing method of the semiconductor device according
to claim 3, wherein said step of forming the first transistor for
the memory, the first transistor for the peripheral circuit and the
second transistor for the peripheral circuit comprises the steps
of: introducing an impurity of the first conductivity type into a
region of the first transistor for the memory and a region of the
first transistor for the peripheral circuit; and introducing an
impurity of the first conductivity type into the region of the
first transistor for the memory and a region of the second
transistor for the peripheral circuit.
5. The manufacturing method of the semiconductor device according
to claim 3, wherein operating voltage of the first transistor for
the memory is made equal to that of the first transistor for the
peripheral circuit, and is made different from that of the second
transistor for the peripheral circuit.
6. The manufacturing method of the semiconductor device according
to claim 3, wherein a conductivity type of the semiconductor
substrate is made the first conductivity type, and said step of
forming the first transistor for the memory, the first transistor
for the peripheral circuit and the second transistor for the
peripheral circuit comprises the steps of: forming an embedded well
of the second conductivity type inside the semiconductor substrate;
forming a first well of the first conductivity type on the embedded
well on the surface of the semiconductor substrate; forming a
second well of the second conductivity type at a position spaced
from the first well on the surface of the semiconductor substrate;
and forming the first transistor for the memory in the first well
and forming a second transistor for the memory with the channel of
the second conductivity type in the second well.
7. A manufacturing method of a semiconductor device, comprising the
steps of: forming an embedded well of a second conductivity type
inside a semiconductor substrate of a first conductivity type;
forming a first well of the first conductivity type on the embedded
well on the surface of the semiconductor substrate; forming a
second well of the second conductivity type at a position spaced
from the first well on the surface of the semiconductor substrate;
and forming a first transistor for a memory with a channel of the
first conductivity type in the first well, and forming a second
transistor for the memory with a channel of the second conductivity
type in the second well.
8. The manufacturing method of the semiconductor device according
to claim 7, wherein said step of forming the first transistor for
the memory and the second transistor for the memory comprises the
step of forming first and second transistors for a peripheral
circuits with channels of the first conductive type on the surface
of the semiconductor substrate, and operating voltage of the first
transistor for the memory is made equal to that of the first
transistor for the peripheral circuit, and is made different from
that of the second transistor for the peripheral circuit.
9. The manufacturing method of the semiconductor device according
to claim 3, wherein a static random access memory is formed as the
memory.
10. The manufacturing method of the semiconductor device according
to claim 3, wherein said step of forming the first transistor for
the memory, the first transistor for the peripheral circuit and the
second transistor for the peripheral circuit comprises the step of
forming a non-volatile memory cell with a channel of the first
conductivity type on the surface of the semiconductor
substrate.
11. The manufacturing method of the semiconductor device according
to claim 6, wherein a structure of the first and the second wells
is a triple-well structure.
12. The manufacturing method of the semiconductor device according
to claim 3, wherein the first conductivity type is p-type, and the
second conductivity type is n-type.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No.
11/020,257, filed Dec. 27, 2004, which is based upon and claims the
benefit of priority from the prior Japanese Patent Application No.
2004-237696, filed on Aug. 17, 2004, the entire contents of which
are incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device
suitable for a SRAM and a manufacturing method of the same.
[0004] 2. Description of the Related Art
[0005] Recently, miniaturization of a transistor is pursued for the
purpose of high-density design and high performance of a
semiconductor device. However, in a SRAM (Static Random Access
Memory), the threshold voltage is reduced due to an inverse narrow
channel effect when the channel width of the transistor which
constitutes each memory cell (SRAM cell) is narrowed. As a result,
the operation margin of the SRAM cell becomes small.
[0006] Patent document 1 (Japanese Patent Application Laid-open No.
2000-58675) discloses a method in which in order to enhance the
threshold voltage of the transistor constituting an SPAM cell, a
step of introducing an impurity into only the transistor is added
besides the introduction of the impurity which is performed in
parallel with formation of a logic circuit and an input and output
circuit (I/O circuit).
[0007] Further, as described in Non-patent document 1 "The Impact
of Technology Scaling on Soft Error Rate Performance and Limits
Efficacy of Error Correction", IEDM 2002, as the high-density
design of a transistor advances, the soft error rate of the SRAM
cell increases, and therefore higher soft error resistance is
required.
[0008] A related art is described in Patent document 2 (Japanese
Patent Application Laid-open No. Hei 11-74378).
SUMMARY OF THE INVENTION
[0009] A first object of the present invention is to provide a
semiconductor device capable of securing an operation margin of a
SRAM cell widely and a manufacturing method of the same. A second
object of the present invention is to provide a semiconductor
device capable of enhancing soft error resistance and a
manufacturing method of the same.
[0010] As a result of repeating earnest study to solve the
above-described objects, the inventors of the present application
have conceived the modes of the invention which will be shown
below.
[0011] In a semiconductor device according to a first aspect of the
present invention, a semiconductor substrate, a first transistor
for a memory with a channel of a first conductivity type, formed on
a surface of the semiconductor substrate, a first transistor for a
peripheral circuit with a channel of the first conductivity type,
formed on the surface of the semiconductor substrate, and a second
transistor for the peripheral circuit with a channel of the first
conductivity type, formed on the surface of the semiconductor
substrate are provided. An impurity profile of the channel of the
first transistor for the memory is a total of that of the first
transistor for the peripheral circuit and that of the second
transistor for the peripheral circuit.
[0012] In a semiconductor device according to a second aspect of
the present invention, a semiconductor substrate of a first
conductivity type, a first well of the first conductivity type
formed on a surface of the semiconductor substrate, a second well
of a second conductivity type formed on the surface of the
semiconductor substrate, and an embedded well of the second
conductivity type formed directly under the first well are
provided. A first transistor for a memory with a channel of the
first conductivity type is formed in the first well, and a second
transistor for the memory with a channel of the second conductivity
type is formed in the second well.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is an equivalent circuit diagram showing a
constitution of a SRAM cell;
[0014] FIG. 2 is a graph showing the relationship between the
threshold voltage of a driver transistor Dr and the rate of memory
cells operating normally;
[0015] FIG. 3 is a graph showing the relationship between the
threshold voltage of a transfer transistor Tr and the rate of SRAM
cells operating normally;
[0016] FIGS. 4A and 4B are sectional views showing a conventional
manufacturing method of a semiconductor device, concerning the
formation of a channel;
[0017] FIGS. 5A and 5B are sectional views showing a manufacturing
method of a semiconductor device according to a first aspect of the
present invention, concerning the formation of a channel;
[0018] FIGS. 6A and 6B are sectional views showing a mechanism of
occurrence of a soft error;
[0019] FIGS. 7A and 7B are sectional views showing an example of
the measure against the soft error;
[0020] FIGS. 8A and 8B are sectional views showing an example of
the measure against the soft error according to a second aspect of
the present invention;
[0021] FIGS. 9A, 9B and 9C are sectional views showing a
conventional manufacturing method of a semiconductor device
concerning the formation of wells;
[0022] FIGS. 10A, 10B and 10C are sectional views showing a
manufacturing method of a semiconductor device according to a
second aspect of the present invention, concerning the formation of
wells;
[0023] FIG. 11A to FIG. 11S are sectional views showing a
manufacturing method of a semiconductor device according to a first
embodiment of the present invention in the sequence of the process
steps;
[0024] FIG. 12A to FIG. 12T are sectional views showing a
manufacturing method of a semiconductor device according to a
second embodiment of the present invention in the sequence of the
process steps; and
[0025] FIG. 13A to FIG. 13Z are sectional views showing a
manufacturing method of a semiconductor device according to a third
embodiment of the present invention in the sequence of the process
steps.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0026] When the method described in Document 1 is adopted
concerning an operation margin of a SRAM cell, the number of
process steps increases, and thus the cost increases. When a
non-volatile memory is mixedly mounted on one chip in addition to a
high-speed logic circuit loaded with the SRAM, an element isolation
insulating film is formed by STI (Shallow Trench Isolation) in
order to form a high voltage resistance CMOS transistor of the
non-volatile memory, it is desirable to make the amount of rounding
oxidation larger than a certain fixed amount. The inventors have
found out that when such oxidation is performed, the channel width
of the SRAM cell in the high-speed logic circuit becomes narrower
and the operation margin of the SRAM cell is significantly
reduced.
[0027] When the non-volatile memory is mixedly mounted, the number
of process steps is increased by the number of steps of forming the
nonvolatile memory, and thus the manufacturing cost increases as
compared with an ordinary high-speed logic circuit loaded with a
SRAM. Therefore, it is the problem how the increase in the number
of steps is reduced and the operation margin of the SRAM cell is
secured.
[0028] Similarly, concerning the countermeasure against the soft
error, it is the problem how the increase in the number of steps is
reduced and the increase in the soft error rate is suppressed even
when the high-density design advances.
[0029] --Gist of the Present Invention--
[0030] The gist of the present invention will be explained. FIG. 1
is an equivalent circuit diagram showing a constitution of a SPRAM
cell. This SPRAM cell is provided with two transfer transistors Tr
connected to bit lines BL, and two driver transistors Dr and two
load transistors Lo, which constitute one flip flop circuit. Gates
of the two transfer transistors Tr are connected to the same word
line WL.
[0031] When, For the SRAM cells of such circuit constitution, the
inventors of the present application examined the relationship
between the threshold voltage and the number of the SRAM cells
operating normally, the results shown in FIG. 2 and FIG. 3 were
obtained. In this examination, the number of memory cells which
operated normally when the power supply voltage (Vcc) was set at
1.2 V was set as the reference (Pass rate:1), and the rate of the
number of memory cells which operated normally when the power
supply voltage was set at 0.8 V was obtained. FIG. 2 shows the
relationship between the threshold voltage of the driver transistor
Dr and the rate of the memory cells which operate normally, and
FIG. 3 shows the threshold voltage of the transfer transistor Tr
and the rate of the SRAM cells which operate normally. As shown in
FIG. 2 and FIG. 3, as the threshold voltage becomes lower, the rate
of the SRAM cells which operate normally decreases even at a low
power supply voltage. From the inverse point of view, it is
effective to enhance the threshold voltage in order to make the
SRAM cells operate normally even at a low power supply voltage.
However, if an exclusive step as described in Patent Document 1 is
added, the number of steps increases and the cost is increased.
[0032] Thus, in the first aspect of the present invention, in
forming a low voltage operation transistor and a middle voltage
operation transistor, which operates at a higher voltage than the
low voltage transistor, in the same chip, in parallel with the
transistor constituting the SRAM cell, ion-implantation is
performed for the transistor constituting the SRAM cell in parallel
with the formation of a channel dope layer of the transistor of the
low voltage operation, and ion implantation is performed for the
transistor which constitutes the SRAM cell in parallel with the
formation of a channel dope layer of the transistor of the middle
voltage operation.
[0033] As shown in FIGS. 4A and 4B, in the conventional
manufacturing method, the low voltage operation nMOS transistor
(N-LN) for the SRAM cell, the low voltage operation nMOS transistor
(N-LV) for the logic circuit and the medium voltage operation nMOS
transistor (N-MV) for the I/O circuit are formed in parallel in one
chip. Namely, as shown in FIG. 4A, for the p-type Si substrate 301
on which element isolation insulating films 302 are formed, channel
doped layers 303 are formed by performing ion-implantation in the
SRAM cell region and the logic circuit region, and thereafter, as
shown in FIG. 4B, a channel doped layer 304 is formed by performing
ion implantation in the I/O circuit region.
[0034] In contrast to this, in the first aspect of the present
invention, as shown in FIG. 5A, for a p-type Si substrate 201 on
which element isolation insulating films 202 are formed, channel
doped layers 203 are formed by performing ion-implantation in the
SRAM cell region and the logic circuit region, and thereafter, as
shown in FIG. 5B, channel doped layers 204 are formed by performing
ion-implantation not only in the I/O circuit region but also in the
SRAM cell region. As a result, as for the nMOS transistor, the
impurity profile in the SRAM cell region corresponds to the total
of the impurity profile in the I/O circuit region and the impurity
profile in the logic circuit region.
[0035] According to the above method, the threshold voltage of the
transistor constituting the SRAM cell can be enhanced without
changing the characteristics of the peripheral circuits such as the
logic circuit and the I/O circuit, or without adding a new process
step, and the transistor can be normally operated at low voltage
and a large operation margin can be secured by extension.
[0036] As described above, it is desired to further enhance the
soft error resistance. Here, the occurrence mechanism of the soft
error will be explained. Assume that a p-well 314 and an n-well 317
are formed on a p-type Si substrate 301, and an n.sup.+ diffusion
layer 318 and a p.sup.+ diffusion layer 319 are formed in the
respective p-well 314 and the n-well 317, as shown FIG. 6A. In the
semiconductor device of such a structure, depletion layers 320
exist in the vicinity of the borders between the n-type regions and
the p-type regions. When .alpha.-ray is incident on such a state,
positive and negative electric charges are induced as shown in FIG.
6A. As a result, as shown in FIG. 6B, as the electric charges move,
the depletion layers changes. On this occasion, the moving amount
of the electrons to the n.sup.+ diffusion layer 318 becomes large,
and the soft error occurs. On the other hand, the moving amount of
the positive holes to the p.sup.+ diffusion layer 319 is not as
large as the moving amount of the electrons, and the soft error due
to this movement hardly occurs.
[0037] Thus, as shown in FIG. 7A, it is considered to form an
n.sup.+ well 321 between the Si substrate 301 and each of the wells
314 and 317. By forming the n.sup.+ wells 321, even when the
electric charges are induced by irradiation of the .alpha.-ray as
shown in FIG. 7A, the change in the depletion layers 320 is
decreased as shown in FIG. 7B. Accordingly, as for the nMOS
transistor, the soft error resistance is enhanced. However, the
change amount of the depletion layer 320 in the pMOS transistor
increases, and it cannot be said that the soft error resistance is
enhanced as a whole.
[0038] Thus, the inventors of the present application formed the
n.sup.+ well 321 between the Si substrate 301 and the p-well 314
for only the nMOS transistor, and the Si substrate 301 and the
n-well 317 were made in contact with each other in the pMOS
transistor as shown in FIG. 8A. Thereby, the inventors have found
out that the change amount of the depletion layer 320 becomes small
as shown in FIG. 8B, and the soft error resistance could be
enhanced for both the nMOS transistor and the pMOS transistor.
[0039] In the conventional manufacturing method, as for the process
steps up to the formation of the wells, after the element isolation
insulating films 302 are formed on the surface of the p-type Si
substrate 301 as shown in FIG. 9A, the p-wells 312 are formed in
the element active regions in which the nMOS transistors are to be
formed in the SRAM cell region, the logic circuit region and the
I/O circuit region as shown in FIG. 9B. Next, the p-wells 313 of
the higher impurity concentration are formed in the p-wells 312.
Thereafter, as shown in FIG. 9C, the n-well 315 is formed in the
element active region in which the pMOS transistor is to be formed
in the SRAM cell region, the logic circuit region and the I/O
circuit region, and thereafter, the n-well 316 of the higher
impurity concentration is formed in the n-well 315.
[0040] In contrast to this, in the second aspect of the present
invention, as shown in FIG. 10A, after the element isolation
insulating films 202 are formed on the surface of the p-type Si
substrate 201, an n-type buried layer 211 is formed by, for
example, ion implantation. Next, as shown in FIG. 10B, p-wells 212
are formed in the element active regions in which the nMOS
transistors are to be formed in the SRAM cell region, the logic
circuit region and the I/O circuit region. Next, p-wells 213 of
higher impurity concentration are formed in the p-wells 212.
Thereafter, as shown in FIG. 10C, an n-well 215 is formed in the
element active region in which the pMOS transistor is to be formed
in the SRAM cell region, the logic circuit region and the I/O
circuit region, and thereafter an n-well 216 of the higher impurity
concentration is formed in the n-well 215.
[0041] In the semiconductor device manufactured according to such a
method, the change in the depletion layer in the SRAM cell is
suppressed even if .alpha.-ray is irradiated, and thus the soft
error hardly occurs.
[0042] Embodiments of the present invention will be concretely
explained hereinafter with reference to the attached drawings.
However, the sectional structure of the semiconductor device will
be explained with the manufacturing method thereof for
convenience.
First Embodiment
[0043] Initially, a first embodiment of the present invention will
be explained. FIG. 11A to FIG. 11S are sectional views showing a
manufacturing method of a semiconductor device according to a first
embodiment of the present invention. In this embodiment, an I/O
circuit, a logic circuit and a SRAM cell each including an nMOS
transistor and a PMOS transistor are formed in one chip. In a logic
circuit region and a SRAM cell region, the transistors operated at
low voltage are formed, and the transistors operated at higher
voltage (medium voltage) are formed in the I/O circuit region. A
region in which the nMOS transistor operated at a low voltage is
formed is called an N-LV region, a region in which the pMOS
transistor operated at a low voltage is formed is called a P-LV
region, a region in which the nMOS transistor operated at a medium
voltage is formed is called an N-MV region, and a region in which
the pMOS transistor operated at a medium voltage is formed is
called a P-MV region.
[0044] In the first embodiment, element isolation insulating films
29 are formed on a surface of an Si substrate 1 first as shown in
FIG. 11A. Next, by thermally oxidizing (sacrificial oxidation) the
surface of the Si substrate 1, an Si oxidation film (not shown) of
the thickness of about 10 nm is formed.
[0045] Next, as shown in FIG. 11B, a photoresist mask 100 exposing
the N-MY region and the N-LV regions is formed by a
photolithography technique. Thereafter, by performing ion
implantation with the photoresist mask 100 as a mask, p-wells 2 and
3 are formed. In formation of the p-well 2, for example, boron ion
is ion-implanted under the condition of the acceleration energy:
400 keV and the dose amount: 1.5.times.10.sup.13 cm.sup.-2. In
formation of the p-well 3, for example, boron ion is ion-implanted
under the condition of the acceleration energy: 100 keV and the
dose amount: 8.times.10.sup.12 cm.sup.-2. As a result, the p-well
of higher impurity concentration is formed in the p-well 2.
[0046] Subsequently, as shown in FIG. 1C, the photoresist mask 100
is removed by, for example, ashing. Next, a photoresist mask 101
exposing the P-MV region and the P-LV regions is formed by a
photolithography technique. Next, with the photoresist mask 101 as
a mask, ion implantation is performed, and thereby, n-wells 4 and 5
are formed. In formation of the n-wells 4, for example, phosphorus
ion is ion-implanted under the condition of the acceleration
energy: 600 keV and the dose amount: 1.5.times.10.sup.13 cm.sup.-2.
In formation of the n-wells 5, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 240
keV, and the dose amount: 5.times.10.sup.12 cm.sup.-2. As a result,
the n-well 5 of higher impurity concentration is formed in each of
the n-wells 4.
[0047] Next, as shown in FIG. 1D, the photoresist mask 101 is
removed by, for example, ashing. Thereafter, a photoresist mask 102
exposing the N-LV regions is formed by a photolithography
technique. Thereafter, with the photoresist mask 102 as a mask, ion
implantation is performed, and thereby, channel doped layers 6 are
formed as a p-type threshold voltage control impurity layer. In
formation of the channel-doped layers 6, for example, boron ion is
ion-implanted under the condition of the acceleration energy: 15
keV and the dose amount: 8.times.10.sup.12 cm.sup.-2.
[0048] Subsequently, as shown in FIG. 11E, the photoresist mask 102
is removed by, for example, ashing. Next, a photoresist mask 103
exposing the P-LV regions is formed by a photolithography
technique. Next, with the photoresist mask 103 as a mask, ion
implantation is performed, and thereby, channel doped layers 7 are
formed as an n-type threshold voltage control impurity layer. In
formation of the channel-doped layers 7, for example, arsenic ion
is ion-implanted under the condition of the acceleration energy:
150 keV and the dose amount: 3.times.10.sup.12 cm.sup.-2.
[0049] Thereafter, as shown in FIG. 1F, the photoresist mask 103 is
removed by, for example, ashing. Subsequently, a photoresist mask
104 exposing the N-MV region and the N-LV region of the SRAM cell
region is formed by a photolithography technique. Next, with the
photoresist mask 104 as a mask, ion implantation is performed, and
thereby, channel doped layers 8 are formed as the threshold voltage
control impurity layers. Accordingly, in the N-LV region of the
SRAM cell region, the channel doped layers 6 and 8 are formed.
Namely, the N-LV region of the SRAM cell region is in the same
state as the state shown in FIG. 5B. In formation of the
channel-doped layer 8, for example, boron ion is ion-implanted
under the condition of the acceleration energy: 35 keV and the dose
amount: 4.5.times.10.sup.12 cm.sup.-2.
[0050] Next, as shown in FIG. 11G, the photoresist mask 104 is
removed by, for example, ashing. Thereafter, a photoresist mask 105
exposing the P-MV region is formed by a photolithography technique.
Subsequently, with the photoresist mask 105 as a mask, ion
implantation is performed, and thereby, a channel doped layer 9 is
formed as the n-type threshold voltage control impurity layers. In
formation of the channel-doped layers 9, for example, arsenic ion
is ion-implanted under the condition of the acceleration energy:
150 keV and the dose amount: 2.times.10.sup.12 cm.sup.-2.
[0051] Next, as shown in FIG. 11H, the photoresist mask 105 is
removed by, for example, ashing. Next, silicone oxide films each of
the film thickness of about 7 nm are formed on the active regions
of the N-MV region, the P-MV region, the N-LV regions and the P-LV
regions as gate insulation films 30 by performing thermal oxidation
at, for example, the temperature of 850.degree. C.
[0052] Next, as shown in FIG. 11I, a photoresist mask 106 covering
the N-MV region and the P-MV region and exposing the regions in
which the low-voltage transistors are to be formed (the N-LV
regions and the P-LV regions) is formed by a photolithography
technique. Thereafter, by wet etching using, for example, a
hydrofluoric acid aqueous solution, the gate insulation films 30
are etched with the photoresist masks 106 as a mask. As a result,
the gate insulation films 30 in the N-LV regions and the P-LV
regions are removed.
[0053] Subsequently, as shown in FIG. 11J, the photoresist mask 106
is removed by, for example, ashing. Next, silicone oxide films each
of the film thickness of about 1.8 nm are formed on the active
regions of the N-LV regions and the P-LV formation regions as gate
insulation films 31 by performing thermal oxidation at, for
example, the temperature of 850.degree. C. The film thickness of
the gate insulation film 30 increases up to about 8.8 nm by this
thermal oxidation.
[0054] Next, as shown in FIG. 11K, a polysilicon film 32 of the
film thickness of about 180 nm, for example, is formed by a CVD
method, and a silicon nitride film 33 of the film thickness of
about 30 nm, for example, is formed on the polysilicon film 32 as a
etching mask also serving as an antireflection film.
[0055] Thereafter, as shown in FIG. 11L, the polysilicon film 32 is
patterned by a photolithography technique and a dry etching
technique, and thereby gate electrodes 34 are formed in the N-MV
region, the P-MV region, the N-LV regions and the P-LV regions. At
this time, the width of each of the gate electrodes 34 in the N-MV
region and the P-MV region is made larger than the width of each of
the gate electrodes 34 in the N-LV regions and the P-LV
regions.
[0056] Subsequently, as shown in FIG. 11M, a photoresist mask 107
exposing the N-MV region and covering the other regions is formed
by a photolithography technique. Next, an extension layer 21 for
forming a source/drain of the N-MV region is formed by performing
ion implantation with the photoresist mask 107 as a mask. In
formation of the extension layer 21, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 35
keV and the dose amount: 4.times.10.sup.13 cm.sup.-2.
[0057] Next, as shown in FIG. 11N, the photoresist mask 107 is
removed by, for example, ashing. Thereafter, a photoresist mask 108
exposing the P-MV region and covering the other regions is formed
by a photolithography technique. Subsequently, an extension layer
22 for forming a source/drain of the P-MV region is formed by
performing ion implantation with the photoresist mask 108 as a
mask. In formation of the extension layer 22, for example, boron
fluoride ion is ion-implanted under the condition of the
acceleration energy: 10 keV and the dose amount: 4.times.10.sup.13
cm.sup.-2.
[0058] Next, as shown in FIG. 11O, the photoresist mask 108 is
removed by, for example, ashing. Next, a photoresist mask 109
exposing the N-LV regions and covering the other regions is formed
by a photolithography technique. Thereafter, ion-implantation is
performed with the photoresist mask 109 as a mask, and thereby,
extension layers 23 for forming sources/drains of the N-LV regions
are formed. In formation of the extension layer 23, for example,
arsenic ion is ion-implanted under the condition of the
acceleration energy: 3 keV and the dose amount: 1.times.10.sup.15
cm.sup.-2, and thereafter, boron fluoride ion is ion-implanted from
the four directions inclined 28 degrees from the normal line of the
Si substrate 1 under the condition of the acceleration energy: 80
keV and the dose amount: 4.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layer 23 becomes an extension layer including
a pocket layer (not shown).
[0059] Subsequently, as shown in FIG. 11P, the photoresist mask 109
is removed by, for example, ashing. Next, a photoresist mask 110
exposing the P-LV regions and covering the other regions is formed
by a photolithography technique. Next, ion-implantation is
performed with the photoresist mask 110 as a mask, and thereby,
extension layers 24 for forming sources/drains of the P-LV regions
are formed. In formation of the extension layer 24, for example,
boron ion is ion-implanted under the condition of the acceleration
energy: 0.5 keV and the dose amount: 6.times.10.sup.14 cm.sup.-2,
and thereafter, arsenic ion is ion-implanted from the four
directions inclined 28 degrees from the normal line of the Si
substrate 1 under the condition of the acceleration energy: 120 keV
and the dose amount: 5.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layer 24 becomes an extension layer including
a pocket layer (not shown).
[0060] Thereafter, as shown in FIG. 11Q, the photoresist mask 110
is removed by, for example, ashing. Subsequently, after a silicon
oxide film is deposited by, for example, a thermal CVD method, the
silicon oxide film is etched back, and thereby side walls (side
wall insulation films) 35 constituted of the silicon oxide film are
formed on side wall portions of the gate electrodes 34. Next, a
photoresist mask 111 exposing the P-MV region and the P-LV regions
is formed by a photolithography technique. Next, by performing ion
implantation with the photoresist mask 111 as a mask, source/drain
diffusion layers (SD diffusion layer) 25 constituting the
sources/drains of the pMOS transistors (transistors in the P-MV
region and the P-LV regions) are formed. In formation of the SD
diffusion layers 25, for example, boron ion is ion-implanted under
the condition of the acceleration energy: 5 keV and the dose
amount: 4.times.10.sup.15 cm.sup.-2. The conductivity type of the
gate electrode 34 of the pMOS transistor becomes p-type by this ion
implantation.
[0061] Thereafter, as shown in FIG. 11R, the photoresist mask 111
is removed by, for example, ashing. Next, a photoresist mask 112
exposing the N-MV region and the N-LV regions is formed by a
photolithography technique. Next, by performing ion implantation
with the photoresist mask 112 as a mask, SD diffusion layers 26
constituting the sources/drains of the nMOS transistors
(transistors in the N-MV region and the N-LV regions) are formed.
In formation of the SD diffusion layer 26, for example, phosphorus
ion is ion-implanted under the condition of the acceleration
energy: 10 keV and the dose amount: 6.times.10.sup.15 cm.sup.-2.
The conductivity type of the gate electrode 34 of the nMOS
transistor becomes n-type by this ion implantation.
[0062] Thereafter, as shown in FIG. 11S, the photoresist mask 112
is removed by, for example, ashing. Subsequently, silicide layers
36 are formed on the gate electrodes 34 and the SD diffusion layers
25 and 26 by a known salicide process. Subsequently, an interlayer
insulation film 37 is formed on the entire surface, and thereafter
contact holes are formed. After contact plugs 38 are formed in the
contact holes, wirings 39 are formed on the interlayer insulation
film 37. In this manner, the steps up to the first metal wiring
layer are completed. As the interlayer insulation film 37, an Si
oxide film of the thickness of about 600 nm is formed by, for
example, an HDP method.
[0063] Thereafter, a further upper wiring layer and interlayer
insulation films and the like are formed, and the logic circuit
element (semiconductor device) loaded with the SRAM is
completed.
[0064] In the semiconductor device manufactured according to the
above method, the impurity profile of the channel in the N-LV
region in the SRAM cell region is the total of the impurity profile
of the channel in the N-LV region of the logic circuit region and
the impurity profile of the channel in the N-MV region of the I/O
circuit region. Therefore, the threshold voltage becomes higher,
and the wide operation margin can be obtained. In manufacturing,
introduction of the impurity into only the channel of the N-LV
region of the SRAM cell region is not required, and therefore it is
possible to avoid an increase in the number of process steps and a
rise in the cost following this.
Second Embodiment
[0065] Next, a second embodiment of the present invention will be
explained. FIGS. 12A to 12T are sectional views showing a
manufacturing method of a semiconductor device according to a
second embodiment of the present invention. In this embodiment, the
I/O circuit, the logic circuit and the SRAM cell including nMOS
transistors and pMOS transistors respectively are also formed in
one chip, as in the first embodiment.
[0066] In the second embodiment, element isolation insulating films
29 are formed on surfaces of an Si substrate 1 by the STI first as
shown in FIG. 12A. Next, by thermally oxidizing (sacrificial
oxidation) the surface of the Si substrate 1, an Si oxide film (not
shown) of the thickness of about 10 nm is formed.
[0067] Next, as shown in FIG. 12B, a photoresist mask 120 exposing
the N-LV region of the SRAM cell region is formed by a
photolithography technique. Thereafter, by performing ion
implantation with the photoresist mask 120 as a mask, an n-type
embedded layer 20 is formed. In formation of the n-type embedded
layer 20, for example, phosphorus ion is ion-implanted under the
condition of the acceleration energy: 2 MeV and the dose amount:
2.times.10.sup.13 cm.sup.-2. The depth of the embedded layer 20
from the substrate surface is about 2 .mu.m, for example.
[0068] Subsequently, as shown in FIG. 12C, the photoresist mask 120
is removed by, for example, ashing. Next, a photoresist mask 100
exposing the N-MV region and the N-LV regions is formed by a
photolithography technique. Thereafter, with the photoresist mask
100 as a mask, ion implantation is performed, and thereby, p-wells
2 and 3 are formed. In formation of the p-wells 2, for example,
boron ion is ion-implanted under the condition of the acceleration
energy: 400 keV and the dose amount: 1.5.times.10.sup.13 cm.sup.-2.
In formation of the p-wells 3, for example, boron ion is
ion-implanted under the condition of the acceleration energy: 100
keV and the dose amount: 2.times.10.sup.12 cm.sup.-2. As a result,
the p-well 3 of higher impurity concentration is formed in each of
the p-wells 2.
[0069] Subsequently, as shown in FIG. 12D, the photoresist mask 100
is removed by, for example, ashing. Next, a photoresist mask 101
exposing the P-MV region and the P-LV regions is formed by a
photolithography technique. Next, with the photoresist mask 101 as
a mask, ion implantation is performed, and thereby, n-wells 4 and 5
are formed. In formation of the n-wells 4, for example, phosphorus
ion is ion-implanted under the condition of the acceleration
energy: 600 keV and the dose amount: 1.5.times.10.sup.13 cm.sup.-2.
In formation of the n-wells 5, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 240
keV and the dose amount: 5.times.10.sup.12 cm.sup.-2. As a result,
the n-well 5 of higher impurity concentration is formed in each of
the n-wells 4.
[0070] Next, as shown in FIG. 12E, the photoresist mask 101 is
removed by, for example, ashing. Thereafter, a photoresist mask 102
exposing the N-LV regions is formed by a photolithography
technique. Thereafter, with the photoresist mask 102 as a mask, ion
implantation is performed, and thereby, channel doped layers 6 are
formed as a p-type threshold voltage control impurity layer. In
formation of the channel-doped layers 6, for example, boron ion is
ion-implanted under the condition of the acceleration energy: 15
keV and the dose amount: 8.times.10.sup.12 cm.sup.-2.
[0071] Subsequently, as shown in FIG. 12F, the photoresist mask 102
is removed by, for example, ashing. Next, a photoresist mask 103
exposing the P-LV regions is formed by a photolithography
technique. Next, with the photoresist mask 103 as a mask, ion
implantation is performed, and thereby, channel doped layers 7 are
formed as an n-type threshold voltage control impurity layer. In
formation of the channel-doped layers 7, for example, arsenic ion
is ion-implanted under the condition of the acceleration energy:
150 keV and the dose amount: 3.times.10.sup.12 cm.sup.-2.
[0072] Thereafter, as shown in FIG. 12G, the photoresist mask 103
is removed by, for example, ashing. Subsequently, a photoresist
mask 104 exposing the N-MV region and the N-LV region of the SRAM
cell region is formed by a photolithography technique. Next, with
the photoresist mask 104 as a mask, ion implantation is performed,
and thereby, channel doped layers 8 are formed as the p-type
threshold voltage control impurity layer. Accordingly, in the N-LV
region of the SRAM cell region, the channel doped layers 6 and 8
are formed. Namely, the N-LV region of the SRAM cell region is in
the same state as the state shown in FIG. 5B. In formation of the
channel-doped layers 8, for example, boron ion is ion-implanted
under the condition of the acceleration energy: 35 keV and the dose
amount: 4.5.times.10.sup.12 cm.sup.-2.
[0073] Next, as shown in FIG. 12H, the photoresist mask 104 is
removed by, for example, ashing. Thereafter, a photoresist mask 105
exposing the P-MV region is formed by a photolithography technique.
Subsequently, with the photoresist mask 105 as a mask, ion
implantation is performed, and thereby, a channel doped layer 9 is
formed as the n-type threshold voltage control impurity layer. In
formation of the channel-doped layer 9, for example, arsenic ion is
ion-implanted under the condition of the acceleration energy: 150
keV and the dose amount: 2.times.10.sup.12 cm.sup.-2.
[0074] Next, as shown in FIG. 12I, the photoresist mask 105 is
removed by, for example, ashing. Next, silicone oxide films each of
the film thickness of about 7 nm are formed on the active regions
of the N-MV region, the p-MV region, the N-LV regions and the P-LV
regions as gate insulation films 30 by performing thermal oxidation
at, for example, the temperature of 850.degree. C.
[0075] Next, as shown in FIG. 12J, a photoresist mask 106 covering
the N-MV region and the P-MV region and exposing the regions in
which the low-voltage transistors are formed (the N-LV regions and
the P-LV regions) is formed by a photolithography technique.
Thereafter, by wet etching using, for example, a hydrofluoric acid
aqueous solution, the gate insulation films 30 are etched with the
photoresist mask 106 as a mask. As a result, the gate insulation
films 30 in the N-LV regions and the P-LV regions are removed.
[0076] Subsequently, as shown in FIG. 12K, the photoresist mask 106
is removed by, for example, ashing. Next, silicone oxide films each
of the film thickness of about 1.8 nm are formed on the active
regions of the N-LV regions and the P-LV formation regions as gate
insulation films 31 by performing thermal oxidation at, for
example, the temperature of 850.degree. C. The film thickness of
the gate insulation film 30 increases up to about 8.8 nm by this
thermal oxidation.
[0077] Next, as shown in FIG. 12L, a polysilicon film 32 of the
film thickness of about 180 nm, for example, are formed by a CVD
method, and a silicon nitride film 33 of the film thickness of
about 30 nm, for example, is formed on the polysilicon film 32 as a
etching mask also serving as an antireflection film.
[0078] Thereafter, as shown in FIG. 12M, the polysilicon film 32 is
patterned by a photolithography technique and a dry etching
technique, and thereby gate electrodes 34 are formed in the N-MV
region, the P-MV region, the N-LV regions and the P-LV regions. At
this time, the width of each of the gate electrodes 34 in the N-MV
region and the P-MV region is made larger than the width of each of
the gate electrodes 34 in the N-LV regions and the P-LV
regions.
[0079] Subsequently, as shown in FIG. 12N, a photoresist mask 107
exposing the N-MV region and covering the other regions is formed
by a photolithography technique. Next, an extension layer 21 for
forming a source/drain of the N-MV region is formed by performing
ion implantation with the photoresist mask 107 as a mask. In
formation of the extension layer 21, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 35
keV and the dose amount: 4.times.10.sup.13 cm.sup.-2.
[0080] Next, as shown in FIG. 120, the photoresist mask 107 is
removed by, for example, ashing. Thereafter, a photoresist mask 108
exposing the P-MV region and covering the other regions is formed
by a photolithography technique. Subsequently, an extension layer
22 for forming a source/drain of the P-MV region is formed by
performing ion implantation with the photoresist mask 108 as a
mask. In formation of the extension layer 22, for example, boron
fluoride ion is ion-implanted under the condition of the
acceleration energy: 10 keV and the dose amount: 4.times.10.sup.13
cm.sup.-2.
[0081] Next, as shown in FIG. 12P, the photoresist mask 108 is
removed by, for example, ashing. Next, a photoresist mask 109
exposing the N-LV regions and covering the other regions is formed
by a photolithography technique. Thereafter, ion-implantation is
performed with the photoresist mask 109 as a mask, and thereby,
extension layers 23 to constitute sources/drains of the N-LV
regions are formed. In formation of the extension layers 23, for
example, arsenic ion is ion-implanted under the condition of the
acceleration energy: 3 keV and the dose amount: 1.times.10.sup.15
cm.sup.-2, and thereafter, boron fluoride ion is ion-implanted from
the four directions inclined 28 degrees from the normal line of the
Si substrate 1 under the condition of the acceleration energy: 80
keV and the dose amount: 4.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layers 23 become the extension layers
including pocket layers (not shown).
[0082] Subsequently, as shown in FIG. 12Q, the photoresist mask 109
is removed by, for example, ashing. Next, a photoresist mask 110
exposing the P-LV regions and covering the other regions is formed
by a photolithography technique. Next, ion-implantation is
performed with the photoresist mask 110 as a mask, and thereby,
extension layers 24 to constitute sources/drains of the P-LV
regions are formed. In formation of the extension layers 24, for
example, boron ion is ion-implanted under the condition of the
acceleration energy: 0.5 keV and the dose amount: 6.times.10.sup.14
cm.sup.-2, and thereafter, arsenic ion is ion-implanted from the
four directions inclined 28 degrees from the normal line of the Si
substrate 1 under the condition of the acceleration energy: 120 keV
and the dose amount: 5.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layers 24 also become the extension layers
including pocket layers (not shown).
[0083] Thereafter, as shown in FIG. 12R, the photoresist mask 110
is removed by, for example, ashing. Subsequently, after a silicon
oxide film is deposited by, for example, a thermal CVD method, the
silicon oxide film is etched back, and thereby side walls (side
wall insulation films) 35 constituted of the silicon oxide film are
formed on side wall portions of the gate electrodes 34. Next, a
photoresist mask 111 exposing the P-MV region and the P-LV regions
is formed by a photolithography technique. Next, by performing ion
implantation with the photoresist mask 111 as a mask, source/drain
diffusion layers (SD diffusion layers) 25 to constitute the
sources/drains of the pMOS transistors (transistors in the P-MV
region and the P-LV regions) are formed. In formation of the SD
diffusion layers 25, for example, boron ion is ion-implanted under
the condition of the acceleration energy: 5 keV and the dose
amount: 4.times.10.sup.15 cm.sup.-2. The conductivity type of the
gate electrode 34 of the pMOS transistor becomes p-type by this ion
implantation.
[0084] Thereafter, as shown in FIG. 12S, the photoresist mask 111
is removed by, for example, ashing. Next, a photoresist mask 112
exposing the N-MV region and the N-LV regions is formed by a
photolithography technique. Next, by performing ion implantation
with the photoresist mask 112 as a mask, SD diffusion layers 26 to
constitute the sources/drains of the nMOS transistors (transistors
in the N-MV region and the N-LV regions) are formed. In formation
of the SD diffusion layers 26, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 10
keV and the dose amount: 6.times.10.sup.15 cm.sup.-2. The
conductivity type of the gate electrode 34 of the nMOS transistor
becomes n-type by this ion implantation.
[0085] Thereafter, as shown in FIG. 12T, the photoresist mask 112
is removed by, for example, ashing. Subsequently, silicide layers
36 are formed on the gate electrodes 34 and the SD diffusion layers
25 and 26 by a known salicide process. Subsequently, an interlayer
insulation film 37 is formed on the entire surface, and thereafter,
contact holes are formed. After contact plugs 38 are formed in the
contact holes, wirings 39 are formed on the interlayer insulation
film 37. In this manner, the steps up to the first metal wiring
layer are completed. As the interlayer insulation film 37, the Si
oxide film of the thickness of about 600 nm is formed by, for
example, a HDP method.
[0086] Thereafter, further upper wiring layer and interlayer
insulation film and the like are formed, and the logic circuit
element (semiconductor device) loaded with the SRAM is
completed.
[0087] In the semiconductor device manufactured according to the
above method, the n-type embedded layer 20 is formed directly under
the p-well 2, and therefore even when a rays are incident thereon,
a change in the depletion layer in the nMOS transistor is
suppressed, thus enhancing the soft error resistance. The embedded
layer 20 is not formed under the n-well 4, the soft error
resistance in the pMOS transistor is not reduced unnecessarily.
[0088] In the second embodiment, the channel doped layer in the
N-LV region of the SRAM cell region does not have to be made a dual
structure.
Third Embodiment
[0089] Next, a third embodiment of the present invention will be
explained. FIG. 13A to FIG. 13Z are sectional views showing a
manufacturing method of a semiconductor device according to the
third embodiment of the present invention. In this embodiment, not
only an I/O circuit, a logic circuit and a SRAM cell respectively
including nMOS transistors and PMOS transistors, but also a flash
memory is formed in one chip. In this embodiment, not only a
transistor operated at low voltage but also an nMOS transistor and
a pMOS transistor operating at higher voltage than the transistor
constituting the I/O circuit are formed. Hereinafter, a region in
which the nMOS transistor operating at high voltage is formed will
be called an N-HV region, an area in which the pMOS transistor
operating at high voltage is formed will be called a P-HV
region.
[0090] In the third embodiment, as shown in FIG. 13A, element
isolation insulating films 29 are formed on a surface of an Si
substrate 1 first as shown in FIG. 13A. Next, by thermally
oxidizing (sacrificial oxidation) the surface of the Si substrate
1, Si oxide film (not shown) of the thickness of about 10 nm is
formed.
[0091] Next, as shown in FIG. 13B, a photoresist mask 130 exposing
a flash memory cell region, an N-HV region and an N-LV region of
the SRAM cell region is formed by a photolithography technique.
Thereafter, by performing ion implantation with the photoresist
mask 130 as a mask, an n-type embedded layer 50 is formed. In
formation of the n-type embedded layer 50, for example, phosphorus
ion is ion-implanted under the condition of the acceleration
energy: 2 MeV and the dose amount: 2.times.10.sup.13 cm.sup.2. The
depth of the embedded layer 50 from the substrate surface is about
2 .mu.m, for example.
[0092] Subsequently, as shown in FIG. 13C, the photoresist mask 130
is removed by, for example, ashing. Next, a photoresist mask 131
exposing the flash memory cell formation region, the N-HV region,
the N-MV region and the N-LV regions and covering the other regions
is formed by a photolithography technique. Thereafter, with the
photoresist mask 131 as a mask, ion implantation is performed, and
thereby, p-wells 51 and 52 are formed. In formation of the p-wells
51, for example, boron ion is ion-implanted under the condition of
the acceleration energy: 400 keV and the dose amount:
1.4.times.10.sup.13 cm.sup.-2. In formation of the p-wells 52, for
example, boron ion is ion-implanted under the condition of the
acceleration energy: 100 keV and the dose amount: 3.times.10.sup.12
cm.sup.-2. As a result, the p-well 52 of higher impurity
concentration is formed in each of the p-wells 51.
[0093] Subsequently, as shown in FIG. 13D, the photoresist mask 131
is removed by, for example, ashing. Next, a photoresist mask 132
exposing the P-HV region, the P-MV region and the P-LV regions and
covering the other regions is formed by a photolithography
technique. Next, with the photoresist mask 132 as a mask, ion
implantation is performed, and thereby, n-wells 53 and 54 are
formed. In formation of the n-wells 53, for example, phosphorus ion
is ion-implanted under the condition of the acceleration energy:
600 keV and the dose amount: 3.times.10.sup.13 cm.sup.-2. In
formation of the n-wells 54, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 240
keV and the dose amount: 9.times.10.sup.12 cm.sup.-2. As a result,
the n-well 54 of higher impurity concentration is formed in each of
the n-wells 53.
[0094] Next, as shown in FIG. 13E, the photoresist mask 132 is
removed by, for example, ashing. Thereafter, a photoresist mask 133
exposing the flash memory region is formed by a photolithography
technique. Thereafter, with the photoresist mask 133 as a mask, ion
implantation is performed, and thereby, a channel doped layer 55 is
formed as a p-type threshold voltage control impurity layer. In
formation of the channel-doped layer 55, for example, boron ion is
ion-implanted under the condition of the acceleration energy: 40
keV and the dose amount: 6.times.10.sup.13 cm.sup.-2.
[0095] Subsequently, as shown in FIG. 13F, the photoresist mask 133
is removed by, for example, ashing. Next, a tunnel oxide film 70 of
the film thickness of about 10 nm is formed on the active regions
by performing thermal oxidation at, for example, the temperature of
900.degree. C. to 1050.degree. C. for 30 minutes.
[0096] Next, as shown in FIG. 13G, after a polysilicon film of the
film thickness of about 90 nm is formed on the tunnel oxide film 70
by, for example, a CVD method, a floating gate 71 is formed in the
flash memory cell region by patterning the polysilicon film by a
photolithography technique and a dry etching technique. Next, an
ONO film 72, which is constituted of a silicon oxide film, a
silicon nitride film and a silicon oxide film which are
sequentially layered, is formed on the entire surface. In formation
of the ONO film 72, the silicon oxide film of the film thickness of
about 5 nm and the silicon nitride film of the film thickness of
about 10 nm are formed by, for example, a CVD method, and
thereafter, the surface of the silicon nitride film is thermally
oxidized at 950.degree. C. for 90 minutes, whereby the silicon
oxide film of the film thickness of about 30 nm is formed.
[0097] Next, as shown in FIG. 13H, a photoresist film 134 exposing
the N-LV regions and covering the other regions is formed by a
photolithography technique. Thereafter, with the photoresist mask
134 as a mask, ion implantation is performed, and thereby, channel
doped layers 56 are formed as the p-type threshold voltage control
impurity layers. In formation of the channel-doped layers 56, for
example, boron ion is ion-implanted under the condition of the
acceleration energy: 15 keV and the dose amount: 8.times.10.sup.12
cm.sup.-2.
[0098] Subsequently, as shown in FIG. 13I, the photoresist mask 134
is removed by, for example, ashing. Next, a photoresist mask 135
exposing the P-LV regions is formed by a photolithography
technique. Next, with the photoresist mask 135 as a mask, ion
implantation is performed, and thereby, channel doped layers 57 are
formed as the n-type threshold voltage control impurity layers. In
formation of the channel-doped layers 57, for example, arsenic ion
is ion-implanted under the condition of the acceleration energy:
150 keV and the dose amount: 3.times.10.sup.12 cm.sup.-2.
[0099] Thereafter, as shown in FIG. 13J, the photoresist mask 135
is removed by, for example, ashing. Subsequently, a photoresist
mask 136 exposing the N-MV region and covering the other regions is
formed by a photolithography technique. Next, with the photoresist
mask 136 as a mask, ion implantation is performed, and thereby, a
channel doped layer 58 is formed as a p-type threshold voltage
control impurity layer. In formation of the channel-doped layer 58,
for example, boron ion is ion-implanted under the condition of the
acceleration energy: 35 keV and the dose amount: 5.times.10.sup.12
cm.sup.-2. As in the first and the second embodiments, the
photoresist mask 136 may be formed into the shape exposing the N-LV
region of the SRAM cell, and the channel doped layer 58 may be also
formed in the N-LV region of the SRAM cell region. In this case,
the channel doped layers 56 and 58 are formed in the N-LV region of
the SRAM cell region, and the state of the N-LV region of the SRAM
cell region is in the same sate as shown in FIG. 5B.
[0100] Next, as shown in FIG. 13K, the photoresist mask 136 is
removed by, for example, ashing. Thereafter, a photoresist mask 137
exposing the P-MV region and covering the other regions is formed
by a photolithography technique. Subsequently, with the photoresist
mask 137 as a mask, ion implantation is performed, and thereby, a
channel doped layer 59 is formed as the n-type threshold voltage
control impurity layer. In formation of the channel-doped layer 59,
for example, arsenic ion is ion-implanted under the condition of
the acceleration energy: 150 keV and the dose amount:
2.times.10.sup.12 cm.sup.-2.
[0101] Next, as shown in FIG. 13L, the photoresist mask 137 is
removed by, for example, ashing. Next, a photoresist mask 138
covering the flash memory cell region and exposing the other
regions is formed by a photolithography technique. Thereafter, by,
for example, dry etching, the ONO film 72 is etched with the
photoresist mask 138 as a mask. As a result, the ONO film 72 of the
other regions than the flash memory cell region is removed.
Further, by wet etching using a hydrofluoric acid aqueous solution,
the tunnel oxide film 70 is etched with the photoresist mask 138 as
a mask. As a result, the tunnel oxide film 70 of the other regions
than the flash memory region is removed.
[0102] Next, as shown in FIG. 13M, the photoresist mask 138 is
removed by, for example, ashing. Next, silicone oxide films each of
the film thickness of about 11 nm are formed on the active regions
as gate insulation films 73 by performing thermal oxidation at, for
example, the temperature of 800.degree. C. Thereafter, by a
photolithography, a photoresist film 139 covering the flash memory
cell region, the N-HV region and the P-HV region and exposing the
other regions is formed. Subsequently, by wet etching using a
hydrofluoric acid aqueous solution, for example, the gate
insulation films 73 are etched with the photoresist mask 139 as a
mask. As a result, the gate insulation films 73 in the N-MV region,
the P-MV region, the N-LV regions and the P-LV regions are
removed.
[0103] Next, as shown in FIG. 13N, the photoresist film 139 is
removed by, for example, ashing. Next, silicone oxide films each of
the film thickness of about 7 nm are formed on the active regions
of the N-MV region, the P-MV region, the N-LV regions and the P-LV
regions as gate insulation films 74 by performing thermal oxidation
at, for example, the temperature of 800.degree. C. The film
thickness of the gate insulation films 73 is increased by this
thermal oxidation. Thereafter, by a photolithography technique, a
photoresist mask 140 covering the flash memory cell region, the
N-HV region, the P-HV region, the N-MV region and the P-MV region
and exposing the N-LV regions and the P-LV regions is formed.
Subsequently, by wet etching using a hydrofluoric acid aqueous
solution, for example, the gate insulation films 74 are etched with
the photoresist mask 140 as a mask. As a result, the gate
insulation films 74 in the N-LV regions and the P-LV regions are
removed.
[0104] Next, as shown in FIG. 130, the photoresist mask 140 is
removed by, for example, ashing. Next, silicone oxide films each of
the film thickness of about 1.8 nm are formed on the active regions
of the N-LV regions and the P-LV regions as gate insulation films
75 by performing thermal oxidation at, for example, the temperature
of 850.degree. C. The film thickness of each of the gate insulation
films 73 and 74 increases by this thermal oxidation.
[0105] Next, as shown in FIG. 13P, a polysilicon film 76 of the
film thickness of about 180 nm, for example, is formed by a CVD
method, and a silicon nitride film 77 of the film thickness of
about 30 nm, for example, is formed on the polysilicon film 76 as a
etching mask also serving as an antireflection film. The silicon
nitride film 77 also exhibits the function of protecting the gate
electrodes in the logic circuit, the I/O circuit and the SRAM cell
when the side surfaces of the gate electrode of the flash memory
cell which will be described later is oxidized. Thereafter, the
silicon nitride film 77, the polysilicon film 76, the ONO film 72
and the floating gate 71 in the flash memory cell region are
patterned by photolithography and dry etching, and thereby, the
gate electrode 90 and the like constituted of the polysilicon film
76 is formed.
[0106] Next, as shown in FIG. 13Q, the side surfaces of the gate
electrode 90 are thermally oxidized by about 10 nm. Thereafter, an
SD diffusion layer 69 which constitutes a source/drain is formed by
ion implantation. Subsequently, the side surfaces of the gate
electrode 90 are thermally oxidized by about 10 nm again. Next,
after a silicon nitride film is deposited by, for example, a
thermal CVD method, the silicon nitride film is etched back, and
thereby side walls (side wall insulation films) 78 constituted of
the silicon nitride film are formed on side wall portions of the
gate electrode 90. Next, the polysilicon film 76 in the N-HV
region, the P-HV region, the N-MV region, the P-MV region, the N-LV
regions and the P-LV regions are patterned by photolithography and
dry etching, and thereby gate electrodes 91 constituted of the
polysilicon film 76 are formed. At this time, the width of each of
the gate electrodes 91 in the N-MV region and the P-MV region is
made larger than the width of each of the gate electrodes 91 in the
N-LV regions and the P-LV regions, and the width of each of the
gate electrodes 91 in the N-HV region and the P-HV region is made
larger than the width of each of the gate electrodes 91 in the N-MV
region and the P-MV region.
[0107] Subsequently, as shown in FIG. 13R, a photoresist mask 141
exposing the N-MV region and covering the other regions is formed
by a photolithography technique. Next, an extension layer 60 for
forming a source/drain of the N-MV region is formed by performing
ion implantation with the photoresist mask 141 as a mask. In
formation of the extension layer 60, for example, phosphorus ion is
ion-implanted under the condition of the acceleration energy: 35
keV and the dose amount: 4.times.10.sup.13 cm.sup.-2.
[0108] Next, as shown in FIG. 13S, the photoresist mask 141 is
removed by, for example, ashing. Thereafter, a photoresist mask 142
exposing the P-MV region and covering the other regions is formed
by a photolithography technique. Subsequently, an extension layer
61 for forming a source/drain of the P-MV region is formed by
performing ion implantation with the photoresist mask 142 as a
mask. In formation of the extension layer 61, for example, boron
fluoride ion is ion-implanted under the condition of the
acceleration energy: 10 keV and the dose amount: 4.times.10.sup.13
cm.sup.-2.
[0109] Next, as shown in FIG. 13T, the photoresist mask 142 is
removed by, for example, ashing. Next, a photoresist mask 143
exposing the N-LV regions and covering the other regions is formed
by a photolithography technique. Thereafter, ion-implantation is
performed with the photoresist mask 143 as a mask, and thereby,
extension layers 62 which constitute the sources/drains of the N-LV
regions are formed. In formation of the extension layers 62, for
example, arsenic ion is ion-implanted under the condition of the
acceleration energy: 3 keV and the dose amount: 1.times.10.sup.15
cm.sup.-2, and thereafter, boron fluoride ion is ion-implanted from
the four directions inclined 28 degrees from the normal line of the
Si substrate 1 under the condition of the acceleration energy: 80
keV and the dose amount: 4.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layers 62 become an extension layers
including pocket layers (not shown).
[0110] Subsequently, as shown in FIG. 13U, the photoresist mask 143
is removed by, for example, ashing. Next, a photoresist mask 144
exposing the P-LV regions and covering the other regions is formed
by a photolithography technique. Next, ion-implantation is
performed with the photoresist mask 144 as a mask, and thereby,
extension layers 63 which constitute sources/drains of the P-LV
regions are formed. In formation of the extension layers 63, for
example, boron ion is ion-implanted under the condition of the
acceleration energy: 0.5 keV and the dose amount: 6.times.10.sup.14
cm.sup.-2, and thereafter, arsenic ion is ion-implanted from the
four directions inclined 28 degrees from the normal line of the Si
substrate 1 under the condition of the acceleration energy: 120 keV
and the dose amount: 5.times.10.sup.12 cm.sup.-2 for each. As a
result, the extension layers 63 also become an extension layers
including pocket layers (not shown).
[0111] Thereafter, as shown in FIG. 13V, the photoresist mask 144
is removed by, for example, ashing. Subsequently, a photoresist
mask 145 exposing the N-HV region and covering the other regions is
formed by a photolithography technique. Next, an extension layer 64
which constitutes a source/drain of the N-HV region is formed by
performing ion implantation with the photoresist mask 145 as a
mask. In formation of the extension layer 64, for example, arsenic
ion is ion-implanted under the condition of the acceleration
energy: 120 keV and the dose amount: 2.times.10.sup.13
cm.sup.-2.
[0112] Next, as shown in FIG. 13W, the photoresist mask 145 is
removed by, for example, ashing. Thereafter, a photoresist mask 146
exposing the P-HV region and covering the other regions is formed
by a photolithography technique. Subsequently, ion-implantation is
performed with the photoresist mask 146 as a mask, and thereby, an
extension layer 65 which constitutes a source/drain of the P-HV
region is formed. In formation of the extension layer 65, for
example, boron fluoride ion is ion-implanted under the condition of
the acceleration energy: 80 keV and the dose amount:
2.times.10.sup.13 cm.sup.-2.
[0113] Next, as shown in FIG. 13X, the photoresist mask 146 is
removed by, for example, ashing. Next, after a silicon oxide film
is deposited by, for example, a thermal CVD method, the silicon
oxide film is etched back, and thereby side walls (side wall
insulation films) 79 constituted of the silicon oxide film are
formed on side wall portions of the gate electrodes 90 and 91.
Thereafter, a photoresist mask 147 exposing the P-HV region, the
P-MV region and the P-LV regions and covering the other regions is
formed. Subsequently, source/drain diffusion layers (SD diffusion
layers) 66 which constitutes the sources/drains of the P-HV region,
the P-MV region and the P-LV regions are formed by performing ion
implantation with the photoresist mask 147 as a mask. In formation
of the SD diffusion layers 66, for example, boron ion is ion
implanted under the condition of the acceleration energy: 5 keV and
the dose amount: 4.times.10.sup.15 cm.sup.-2. The conductivity type
of the gate electrodes 91 in the P-HV region, the P-MV region and
the P-LV regions become p-type.
[0114] Thereafter, as shown in FIG. 13Y, the photoresist mask 147
is removed by, for example, ashing. Next, a photoresist mask 148
exposing the flash memory cell region, the N-HV region, the N-MV
region and the N-LV regions and covering the other regions is
formed by a photolithography technique. Next, ion implantation is
performed with the photoresist mask 148 as a mask, and thereby SD
diffusion layers 67 which constitute sources/drains of the flash
memory cell region, the N-HV region, the N-MV region and the N-LV
regions are formed. In formation of the SD diffusion layers 67, for
example, phosphorus ion is ion-implanted under the condition of the
acceleration energy: 10 keV and the dose amount: 6.times.10.sup.15
cm.sup.-2. By this ion implantation, the conductivity type of the
gate electrode 90 of the flash memory cell and the gate electrodes
91 of the N-HV region, the N-MV region and the N-LV regions becomes
n-type.
[0115] Thereafter, as shown in FIG. 13Z, the photoresist mask 148
is removed by, for example, ashing. Subsequently, silicide layers
68 are formed on the gate electrodes 90 and 91, and the SD
diffusion layers 66 and 67 by a known salicide process.
Subsequently, an interlayer insulation film 80 is formed on the
entire surface, and thereafter contact holes are formed. After
contact plugs 81 are formed in the contact holes, wirings 82 are
formed on the interlayer insulation film 80. In this manner, the
steps up to the first metal wiring layer are completed. As the
interlayer insulation film 80, an Si oxide film of the thickness of
about 600 nm is formed by, for example, a HDP method.
[0116] Thereafter, a further upper wiring layer and interlayer
insulation film and the like are formed, and the semiconductor
device on which the logic circuit element loaded with the SRAM and
the flash memory are mixedly mounted is completed.
[0117] According to the above third embodiment, the same effect as
in the second embodiment is also obtained. Even if the SRAM cell is
formed in parallel with the formation of the non-volatile memory
(flash memory) cell, it is possible to avoid increase in the number
of process steps and increase in the cost following this.
[0118] According to the first aspect of the present invention, the
impurity concentration of the channel of the transistor for the
first memory is higher than those of the transistor for the first
peripheral circuit and the transistor for the second peripheral
circuit, thus making it possible to obtain high threshold voltage
and ensure a wide operation margin. The introduction of the
impurity into the channel of the transistor for the first memory
can be performed in parallel with the introduction of the impurity
into the channels of the transistor for the first peripheral
circuit and the transistor for the second peripheral circuit, and
therefore the increase in the process steps and the increase in
cost can be avoided.
[0119] According to the second aspect of the present invention, the
embedded well of the second conductivity type is formed directly
under the first well, and therefore when .alpha.-ray is incident on
the transistor for the first memory, a change in the depletion
layer is suppressed, thus making it possible to suppress a soft
error.
[0120] The present embodiments are to be considered in all respects
as illustrative and no restrictive, and all changes which come
within the meaning and range of equivalency of the claims are
therefore intended to be embraced therein. The invention may be
embodied in other specific forms without departing from the spirit
or essential characteristics thereof.
* * * * *