U.S. patent application number 12/247019 was filed with the patent office on 2009-08-20 for direct memory access system and method using the same.
Invention is credited to Kuo-Cheng LU.
Application Number | 20090210577 12/247019 |
Document ID | / |
Family ID | 40956149 |
Filed Date | 2009-08-20 |
United States Patent
Application |
20090210577 |
Kind Code |
A1 |
LU; Kuo-Cheng |
August 20, 2009 |
DIRECT MEMORY ACCESS SYSTEM AND METHOD USING THE SAME
Abstract
The invention discloses a DMA system capable of being adapted to
various interfaces. The DMA system includes the following
advantages: 1) the software porting effort can be reduced when
different interfaces are integrated into a SoC; 2) a flexible DMA
that could provide protocol transparency and could be ported into
different interfaces easily; 3) a scalable DMA that can support
unlimited TX/RX scattering/gathering data segments; 4) a reusable
DMA that provides user defined TX information (or RX information)
and TX message (or RX message) field; and 5) a high performance DMA
that support unaligned segment data pointers and unlimited
scattering/gathering data segments, so as to reduce extra memory
copies by CPU.
Inventors: |
LU; Kuo-Cheng; (Hsinchu
City, TW) |
Correspondence
Address: |
Muncy, Geissler, Olds & Lowe, PLLC
P.O. BOX 1364
FAIRFAX
VA
22038-1364
US
|
Family ID: |
40956149 |
Appl. No.: |
12/247019 |
Filed: |
October 7, 2008 |
Current U.S.
Class: |
710/22 |
Current CPC
Class: |
G06F 13/28 20130101 |
Class at
Publication: |
710/22 |
International
Class: |
G06F 13/28 20060101
G06F013/28 |
Foreign Application Data
Date |
Code |
Application Number |
Feb 20, 2008 |
TW |
097105859 |
Claims
1. A direct memory access (DMA) system, comprising: a DMA
transmitter for transmitting a TX packet according to a TX
descriptor and appending a TX information to the head of the TX
packet based on the TX descriptor; and a DMA receiver for receiving
an RX packet according to an RX descriptor and appending an RX
information to the tail of the RX packet based on the RX
descriptor.
2. The DMA system of claim 1, wherein the TX descriptor comprises
at least one pointer, at least one length of the TX packet, and the
TX information; wherein the RX descriptor comprises at least one
pointer, at least one length of RX packet, and the RX
information.
3. The DMA system of claim 1, wherein the DMA transmitter
selectively appends a TX message between the TX packet and the TX
information, and the DMA receiver selectively appends an RX message
to the head of the RX packet.
4. The DMA system of claim 1, further comprising at least two first
hardware indexes and at least two second hardware indexes, wherein
the first hardware indexes are used for indicating an ownership of
the TX descriptor, and the second hardware indexes are used for
indicating an ownership of the RX descriptor.
5. The DMA system of claim 1, wherein the TX descriptor is a TX
descriptor ring, and the RX descriptor is an RX descriptor
ring.
6. The DMA system of claim 5, further comprising a scheduler for
arranging the sequence of accessing the TX descriptor ring.
7. The DMA system of claim 1, wherein the DMA system communicating
with a memory via a system bus.
8. A method for transmitting/receiving a packet in a direct memory
access (DMA) system, comprising the steps of: transmitting a TX
packet according to a TX descriptor and appending a TX information
to the head of the TX packet based on the TX descriptor; and
receiving an RX packet according to an RX descriptor and appending
an RX information to the tail of the RX packet based on the RX
descriptor.
9. The method of claim 8, wherein the TX descriptor comprises at
least one pointer, at least one length of the TX packet, and the TX
information; wherein the RX descriptor comprises at least one
pointer, at least one length of the RX packet, and the RX
information.
10. The method of claim 8, further comprising the steps of:
selectively appending a TX message between the TX packet and the TX
information; and selectively appending an RX message to the head of
the RX packet.
11. The method of claim 8, further comprising the steps of:
indicating an ownership of the TX descriptor with at least two
first hardware indexes; and indicating an ownership of the RX
descriptor with at least two second hardware indexes.
12. The method of claim 8, wherein the TX descriptor is a TX
descriptor ring, and the RX descriptor is an RX descriptor
ring.
13. The method of claim 12, further comprising the step of:
arranging the sequence of accessing the TX descriptor ring with a
scheduler.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The invention relates to a direct memory access (DMA) system
and, more particularly, to a unified DMA system adapted to various
networking protocol such as WLAN, Ethernet, WiMAX, UWB, USB, and so
on.
[0003] 2. Description of the Prior Art
[0004] For any kind of high-performance network interface cards
(NICs), a dedicated hardware for transferring TX/RX packets is
widely used to improve the performance. Generally, this dedicated
hardware utilizes the technology called direct memory access (DMA),
which allows direct data transfer between certain interfaces and
memories in a computer system without the intervention of central
processing units (CPU).
[0005] Please refer to FIG. 1, which illustrates the operation flow
of a conventional DMA device 10. When a CPU 12 plans to send a TX
packet 14, it stores a buffer address 160 of the packet and some
related packet information 162 into a TX descriptor 16 and then
resets an associated owner bit 164. Subsequently, CPU 12 would
inform DMA device 10 to move TX packet 14 from memory 18 to
interface 20. After transmitting the TX packet 14, DMA device 10
sets owner bit 164 as 1 and inform CPU 12 that the transmission of
TX packet 14 is finished.
[0006] When receiving an RX packet 22, CPU 12 allocates an
available buffer space in memory 18 for the packet, stores a buffer
address 240 into an RX descriptor 24, and then resets an associated
owner bit 244. When the RX packet 22 is transferred from interface
20, DMA device 10 first checks the owner bit 244 of RX descriptor
24. Then, DMA device 10 transfers RX packet 22 from interface 20 to
memory 18. After RX packet 22 is moved to memory 18, DMA device 10
writes a packet information 242 into the RX descriptor 24 and sets
owner bit 244 as 1 and then informs CPU 12 of the completeness of
receiving RX packet 22.
[0007] In order to improve the performance and reduce the
requirement of First-In-First-Out (FIFO) memory, most conventional
DMA devices support multiple TX/RX descriptors by, for instance,
arranging descriptors as descriptor chains or descriptor rings. A
typical TX descriptor chain is shown in FIG. 2, and a typical TX
descriptor ring is shown in FIG. 3.
[0008] Although most DMA devices have similar operation rules, the
designs of the DMA devices are not exactly the same. In particular,
DMA devices will be different when the attached network media
(e.g., Ethernet, WLAN, ADSL, WiMAX, and so on) changes. Therefore,
when more and more interfaces are integrated into a system on chip
(SoC), non-unified DMA descriptor architectures and semantic
languages would increase hardware verification effort and software
porting effort significantly. Moreover, different DMA engines for
different interfaces are hard to maintain from the perspective of
ASIC design.
[0009] Therefore, the scope of the invention is to provide a
unified DMA system to solve the aforesaid problems.
SUMMARY OF THE INVENTION
[0010] An object of the present invention is to provide a unified
DMA system which allows different interfaces to share the same DMA
engine.
[0011] According to an embodiment of the present invention, the DMA
system is used for transmitting/receiving packets between an
interface and a memory. The DMA system includes a DMA transmitter
and a DMA receiver. The DMA transmitter transmits a TX packet based
on a TX descriptor and appends a TX information to the head of the
TX packet based on the TX descriptor. On the other hand, the DMA
receiver receives an RX packet based on an RX descriptor and
appends an RX information to the tail of the RX packet. In this
embodiment, the TX descriptor and the RX descriptor can be
selectively embedded the interface or the memory.
[0012] The TX information is used for informing the interface about
the TX path, so that the interface can perform the packet
processing procedure. When the information to be transmitted is too
large to be completely filled into the TX information, the DMA
transmitter of the invention can selectively append a TX message
between the TX packet and the TX information.
[0013] The RX information is used for storing the receiving state
of packets. If the RX information is too small for some
applications, the DMA receiver can selectively append an RX message
to the head of the RX packet, so as to transmit more necessary
receiving statuses.
[0014] From the perspective of DMA, since the TX message (or RX
message) and TX packet (or RX packet) are transmitted as a TX
payload (or an RX payload), the DMA device does not know the
semantic program and data length of the TX message (or RX message),
and designers can decide to fill what information into the TX
message (or RX message). Thereby, the DMA system of the invention
can be formatted based on different interfaces and adapted to
various networking protocols such as WLAN, Ethernet, WiMAX, UWB,
USB, and so on.
[0015] The advantage and spirit of the invention may be understood
by the following recitations together with the appended
drawings.
BRIEF DESCRIPTION OF THE APPENDED DRAWINGS
[0016] FIG. 1 illustrates the operation flow of a DMA device 10 in
the prior arts.
[0017] FIG. 2 is a schematic diagram of a typical TX descriptor
chain.
[0018] FIG. 3 is a schematic diagram of a typical TX descriptor
ring.
[0019] FIG. 4(A) is a functional diagram illustrating a DMA system
in an embodiment according to the invention.
[0020] FIG. 4(B) is a functional diagram illustrating a DMA system
in another embodiment according to the invention.
[0021] FIG. 5(A) illustrates the format of a TX descriptor in an
embodiment according to the invention.
[0022] FIG. 5(B) illustrates the format of an RX descriptor in an
embodiment according to the invention.
[0023] FIG. 6 is illustrating the relationship between data
segments of a packet and the TX descriptor.
[0024] FIG. 7(A) and FIG. 7(B) respectively illustrate the
ownership of the TX descriptor indicated by two hardware indexes
according to an embodiment of the present invention.
[0025] FIG. 8(A) and FIG. 8(B) respectively illustrate the
ownership of the RX descriptor indicated by two hardware indexes
according to an embodiment of the present invention.
[0026] FIG. 9 is a schematic diagram illustrating a carried TX
message.
DETAILED DESCRIPTION OF THE INVENTION
[0027] Please refer to FIG. 4(A), which illustrates a functional
block diagram of a DMA system 40 in an embodiment according to the
invention. As shown in FIG. 4(A), a DMA device 42 communicates with
a memory 46 and a CPU 48 via a system bus 44. DMA device 42
includes a DMA transmitter 420 and a DMA receiver 422. An interface
50 is connected to DMA device 42 via a FIFO memory 52. FIFO memory
52 includes a FIFO transmitter 520 and a FIFO receiver 522. A
scheduler 54 is connected to DMA device 42 for arranging the
sequence of accessing TX descriptor rings.
[0028] As shown in FIG. 4(A), when transmitting a TX packet 560,
DMA transmitter 420 appends a TX information 562 to the head of TX
packet 560 based on a TX descriptor (described later). TX
information 562 is used for informing interface 50 of the
transmitting path, so that interface 50 can perform a packet
processing procedure. Typical TX information 562 can include
TCP/UDP/IP checksum offload, cyclic redundancy check (CRC)
calculation, packet destination port, and so on. TX information 562
is a part of the TX descriptor and is appended to the TX descriptor
when TX packet 560 is transferred from memory 46 to interface 50 by
DMA transmitter 420.
[0029] Similarly, as shown in FIG. 4(A), when DMA receiver 422
receives an RX packet 580, DMA receiver 422 appends an RX
information 582 to the tail of RX packet 580 based on an RX
descriptor (described later). RX information 582 is used for
storing the receiving status of packets such as CRC check result,
packet type, and so on.
[0030] Please refer to FIG. 4(B), which illustrates a functional
block diagram of a DMA system 40' in another embodiment according
to the invention. When the information to be transmitted is too
large to be completely filled into TX information 562, DMA
transmitter 420 can selectively append an extended TX information
(i.e. a TX message 564 shown in FIG. 4(B)) between TX packet 560
and TX information 562. In the same manner, if RX information 582
is too small for certain applications, DMA receiver 422 can also
selectively append a RX message 584 to the head of the RX packet
580 for carrying more necessary receiving statuses such as
description keys, received signal strength (RSS) in WLAN
applications, and so on.
[0031] From the perspective of DMA device 42, DMA transmitter 420
treats and processes both TX message 564 and TX packet 560 as TX
payloads, and DMA receiver 422 treats and processes both RX message
584 and RX packet 580 as RX payloads. In other words, DMA device 42
does not have to know the semantic language and data length of TX
message 564 or RX message 584. Thereby, DMA device 42 of the
invention can be formatted based on various interface devices and
adapted to various networking protocols such as WLAN, Ethernet,
WIMAX, UWB, USB, and so on.
[0032] Please refer to FIG. 5(A) and FIG. 5(B). FIG. 5(A) shows the
format of a TX descriptor 60 in an embodiment according to the
invention. FIG. 5(B) is shows the format of an RX descriptor 62 in
an embodiment according to the invention. DMA system 40 of the
invention includes TX descriptor 60 and RX descriptor 62. In this
embodiment, both TX descriptor 60 and RX descriptor 62 can be
selectively embedded in interface 50 or memory 46.
[0033] As shown in FIG. 5(A), TX descriptor 60 includes two
pointers (SDP0 and SDP1) for indicating the memory address of TX
packet 560. The data length of TX packet 560 is stored in SDL0 and
SDL1 of TX descriptor 60. In addition, the bit LS is used for
indicating which data segment is the last data segment of TX packet
560. For example, if the bit LS is set as 1, the data segment
(pointed by SDP0 or SDP1) is the last one of TX packet 560. As
shown in FIG. 5(A), the data segment pointed by SDP1 is the last
one of TX packet 560.
[0034] In order to support the scattered/gathered data segments, TX
packet 560 can be divided into a plurality of data segments and
respectively stored into different memory sections. These data
segments of TX packet 560 are associated by one or more TX
descriptors 60. Please refer to FIG. 6, which illustrates the
relationship between the data segments of the packet and the TX
descriptor. A packet P1 is divided into three data segments: DS11,
DS12, and DS13. DS11 and DS12 are related to the descriptor TXD1,
and DS13 is related to the descriptor TXD2. A packet P2 includes
only one data segment DS21 and relative to the descriptor TXD3. A
packet P3 is divided into two data segments: DS31 and DS32, which
are both relative to the descriptor TXD4. Because the data segments
DS13, DS21, and DS32 are respectively the last data segments of P1,
P2, and P3, their bit LS are all set as 1.
[0035] In addition, before using TX descriptor 60, DMA transmitter
420 will first check a DMA Done (DDONE) bit (as shown in FIG.
5(A)). If the DDONE bit is 0, DMA transmitter 420 has an ownership
to use and transfers the data segments pointed by SDP0 and SDP1.
After finishing transferring the data, DMA transmitter 420 returns
the ownership of TX descriptor 60 to the CPU by writing 1 to the
DDONE bit. At last, TX information 562 will be appended to the head
of TX packet 560 by DMA transmitter 420 before the packet is sent
to interface 50.
[0036] In most networking applications, a plurality of TX
descriptor rings are used to support the quality of service (QoS).
Scheduler 54 in FIG. 4(A) is used to decide which TX packet is
going to be transferred first. If a user wants to guarantee two or
more packets in the same TX descriptor ring can be transferred
consecutively, the user can inform DMA transmitter 420 by setting a
BURST bit (as shown in FIG. 5(A)). Besides, because TX information
562 is transferred by DMA transmitter 420, the user can define TX
information 562 according to actual applications.
[0037] On the other hands, as shown in FIG. 5(B), RX descriptor 62
includes two pointers (SDP0 and SDP1) for indicating the memory
address of RX packet 580. And the data length of RX packet 580 is
stored in SDL0 and SDL1 of RX descriptor 62. In addition, the bit
LS is used for indicating which segment if the last data segment of
RX packet 580. For example, if the bit LS is set as 1, the
corresponding data segment (pointed by SDP0 or SDP1) is the last
one of RX packet 580. As shown in FIG. 5(B), the data segment
pointed by SDP1 is the last one of RX packet 580.
[0038] In this embodiment, the operation rules of RX descriptor 62
are similar to those of TX descriptor 60. The major difference is
that unused data segment buffers are prepared and associated with
the pointers (SDP0 and SDP1) and the data lengths (SDL0 and SDL1)
of RX descriptors 62. When DMA receiver 422 wants to receive RX
packet 580, it first checks if the data segments (SDL0 and SDL1)
are large enough for storing RX packet 580. If the space is not
enough, DMA receiver 422 uses other pointers to store the residual
parts of RX packet 580. After the packet is completely transferred
to memory 46, DMA receiver 422 will update the data length to
indicate the length of the last data segment and set the associated
LS bit as 1.
[0039] In the present invention, in addition to utilizing the DDONE
bit to manage the ownership of the TX descriptor, DMA system 40 can
further provide two hardware indexes: a CTX_IDX and a DTX_IDX for
indicating the ownership of the TX descriptor. Please refer to FIG.
7(A) and FIG. 7(B), which illustrate the operation rule of the two
indexes. As shown in FIG. 7(A), when the TX descriptors (TXDn,
n=0.about.7) pointed by the DTX_IDX and the CTX_IDX are different,
DMA transmitter 420 processes the TX descriptor pointed by the
DTX_IDX. As shown in FIG. 7(B), when the TX descriptors pointed by
the DTX_IDX and the CTX_IDX are the same, DMA transmitter 420 stops
the processing procedure.
[0040] In the present invention, in addition to utilizing the DDONE
bit to manage the ownership of the RX descriptor, DMA system 40 can
further provide two hardware indexes: a CRX_IDX and a DRX_IDX for
indicating the ownership of the RX descriptor. Please refer to FIG.
8(A) and FIG. 8(B), which illustrate the operation rule of the two
indexes. The operation rule of the CRX_IDX and the DRX_IDX is
similar to that of the CTX_IDX and the DTX_IDX, so it is not
described again.
[0041] One benefit of this DMA system 40 of the invention is that
users are allowed to define their own incormation/messages to
communicate with interface 50. There are two ways for carrying
these incormation/messages. If the message is short, it can be
carried by TX information 562 or RX information 582. If the message
is too large to be filled into TX information 562 or RX information
582, TX message 564 or RX message 584 can be utilized. From the
perspective of DMA, the DMA device is not aware of how much message
is carried in TX/RX payloads. In other words, the DMA device will
treat the carried messages as a portion of a packet. Please refer
to FIG. 9, which illustrates a schematic diagram of a carried TX
message. The TX message can be connected to SDP0 as the first data
segment of a packet, so that no extra memory space is required.
[0042] Compared to the prior arts, the DMA system of the invention
has the following advantages:
[0043] can be adapted to various interfaces;
[0044] can reduce the effort of porting software when various
interfaces are integrated into a SoC;
[0045] can be ported into different interfaces easily since a
transparent networking protocol is provided;
[0046] can support unlimited scattered/gathered of the TX/RX
data;
[0047] users can define the TX/RX information and the TX/RX message
by themselves; and
[0048] providing a high performance DMA that supports unaligned
data pointers and unlimited scattered/gathered data segments, so as
to reduce extra memory space.
[0049] With the example and explanations above, the features and
spirits of the invention will be hopefully well described. Those
skilled in the art will readily observe that numerous modifications
and alterations of the device may be made while retaining the
teaching of the invention. Accordingly, the above disclosure should
be construed as limited only by the metes and bounds of the
appended claims.
* * * * *