U.S. patent application number 12/027570 was filed with the patent office on 2009-08-13 for hybrid memory system and spin-buffer journaling in a gaming machine.
This patent application is currently assigned to IGT. Invention is credited to Kenneth Walter Peek.
Application Number | 20090203430 12/027570 |
Document ID | / |
Family ID | 40939364 |
Filed Date | 2009-08-13 |
United States Patent
Application |
20090203430 |
Kind Code |
A1 |
Peek; Kenneth Walter |
August 13, 2009 |
HYBRID MEMORY SYSTEM AND SPIN-BUFFER JOURNALING IN A GAMING
MACHINE
Abstract
A gaming machine is comprised of a processor, an interface, and
a hybrid non-volatile memory component having a byte-addressable
non-volatile memory sub-component and a block-addressable
non-volatile memory sub-component. The machine is capable of
storing critical gaming data or data that is required to be stored
pursuant to gaming regulations in an efficient, reliable, and
cost-effective manner. The byte-addressable sub-component (the
"expensive" memory) has at least three buffers for temporarily
storing critical game data and the block-addressable sub-component
(the "lower cost" memory) has at least one block for storing game
data, wherein critical gaming data is transferred from the
byte-addressable sub-component to the block-addressable
sub-component, where it is permanently stored. The
block-addressable memory may be flash memory. A confirmation is
sent from the block-addressable sub-component to the
byte-addressable sub-component when the critical gaming data is
permanently stored. The critical gaming data is deleted from the
byte-addressable sub-component when the confirmation is received.
In one embodiment, the byte-addressable sub-component is a memory
that continues to store data during a power loss, in contrast to
the block-addressable memory, which may lose data during a write
operation if a disruption occurs.
Inventors: |
Peek; Kenneth Walter; (Las
Vegas, NV) |
Correspondence
Address: |
Weaver Austin Villeneuve & Sampson LLP - IGT;Attn: IGT
P.O. Box 70250
Oakland
CA
94612-0250
US
|
Assignee: |
IGT
Reno
NV
|
Family ID: |
40939364 |
Appl. No.: |
12/027570 |
Filed: |
February 7, 2008 |
Current U.S.
Class: |
463/25 |
Current CPC
Class: |
G07F 17/3223 20130101;
G07F 17/32 20130101 |
Class at
Publication: |
463/25 |
International
Class: |
A63F 9/24 20060101
A63F009/24 |
Claims
1. A gaming machine comprising: at least one processor; at least
one interface; a hybrid non-volatile memory component having a
byte-addressable non-volatile memory sub-component and a
block-addressable non-volatile memory sub-component, the
byte-addressable sub-component having at least three buffers and
the block-addressable sub-component having at least one block,
wherein critical gaming data is transferred from the
byte-addressable sub-component to the block-addressable
sub-component, where it is permanently stored; and wherein a
confirmation is sent from the block-addressable sub-component to
the byte-addressable sub-component when the critical gaming data is
permanently stored; and wherein the critical gaming data is deleted
from the byte-addressable sub-component when the confirmation is
received.
2. A gaming machine as recited in claim 1 further comprising: a
hybrid non-volatile memory manager for controlling operations of
the hybrid non-volatile memory component.
3. A gaming machine as recited in claim 1 wherein the
block-addressable sub-component is a flash memory.
4. A gaming machine as recited in claim 1 wherein the size of a
buffer in the byte-addressable sub-component depends on the size of
a block in block-addressable sub-component.
5. A gaming machine as recited in claim 1 wherein critical gaming
data is selected from the group consisting of game history
information, security information, accounting information, player
tracking information, wide area progressive information, game state
information, game usage information, game transactional
information, game meter information, bonus of game information, and
player input information.
6. A gaming machine as recited in claim 1 wherein the hybrid
non-volatile memory manager is an FPGA.
7. A gaming machine as recited in claim 6 wherein the hybrid
non-volatile memory component and the memory manager are on the
same chip in the gaming machine.
8. A gaming machine as recited in claim 7 wherein the chip is on a
main processing board of the gaming machine.
9. A gaming machine as recited in claim 1 wherein the critical
gaming data is transmitted to the hybrid non-volatile memory
component from the at least one processor.
10. A method of storing gaming data in a hybrid memory component in
a gaming machine, the gaming data required to be stored by a gaming
operator pursuant to gaming regulations, the method comprising:
receiving gaming data at the hybrid memory component from one or
more components in the gaming machine; determining if a
byte-addressable non-volatile memory buffer in the hybrid memory
component is at maximum storage capacity with gaming data; if it is
at maximum storage capacity, writing the gaming data from the
buffer to a block in the block-addressable non-volatile memory,
wherein the gaming data continues to be stored in the buffer during
the writing; if it is not at maximum storage capacity, continuing
to receive gaming data from the one or more components; if the
writing operation is complete, at the block-addressable
non-volatile memory, checking if the gaming data has been stored
persistently; is if the gaming data has been stored persistently in
the block-addressable non-volatile memory, sending a confirmation
from the block-addressable non-volatile memory to the
byte-addressable non-volatile memory buffer; and deleting the
gaming data from the buffer when the confirmation is received,
thereby freeing the buffer to receive new data, such that gaming
data is not lost if there is a disruption during the writing
operation.
11. A method as recited in claim 10 further comprising checking the
contents of the buffer to determine if the buffer is at maximum
storage capacity.
12. A method as recited in claim 10 further comprising sending the
confirmation to a non-volatile memory manager, wherein the
non-volatile memory manager is a component in the hybrid memory
component of the gaming machine.
13. A method as recited in claim 10 further comprising: reading
byte-addressable non-volatile memory administrative data to
determine a next available buffer for receiving gaming data; and
changing a state of the buffer to indicate it is receiving gaming
data.
14. A method as recited in claim 10 further comprising: determining
if the writing operation of gaming data from the buffer to the
block is complete; and if complete, changing a state of the buffer
to indicate that it is at maximum storage capacity.
15. A method as recited in claim 10 further comprising: determining
if the writing operation was in progress between a byte-addressable
buffer and the block in block-addressable non-volatile memory
during a disruption in the gaming machine operations; if gaming
data was being written to the block during the disruption, erasing
the data from the block upon resumption of gaming machine
operations; and re-writing the gaming data from the
byte-addressable buffer to the block.
16. A method as recited in claim 15 further comprising: reading
administrative data in the byte-addressable non-volatile memory to
determine which sectors in the block should be erased.
17. A method as recited in claim 15 further comprising checking a
state variable of the block-addressable buffer.
18. A method as recited in claim 10 wherein the gaming data is
selected from the group consisting of game history information,
security information, accounting information, player tracking
information, wide area progressive information and game state
information, game usage information, game transactional
information, game meter information, bonus of game information, and
player input information.
19. A gaming device capable of storing required gaming data
pursuant to wager gaming regulations comprising: a master gaming
controller; a hybrid non-volatile memory component having a
byte-addressable memory, a block-addressable memory, and an FPGA;
and a memory storing computer instructions for: receiving the
required gaming data at the hybrid memory component from the master
gaming controller; determining if a byte-addressable non-volatile
memory buffer in the hybrid memory component is at maximum storage
capacity with required gaming data; if it is at maximum storage
capacity, writing the required gaming data from the buffer to a
block in the block-addressable memory, wherein the required gaming
data continues to be stored in the buffer during the writing; if it
is not at maximum storage capacity, continuing to receive required
gaming data from the master gaming controller; if the writing
operation is complete, at the block-addressable memory, checking if
the required gaming data has been journaled persistently; if the
required gaming data has been journaled persistently in the
block-addressable memory, sending a confirmation from the
block-addressable memory to the byte-addressable memory buffer; and
deleting the required gaming data from the buffer when the
confirmation is received, thereby freeing the buffer to receive new
required gaming data, such that required gaming data being written
is not lost if there is a disruption in the gaming device
operations during the writing operation, and wherein the gaming
device is able to store required gaming data pursuant to gaming
regulations using a combination of lower-cost non-volatile memory
for long-term persistent journaling and higher-cost memory for
intermediate buffering of the required gaming data.
20. A gaming device as recited in claim 19 wherein the memory
further comprises computer code for: determining if the writing
operation of required gaming data from the buffer to the block is
complete; and if complete, changing a state of the buffer to
indicate that it is at maximum storage capacity.
21. A gaming device as recited in claim 19 wherein the memory
further comprises computer code for: determining if the writing
operation was in progress between a byte-addressable buffer and the
block in block-addressable memory during a disruption in the gaming
machine operations; if the required gaming data was being written
to the block during the disruption, erasing the required data from
the block upon resumption of gaming machine operations; and
re-writing the required gaming data from the byte-addressable
buffer to the block.
22. A gaming device as recited in claim 19 wherein the required
gaming data is selected from the group consisting of game history
information, security information, accounting information, player
tracking information, wide area progressive information, game state
information, game usage information, game transactional
information, game meter information, bonus of game information, and
player input information.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to wager gaming machines and
memory management. More specifically, it relates to managing gaming
machine data using two types of memory and a spin buffering
methodology.
[0003] 2. Description of the Related Art
[0004] In a gaming machine network, slow-speed serial lines have
kept the amount of data that could be transmitted in the network
relatively small. Gaming control board regulations and casino
policies were limited by what the technology could provide. For
example, increments in meters and a few bytes indicating an action,
such as a wheel spin, was all that was typically sent over the
network. This required a few bytes of data and was suitable for
transmission over serial lines.
[0005] When Ethernet was introduced, the speed with which data
could be transmitted increased by orders of magnitude. For example,
programmers could now wrap data in XML and use other similar
techniques. With the introduction of Ethernet, much larger amounts
of data could be transmitted and at much faster speeds. Gaming
regulatory bodies then required that more data be stored. For
example, with Ethernet, 512 byte packets for each event on a gaming
machine could now be sent. However, with these new requirements and
speed came the significantly increased need for extra storage
capacity on a gaming machine. As is known in the art, a gaming
machine logs data on the machine and stores the data, for example,
in a CMOS nvRAM on the machine. This type of battery-backed
non-volatile memory is expensive and now reaches capacity very
quickly with the new requirements for storing data for each event,
which may be any type of gaming transaction or any synchronous or
asynchronous gaming machine event. Gaming machines use nvRAM
primarily because of its write speed. Hard drives are typically too
slow.
[0006] The capacity of non-volatile memory on older gaming machines
was, for example, in the 128k range. But what is now needed is more
in the range of 16 MB of such memory. The newest AVP i960 gaming
machine from IGT, Inc. of Reno, Nev., does not have enough nvRAM
now that some gaming control boards are requiring that complete
pictures of all the meters and other data be stored by the gaming
operator, even if such storage may be on the machine or at another
memory source, for example, a server in the gaming network. In
another example, in a server-based gaming environment using new
protocols that take advantage of Ethernet (e.g., G2S, developed in
part by IGT), storage of large amounts of data is needed for game
and system log data.
SUMMARY OF THE INVENTION
[0007] In one embodiment, a gaming machine is comprised of a
processor, an interface, and a hybrid non-volatile memory component
having a byte-addressable non-volatile memory sub-component and a
block-addressable non-volatile memory sub-component. The
byte-addressable sub-component has at least three buffers for
temporarily storing critical game data and the block-addressable
sub-component has at least one block for storing game data, wherein
critical gaming data is transferred from the byte-addressable
sub-component to the block-addressable sub-component, where it is
permanently stored. A confirmation is sent from the
block-addressable sub-component to the byte-addressable
sub-component when the critical gaming data is permanently stored.
The critical gaming data is deleted from the byte-addressable
sub-component when the confirmation is received. In one embodiment,
the byte-addressable sub-component is a memory that continues to
store data during a power is loss, in contrast to the
block-addressable memory, such as flash memory, which may lose data
during a write operation if a disruption occurs.
[0008] In another embodiment, a method of storing gaming data in a
hybrid memory component in a gaming machine is described, where the
gaming data is required to be stored is dictated by relevant gaming
regulations. The gaming data is received at the hybrid memory
component from one or more components in the gaming machine. It is
then determined if a byte-addressable non-volatile memory buffer in
the hybrid memory component is at maximum storage capacity with the
required gaming data. If the buffer is at maximum storage capacity,
the gaming data from the buffer is written to a block in the
block-addressable non-volatile memory, while the gaming data
continues to be stored in the buffer during the writing. If it is
not at maximum storage capacity, the buffer continues to receive
gaming data from the one or more components. If the writing
operation is complete, at the block-addressable non-volatile
memory, it is checked if the gaming data has been stored
persistently. If the gaming data has been stored persistently in
the block-addressable non-volatile memory, a confirmation is sent
from the block-addressable non-volatile memory to the
byte-addressable non-volatile memory buffer. The gaming data is
deleted from the buffer when the confirmation is received, thereby
freeing the buffer to receive new data, such that gaming data is
not lost if there is a disruption during the writing operation.
[0009] In one embodiment, a gaming device capable of storing
required gaming data pursuant to wager gaming regulations is
described. The device includes a master gaming controller, a hybrid
non-volatile memory component having a byte-addressable memory, a
block-addressable memory, an FPGA, and a memory. The memory stores
computer instructions for performing various operations on the
gaming device. In one embodiment, the required gaming data is
received at the hybrid memory component from the master gaming
controller. It is then determined if a byte-addressable
non-volatile memory buffer in the hybrid memory component is at
maximum storage capacity with required gaming data. If it is at
maximum storage capacity, the required gaming data is written from
the buffer to a block in the block-addressable memory, wherein the
required gaming data continues to be stored in the buffer during
the writing. If it is not at maximum storage capacity, the buffer
continues to receive required gaming data from the master gaming
controller. If the writing operation is complete, at the
block-addressable memory, it is checked if the required gaming data
has been journaled or stored persistently. If the required gaming
data has been journaled persistently in the block-addressable
memory, a confirmation is sent from the block-addressable memory to
the byte-addressable memory buffer. The required gaming data is
deleted from the buffer when the confirmation is received. In this
manner the buffer is free to receive new required gaming data, such
that required gaming data being written is not lost if there is a
disruption in the gaming device operations during the writing
operation. The gaming device is able to store required gaming data
pursuant to gaming regulations using a combination of lower-cost
non-volatile memory for long-term persistent journaling and
higher-cost memory for intermediate buffering of the required
gaming data.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] References are made to the accompanying drawings, which form
a part of the description and in which are shown, by way of
illustration, particular embodiments:
[0011] FIG. 1 is an exemplary gaming machine illustrated in
perspective view;
[0012] FIG. 2 is a partial exemplary architecture for an electronic
gaming machine in accordance with one embodiment;
[0013] FIG. 3 is a simplified block diagram of an exemplary gaming
machine in accordance with a specific embodiment of the present
invention;
[0014] FIG. 4 is a block diagram showing components of a hybrid
memory component that may be used in a gaming machine or in other
gaming-related components in accordance with one embodiment of the
present invention;
[0015] FIG. 5 is a block diagram showing in greater detail
byte-addressable non-volatile memory and flash memory;
[0016] FIG. 6 is a flow diagram of a process of writing data from
byte-addressable non-volatile memory to flash memory in accordance
with one embodiment of the spin buffering methods of the present
invention;
[0017] FIG. 7 is a flow diagram of a process of writing data to
byte-addressable non-volatile memory from other components in the
gaming machine in accordance with one embodiment;
[0018] FIG. 8 is a flow diagram of a process of recovering from an
incomplete write operation or any type of error in accordance with
one embodiment; and
[0019] FIG. 9 is a logical block diagram showing a configuration of
a hybrid memory unit in accordance with one embodiment.
DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
[0020] Reference will now be made in detail to specific embodiments
of the invention including the best modes contemplated by the
inventors for carrying out the invention. Examples of these
specific embodiments are illustrated in the accompanying drawings.
While the invention is described in conjunction with these specific
embodiments, it will be understood that it is not intended to limit
the invention to the described embodiments. On the contrary, it is
intended to cover alternatives, modifications, and equivalents as
may be included within the spirit and scope of the invention as
defined by the appended claims. In the following description,
numerous specific details are set forth in order to provide a
thorough understanding of the present invention. The present
invention may be practiced without some or all of these specific
details. In addition, well known process operations have not been
described in detail in order to not unnecessarily obscure the
present invention.
[0021] Although the present invention is directed primarily to
gaming machines and systems, it is worth noting that some of the
apparatuses, systems and methods disclosed herein might be
adaptable for use in other types of devices or environments, such
that their use is not restricted exclusively to gaming machines and
contexts. Such other adaptations may become readily apparent upon
review of the inventive devices, systems and methods illustrated
and discussed herein. The remainder of the detailed description
herein first provides general discussions of gaming machines,
gaming machine architectures and conventional MRAM devices.
Following that, specific embodiments of specialized gaming machines
having alternative gaming machine architectures are provided, after
which various methods of use for such gaming machines and gaming
systems are provided. Finally, exemplary network and system
configurations are given.
[0022] Referring first to FIG. 1, an exemplary gaming machine is
illustrated in perspective view. Gaming machine 10 includes a top
box 11 and a main cabinet 12, which generally surrounds the machine
interior (not shown) and is viewable by users. This top box and/or
main cabinet can together or separately form an exterior housing
adapted to contain a plurality of internal gaming machine
components therein. Main cabinet 12 includes a main door 20 on the
front of the gaming machine, which preferably opens to provide
access to the gaming machine interior. Attached to the main door
are typically one or more player-input switches or buttons 21, one
or more money or credit acceptors, such as a coin acceptor 22 and a
bill or ticket validator 23, a coin tray 24, and a belly glass 25.
Viewable through main door 20 is a primary video display monitor 26
and one or more information panels 27. The primary video display
monitor 26 will typically be a cathode ray tube, high resolution
flat-panel LCD, plasma/LED display or other conventional or other
type of appropriate video monitor. Alternatively, a plurality of
gaming reels can be used as a primary gaming machine display in
place of display monitor 26, with such gaming reels preferably
being electronically controlled, as will be readily appreciated by
one skilled in the art.
[0023] Top box 11, which typically rests atop of the main cabinet
12, may contain a ticket printer 28, a key pad 29, one or more
additional displays 30, a card reader 31, one or more speakers 32,
a top glass 33, one or more cameras 34, and a secondary video
display monitor 35, which can similarly be a cathode ray tube, a
high resolution flat-panel LCD, a plasma/LED display or any other
conventional or other type of appropriate video monitor.
Alternatively, secondary display monitor 35 might also be foregone
in place of other displays, such as gaming reels or physical
dioramas that might include other moving components, such as, for
example, one or more movable dice, a spinning wheel or a rotating
display. It will be understood that many makes, models, types and
varieties of gaming machines exist, that not every such gaming
machine will include all or any of the foregoing items, and that
many gaming machines will include other items not described
above.
[0024] With respect to the basic gaming abilities provided, it will
be readily understood that gaming machine 10 can be adapted for
presenting and playing any of a number of gaming events,
particularly games of chance involving a player wager and potential
monetary payout, such as, for example, a wager on a sporting event
or general play as a slot machine game, a keno game, a video poker
game, a video blackjack game, and/or any other video table game,
among others. While gaming machine 10 can typically be adapted for
live game play with a physically present player, it is also
contemplated that such a gaming machine may also be adapted for
game play with a player at a remote gaming terminal. Other features
and functions may also be used in association with gaming machine
10, and it is specifically contemplated that the present invention
can be used in conjunction with such a gaming machine or device
that might encompass any or all such additional types of features
and functions. Gaming machines such as these and other variations
and types are made by many manufacturers, such as, for example, IGT
of Reno, Nev.
[0025] With respect to electronic gaming machines in particular,
the electronic gaming machines made by IGT are provided with
special features and additional circuitry that differentiate them
from general-purpose computers, such as a laptop or desktop
personal computer. Because gaming machines are highly regulated to
ensure fairness, and in many cases are operable to dispense
monetary awards of millions of dollars, hardware and software
architectures that differ significantly from those of
general-purpose computers may be implemented into a typical
electronic gaming machine in order to satisfy security concerns and
the many strict regulatory requirements that apply to a gaming
environment. Descriptions and examples of current gaming machine
architectures can be found in a variety of references, and various
discussions of hardware and software structures for an electronic
gaming machine are disclosed in, for example, commonly assigned
U.S. Pat. No. 6,804,763 by Stockdale, et al., entitled "High
Performance Battery Backed RAM Interface;" as well as commonly
assigned and co-pending U.S. patent application Ser. No.
10/040,239, by LeMay, et al., entitled "Game Development
Architecture That Decouples The Game Logic From The Graphics
Logic;" and Ser. No. 10/041,242, by Breckner, et al., entitled
"Decoupling Of The Graphical Presentation Of A Game From The
Presentation Logic," each of which is incorporated herein in its
entirety and for all purposes. A general description of many
specializations in electronic gaming machines relative to
general-purpose computing machines and specific examples of
additional or different components and features found in such
electronic gaming machines now follows.
[0026] At first glance, one might think that adapting PC
technologies to the gaming industry would be a simple proposition,
since both PCs and gaming machines employ microprocessors that
control a variety of devices. However, because of such reasons as
1) the regulatory requirements that are placed upon gaming
machines, 2) the harsh environment in which gaming machines
operate, 3) security requirements and 4) fault tolerance
requirements, adapting PC technologies to a gaming machine can be
quite difficult. Further, techniques and methods for solving a
problem in the PC industry, such as device compatibility and
connectivity issues, might not be adequate in the gaming
environment. For instance, a fault or a weakness tolerated in a PC,
such as security holes in software or frequent crashes, may not be
tolerated in a gaming machine because in a gaming machine these
faults can lead to a direct loss of funds from the gaming machine,
such as stolen cash or loss of revenue when the gaming machine is
not operating properly.
[0027] Accordingly, one difference between gaming machines and
common PC based computers or systems is that gaming machines are
designed to be state-based systems. In a state-based system, the
system stores and maintains its current state in a non-volatile
memory, such that in the event of a power failure or other
malfunction the gaming machine will return to its current state
when the power is restored. For instance, if a player were shown an
award for a game of chance and the power failed before the award
was provided, the gaming machine, upon the restoration of power,
would return to the state where the award was indicated. As anyone
who has used a PC knows, PCs are not state machines, and a majority
of data is usually lost when a malfunction occurs. This basic
requirement affects the software and hardware design of a gaming
machine in many ways.
[0028] A second important difference between gaming machines and
common PC based computer systems is that for regulation purposes,
the software on the gaming machine used to generate the game of
chance and operate the gaming machine must be designed as static
and monolithic to prevent cheating by the operator of gaming
machine. For instance, one solution that has been employed in the
gaming industry to prevent cheating and satisfy regulatory
requirements has been to manufacture a gaming machine that can use
a proprietary processor running instructions to generate the game
of chance from an EPROM or other form of non-volatile memory. The
coding instructions on the EPROM are static (non-changeable) and
must be approved by a gaming regulator in a particular jurisdiction
and installed in the presence of a person representing the gaming
jurisdiction. Any change to any part of the software required to
generate the game of chance, such as, for example, adding a new
device driver used by the master gaming controller to operate a
device during generation of the game of chance, can require a new
EPROM to be burnt, approved by the gaming jurisdiction, and
reinstalled on the gaming machine in the presence of a gaming
regulator. Regardless of whether the EPROM solution is used, to
gain approval in most gaming jurisdictions, a gaming machine must
demonstrate sufficient safeguards that prevent an operator of the
gaming machine from manipulating hardware and software in a manner
that gives the operator an unfair or even illegal advantage over a
player. The code validation requirements in the gaming industry
affect both hardware and software designs on gaming machines.
[0029] A third important difference between gaming machines and
common PC based computer systems is that the number and kinds of
peripheral devices used on a gaming machine are not as great as on
PC based computer systems. Traditionally in the gaming industry,
gaming machines have been relatively simple in the sense that the
number of peripheral devices and the number of functions on the
gaming machine have been limited. Further, the functionality of a
gaming machine tends to remain relatively constant once the gaming
machine is deployed, in that new peripheral devices and new gaming
software is infrequently added to an existing operational gaming
machine. This differs from a PC, where users tend to buy new and
different combinations of devices and software from different
manufacturers, and then connect or install these new items to a PC
to suit their individual needs. Therefore, the types of devices
connected to a PC may vary greatly from user to user depending on
their individual requirements, and may also vary significantly over
time for a given PC.
[0030] Although the variety of devices available for a PC may be
greater than on a gaming machine, gaming machines still have unique
device requirements that differ from a PC, such as device security
requirements not usually addressed by PCs. For instance, monetary
devices such as coin dispensers, bill validators, ticket printers
and computing devices that are used to govern the input and output
of cash to a gaming machine have security requirements that are not
typically addressed in PCs. Many PC techniques and methods
developed to facilitate device connectivity and device
compatibility do not address the emphasis placed on security in the
gaming industry. To address some of these issues, a number of
hardware/software components and architectures are utilized in
gaming machines that are not typically found in general purpose
computing devices, such as PCs. These hardware/software components
and architectures include, but are not limited to, items such as
watchdog timers, voltage monitoring systems, state-based software
architectures and supporting hardware, specialized communication
interfaces, security monitoring, and trusted memory.
[0031] A watchdog timer is normally used in IGT gaming machines to
provide a software failure detection mechanism. In a normal
operating system, the operating software periodically accesses
control registers in a watchdog timer subsystem to "re-trigger" the
watchdog. Should the operating software not access the control
registers within a preset timeframe, the watchdog timer will time
out and generate a system reset. Typical watchdog timer circuits
contain a loadable timeout counter register to allow the operating
software to set the timeout interval within a certain time range. A
differentiating feature of some preferred circuits is that the
operating software cannot completely disable the function of the
watchdog timer. In other words, the watchdog timer always functions
from the time power is applied to the board.
[0032] IGT gaming computer platforms preferably use several power
supply voltages to operate portions of the computer circuitry.
These can be generated in a central power supply or locally on the
computer board. If any of these voltages falls out of the tolerance
limits of the circuitry they power, unpredictable operation of the
computer may result. Though most modern general-purpose computers
include voltage monitoring circuitry, these types of circuits only
report voltage status to the operating software. Out of tolerance
voltages can cause software malfunction, creating a potential
uncontrolled condition in the gaming computer. IGT gaming machines,
however, typically have power supplies with tighter voltage margins
than that required by the operating circuitry. In addition, the
voltage monitoring circuitry implemented in IGT gaming computers
typically has two thresholds of control. The first threshold
generates a software event that can be detected by the operating
software and an error condition generated. This threshold is
triggered when a power supply voltage falls out of the tolerance
range of the power supply, but is still within the operating range
of the circuitry. The second threshold is set when a power supply
voltage falls out of the operating tolerance of the circuitry. In
this case, the circuitry generates a reset, halting operation of
the computer.
[0033] The standard method of operation for IGT gaming machine game
software is to use a state machine. Each function of the game
(e.g., bet, play, result) is defined as a state. When a game moves
from one state to another, critical data regarding the game
software is stored in a custom non-volatile memory subsystem. In
addition, game history or "state" information can include
information regarding the amount of credits on the machine, the
state of any game in progress, data regarding previous games
played, amounts wagered, and so forth, any or all of which can be
stored in a non-volatile memory device. This feature allows the
state of the gaming machine to be recovered in the event of a
substantial interruption to the gaming machine, which can include a
power outage, a gaming machine reset, a critical hardware
malfunction, a critical software malfunction and a gaming machine
functional tilt, among other items, as will be readily appreciated.
This is critical to ensure that correct wagers, credits and other
important informational items are preserved.
[0034] Typically, battery backed RAM devices or other similar
components are used to preserve this critical data. These memory
devices are not used in typical general-purpose computers. Also,
the software structure on the gaming machine can include a safe
storage manager module that is configured to update the overall
state of the gaming machine to the non-volatile storage component
or components, preferably on a recurring basis. This safe storage
manager can also be configured to restore the gaming machine to a
part or all of the overall state stored at a non-volatile storage
component. Further details of state based storage and recovery
processes in a gaming machine are disclosed in commonly assigned
U.S. Pat. No. 6,804,763, which is again incorporated herein by
reference in its entirety and for all purposes.
[0035] In addition, substantial interruptions to the gaming machine
are typically monitored for by one or more system managers, such
as, for example, a tilt manager. Machine properties such as power
level, temperature, electrostatic level and other factors are
monitored, and cautionary signals or tilt generation instructions
are sent and acted upon as appropriate when one or more of these
properties of the gaming machine crosses a set tolerance level for
whatever reason. Details of such property monitoring and tilt
generation processes in a gaming machine are disclosed in commonly
assigned and co-pending U.S. patent application Ser. No.
09/954,816, by Breckner, et al., entitled "Modular Tilt Handling
System," which is incorporated herein by reference in its entirety
and for all purposes. Continuing further, IGT gaming computers
normally contain additional interfaces, including serial
interfaces, to connect to specific subsystems internal and external
to the gaming machine. The serial devices may have electrical
interface requirements that differ from the "standard" EIA RS232
serial interfaces provided by general-purpose computers. These
interfaces may include EIA RS485, EIA RS422, Fiber Optic Serial,
optically coupled serial interfaces, current loop style serial
interfaces, and the like. In addition, to conserve serial
interfaces internally in the gaming machine, serial devices may be
connected in a shared, daisy-chain fashion where multiple
peripheral devices are connected to a single serial channel.
[0036] IGT gaming machines may alternatively be treated as
peripheral devices to a casino communication controller and
connected in a shared daisy chain fashion to a single serial
interface. In both cases, the peripheral devices are preferably
assigned device addresses. If so, the serial controller circuitry
must implement a method to generate or detect unique device
addresses. General-purpose computer serial ports are not able to do
this. In addition, security monitoring circuits detect intrusion
into an IGT gaming machine by monitoring security switches attached
to access doors in the gaming machine cabinet. Preferably, access
violations result in suspension of game play and can trigger
additional security operations to preserve the current state of
game play. These circuits also function when power is off by use of
a battery backup. In power-off operation, these circuits continue
to monitor the access doors of the gaming machine. When power is
restored, the gaming machine can determine whether any security
violations occurred while power was off, such as by software for
reading status registers. This can trigger event log entries and
further data authentication operations by the gaming machine
software.
[0037] Trusted memory devices are preferably included in an IGT
gaming machine computer to ensure the authenticity of the software
that may be stored on less secure memory subsystems, such as mass
storage devices. Trusted memory devices and controlling circuitry
are typically designed to not allow modification of the code and
data stored in the memory device while the memory device is
installed in the gaming machine. The code and data stored in these
devices may include, for example, authentication algorithms, random
number generators, authentication keys, operating system kernels,
and so forth. The purpose of these trusted memory devices is to
provide gaming regulatory authorities a root trusted authority
within the computing environment of the gaming machine that can be
tracked and verified as original. This may be accomplished via
removal of the trusted memory device from the gaming machine
computer and verification of the secure memory device contents is a
separate third party verification device. Once the trusted memory
device is verified as authentic, and based on the approval of
verification algorithms contained in the trusted device, the gaming
machine is allowed to verify the authenticity of additional code
and data that may be located in the gaming computer assembly, such
as code and data stored on hard disk drives.
[0038] Mass storage devices used in a general purpose computer
typically allow code and data to be read from and written to the
mass storage device. In a gaming machine environment, modification
of the gaming code stored on a mass storage device is strictly
controlled and would only be allowed under specific maintenance
type events with electronic and physical enablers required. Though
this level of security could be provided by software, IGT gaming
computers that include mass storage devices preferably include
hardware level mass storage data protection circuitry that operates
at the circuit level to monitor attempts to modify data on the mass
storage device and will generate both software and hardware error
triggers should a data modification be attempted without the proper
electronic and physical enablers being present. In addition to the
basic gaming abilities provided, these and other features and
functions serve to differentiate gaming machines into a special
class of computing devices separate and distinct from general
purpose computers.
[0039] Moving next to FIG. 2, a partial exemplary architecture for
the electronic gaming machine of FIG. 1 is illustrated in block
diagram format. Although it may be appreciated that this
architecture resembles a PC architecture in some ways, there remain
various nuances that can be peculiar to such a gaming machine
architecture. It will also be appreciated that the various
architectural items illustrated represent only a portion of the
many possible architectural elements of a gaming machine, that many
other such items may also be included and/or substituted for those
shown, and that not every item shown must be included. It is also
understood that a wide variety of makes and models of hardware
components can be used for a given item, and that any such suitable
components are contemplated for use in the present invention. It
will be further understood that the various items shown are
provided for purposes of illustration only, need not be in the
particular locations or arrangements shown, much less present at
all in a given gaming machine. For example, while primary display
26 is generally at or near the center of the front face of the
gaming machine and speakers are located at the gaming machine sides
where the top box meets the main cabinet, one or more of these
items may be alternatively placed in a variety of other locations
or relative arrangements.
[0040] As is also shown in FIG. 1, gaming machine 10 generally
includes a top box 11 and main cabinet 12. CPU 50, which is
preferably the gaming machine MGC or a portion thereof, executes
the logic provided by gaming software on the gaming machine or
system. Such a CPU can be, for example, a Pentium series processor
available from Intel Corporation of Santa Clara, Calif. or a K6
series processor available from AMD Corporation of Sunnyvale,
Calif., among others. To increase the performance of this MGC or
CPU, data and instructions may be stored in a memory cache 51
directly on the CPU 50 or at some other relatively convenient
location (not shown), such as one that might be located directly
off of CPU bus 52, for example. For applications with critical data
storage requirements, such memory caches are not usually utilized
for critical data storage, since data stored in these locations may
be lost in the event of a power failure. Thus, a separate
non-volatile memory storage device is utilized, such as NVRAM2 81,
as detailed further below.
[0041] A north bridge 60 is provided essentially as a memory hub
adapted to facilitate and convert communications between various
signals, such as, for example, CPU bus signals, Peripheral
Component Interface ("PCI") bus signals, and memory bus signals,
among others. One example of such another signal can be advanced
graphic port ("AGP") signals, if applicable. Signals for the CPU
bus 52, PCI bus 69, memory bus 68, AGP (not shown) and others may
differ according to the voltage level, clock rate and bit width.
Also, the format of appropriate control signals on each type
conduit such as read strobe, write strobe, ready signal for timing,
address signals and data signals may vary from conduit to conduit.
North bridge 60, which can be any suitable form of suitable memory
hub, such as, for example, an ASIC or Field Programmable Gate Array
("FPGA"), among others, enables communications between these and
other different types of conduits. For instance, the PCI standard
is a well-defined standard used in the personal computer industry,
and is maintained by the Peripheral Component Interface Special
Interest Group ("PCISIG") of Portland, Oreg. PCI version 2.1
typically uses a 66 MHz clock rate and a 32 bit wide data signal at
5 volts to send signals. Other versions of PCI using a 133 MHz
clock rate and/or a 64 bit wide data signal may also be available.
In contrast, the clock rate used to send data signals on or "speed"
of CPU bus 52 may be much higher, such as at or above 800 MHz, as
will be readily appreciated.
[0042] One or more SDRAM units 66 may store various data and items,
such as the gaming machine software to be executed by the CPU 50.
As is generally known, such gaming machine software generally
provides and allows a game to be played on the gaming machine.
SDRAM 66 can be in communication with the CPU indirectly via north
bridge 60, and with the north bridge directly via a memory bus 68
or other similar communication link. As is generally known in the
art, such a memory bus can be relatively fast, operating at a clock
rate of at or above 800 MHz, for example. SDRAM 66 can be the
primary form of storage used by the gaming machine for high speed
data storage and processing during regular gaming machine
operations. It will also be readily appreciated that while SDRAM 66
is relatively fast, it is generally a volatile form of memory, and
as such must typically be refreshed or restored upon any new gaming
machine power up or reset, such as by loading software from a more
stable source, such as, for example, a relatively slower hard drive
72 or CD-ROM 73.
[0043] North bridge 60 also preferably connects to a wide variety
of gaming machine components, peripherals and additional memory
hubs via PCI bus 69. Keyboards, printers, audio components, video
components, touch screens, player tracking units, coin acceptors,
bill validators, network components and the like are all examples
of devices that may communicate with CPU 50 via the PCI bus 69. It
will be readily appreciated that while several specific examples of
PCI bus devices and components are illustrated and discussed as
follows, that many more may also be present and connected to the
PCI bus of a gaming machine. As one example, an audio controller
61, which may send signals to one or more speakers or other sound
projection devices, can be connected to PCI bus 69. Video
controller 62 may also be so connected, and can be used to send
signals to one or more displays connected to the gaming machine,
such as primary display 26, such that a game outcome may be
presented to a player playing a game on the gaming machine. Video
controller 62 might be installed as part of a video card that
includes video memory and a separate video processor. Using the CPU
50, audio controller 61 and video controller 62, high-quality
graphics, sound and multimedia presentations may be presented as
part of a game play, outcome or other presentation.
[0044] A tell-tale board 63 adapted to detect and record various
events when the main power to gaming machine 10 is down or
completely off can also connect to PCI bus 69. Such events can be
recorded to NVRAM1 67, which can be some form of battery backed RAM
or flash RAM, for example. As noted above, tell-tale board 63 can
be battery powered, and in any event should at least be adapted to
receive power from a source other than the main power source (not
shown) of the gaming machine. Such a secondary power source becomes
necessary if the tell-tale board is to perform its primary function
of recording critical event information while the main power is
down or off. As also noted above, such recorded events can be, for
example, a notice that a main door has been opened, a bill door has
been opened, and/or a card cage or "brain box" door has been
opened, among others. A network controller 64, which may
communicate with one or more networks including a casino local area
network ("LAN") or a wide area network ("WAN") can also be
connected to PCI bus 69. Such a network controller 64 may allow the
gaming machine to communicate with devices that provide gaming
services, such as an accounting server and a wide area progressive
server, among others. The accounting server may poll the gaming
machine for accounting information stored in a non-volatile memory
storage device, such as NVRAM2 81. The wide area progressive server
may receive information stored in NVRAM2 81, such as wagers made on
the gaming machine, and may also send information to be stored in
an NVRAM, such as the value of a progressive jackpot.
[0045] A generic controller 65 is also shown as being connected to
PCI bus 69, with such a controller representing any of the numerous
other controllers or devices that can also be connected to the PCI
bus. Controller 65 could be, for example, a player tracking unit,
keyboard, ticket printer, coin acceptor, bill validator, coin
hopper or any of various inputs, such as a touch screen or button,
for example.
[0046] One or more additional information or memory hubs may also
be linked along PCI bus 69, such as, for example, a south bridge
70. This south bridge 70 may also separately connect to various
additional memory devices, as well as one or more serial ports (not
shown), such as those for a bill validator. In one particular
example, when a monetary bill, printed ticket or other acceptable
indicia of credit is accepted by the bill validator, information
regarding the denomination of the bill or value of the ticket or
other indicia may be transferred serially using a Netplex interface
to the south bridge 70, with Netplex being an IGT proprietary
protocol. Such Netplex serial signals can then be converted to PCI
standard signals by the south bridge 70 using a Netplex device
driver. Other suitable non-proprietary methods of communication,
such as those under the RS-232 serial standard, may also be used.
The information transferred from the bill validator might be
treated as critical game information, whereby non-volatile memory
storage such as NVRAM2 81 might be used.
[0047] South bridge 70 may contain various components internally,
such as a hard drive controller 71, and can be used to connect
various stable ROM storage devices to the system, such as hard
drive 72, CD-ROM 73 and EPROM1 74, among others. Some of these
devices, such as hard drive 72 and CD-ROM 73 can connect to the
south bridge 70 via an integrated drive electronics ("IDE") bus 75
or other similar connection. As is known in the art, a typical IDE
bus operates at a speed of about 100 MHz, which is generally
appropriate for the access rates of many hard drives and CD-ROM
drives. Other devices, such as EPROM1 74, can connect to the south
bridge 70 via a basic industry standard architecture ("ISA") bus
76, which can be relatively slow in comparison to other buses and
connections. For example, a typical ISA bus might transmit data at
a speed of about 8 MHz, which would be appropriate for an EPROM and
other similarly slower components. In many gaming machines, the
boot programs used in a power up or restart process tend to be in
multiple locations, such as an initial basic input/output system
("BIOS") at a "BOOT 1" location within EPROM1 74 and an extended
BIOS at a "BOOT2" location within EPROM2 82, as discussed in
greater detail below. Other components might also connect to south
bridge 70 by a universal serial bus ("USB") (not shown) and/or any
of a number of other suitable buses and connections, as will be
readily appreciated.
[0048] Additional components and storage devices can also be
connected to the PCI bus 69 as part of a gaming system extension,
such as through an FPGA 80 or another similar logic device or
memory hub. FPGA 80 can be, for example, a model XC3S50 FPGA
manufactured by Xilinx, Inc. of San Jose, Calif. Alternatively,
such a gaming system extension can be another PCI interface device,
such as the PLX 9050 made by PLX Technology of Sunnyvale, Calif. Of
course, any other similarly suitable device can also be used as a
gaming system extension. FPGA 80 or other gaming system extension
can include various serial connections that allow communication
with several devices, such as player tracking units, wide area
progressive systems and casino area networks, among others. Memory
units that connect to the PCI bus 69 through FPGA 80 or another
similar extension can include, for example, a battery backed RAM or
other non-volatile memory unit NVRAM2 81, a boot related memory
unit EPROM2 82, and a "black box" EEPROM 83 for storing data and
other gaming machine specific information, among others. Of course,
multiple FPGAs or other similar extension devices may also connect
to PCI bus 69, although only one is illustrated here for purposes
of simplicity and discussion.
[0049] One use for battery backed RAM or otherwise non-volatile
NVRAM2 81 is to preserve a game history or state of the gaming
machine. Such a gaming machine history or state can include many
details and data items regarding information from a game
presentation and/or outcome, including one or more frames from a
sequence of frames used in the game outcome or presentation. Such
frames may be copied to NVRAM2 81 from frame buffers residing on
the video controller 62 or at another location in the gaming
machine. As such, NVRAM2 81 is a "safe storage" device for gaming
machine 10, and can be connected to PCI bus 69 for a number of
reasons. For one, the PCI bus 69 allows for a relatively fast
connection (e.g., 66 or 133 MHz) to the CPU 50 from NVRAM2 81 (via
FPGA 80, north bridge 60 and the faster CPU bus 52). Such a speedy
connection is important, since the software typically does not
advance to the next state until the current state is executed or
rolled back in a state based transaction system. Execution of each
state involves a number of access requests to NVRAM2 81, such that
the access rate to this device typically affects the performance of
the entire gaming machine or system. Although a faster connection
than PCI bus 69 might be desirable, the speed of this bus tends to
be on par with the speed of many typical battery backed RAM
devices, such that a faster bus would not provide any significant
advantage when used with NVRAM2 81.
[0050] Other reasons for using a PCI bus in association with NVRAM2
81 or other battery backed RAM can include the fact that there is
typically no data caching on a PCI bus, which is an important
feature where critical data is being backed up, as well as the
ability for items on a PCI bus to be interchangeable and to be
tolerant of changes on a main processor board, such as a CPU swap.
This permits flexibility in swapping out various gaming machine
components without having to make any corresponding changes to the
NVRAM2 81 for purposes of compatibility. It is preferable that a
gaming machine safe storage component, such as NVRAM2 81, be
relatively large, given its critical function of backing up states
in a gaming machine. Such an inclusion or use of a large
non-volatile memory is usually not a standard component on a PC,
thus distinguishing PCs from gaming machines at least in this
regard. Further details of safe storage at an NVRAM device are
disclosed in the previously noted commonly assigned U.S. Pat. No.
6,804,763 by Stockdale, et al., entitled "High Performance Battery
Backed RAM Interface," which has been incorporated by reference
herein in its entirety and for all purposes.
[0051] One use for a one time writable ROM such as EPROM2 82 can be
that of storage for critical extended BIOS ("BOOT2"), as noted
above. In a typical boot up or reset process, the gaming machine is
initially directed to the initial BIOS program stored at BOOT1
within the EPROM1 74 connected to south bridge 70. Once this has
been booted and acted upon, logic within the BOOT1 direct the
gaming machine to the extended BIOS program stored at BOOT2 within
the EPROM2 82 connected to FPGA 80. As will be readily appreciated,
both of these processes can involve various boot, loading,
decryption, authentication and verification processes, and any of a
number of suitable encryption techniques may be employed during
these processes. For example, a public-key encryption can involve a
combination of a private key that is known only to a single host
device and a public-key that is given to any other device that
wants to communicate securely with the host device. A sending
device encrypts a document using the public key from the recipient
and its own private key. The receiving device uses the public-key
(as provided by the other device) and its own private key to decode
the encrypted message. Files may also be authenticated using
digital signatures or digital certificates created via the private
key of the sender. Such digital certificates permit the recipient
to confirm the identity of the sender, as is generally known in the
art.
[0052] Uses for a "black box" non-volatile RAM device, such as
EEPROM 83, can be for storing data specific to the exterior cabinet
or physical terminal of a gaming machine or system. Such data can
be overall cabinet or terminal based meter data, backup data or
code for other gaming machine or system components, and/or other
gaming machine or terminal specific information, such as country
designations, accounting denominations, machine yield data,
progressive jackpot data, volume settings and overall gaming
machine configuration data, among others. The need for such overall
EEPROMs or other like storage devices typically arises due to
gaming regulations, gaming operator desire to track overall data
with respect to a machine housing or physical terminal, or both. As
such, this "black box" EEPROM 83 can be located on a back plane
board of the gaming machine, such that it remains with the exterior
housing when the main processor board or "brain box" and/or its
associated components are replaced. As is generally known, a "brain
box" is typically a sheet metal enclosure within the gaming machine
that is adapted to house a number of critical components, such as
the MGC or CPU, as well as various memory devices, such as some
RAM, NVRAM, the hard drive, and other such components. This brain
box can come with a lock, and may be removable from the gaming
machine as an entire unit in some cases. EEPROM 83 can then be
interfaced to the new "brain box" and/or other components that are
newly installed, as will be readily appreciated.
[0053] Referring again to FIG. 2, designations for those items that
are primarily associated with the main processor board or "brain
box," such that they are typically removed from the gaming machine
along with the brain box when it is replaced, are shown as being
within brain box region 40. Conversely, those gaming machine items
that are primarily associated with the gaming machine exterior
housing, such that they remain with the exterior housing while the
main processor board is replaced, are seen as being within back
plane board region 41. As shown, replacement of a main processor
board typically involves the replacement of CPU 50, its cache 51,
north bridge 60, SDRAM 66, south bridge 70, hard drive 72, CD-ROM
73, EPROM1 74, FPGA 80, NVRAM2 81, EPROM2 82 and possibly one or
more other components, such as generic controller 65. Items that
usually remain with the cabinet or exterior housing during a brain
box swap can include the "black box" EEPROM 83, as well as audio
controller 61 and speakers 32, video controller 62 and main display
26, tell-tale board 63 and its associated NVRAM1 67, and network
controller 64, among others.
[0054] FIG. 3 is a simplified block diagram of another embodiment
of an example gaming machine 200 in accordance with a specific
embodiment of the present invention. As illustrated in the
embodiment of FIG. 3, gaming machine 200 includes at least one
processor 210, at least one interface 206, and memory 216.
[0055] In one implementation (not shown), processor 210 and master
gaming controller 212 are included in a logic device 213 enclosed
in a logic device housing. In the implementation shown in FIG. 3,
processor 210 is in logic device 213 which, together with other
components described below, are in master gaming controller 212.
Processor 210 may include any conventional processor or logic
device configured to execute software allowing various
configuration and reconfiguration tasks such as, for example: a)
communicating with a remote source via communication interface 206,
such as a server that stores authentication information or games;
b) converting signals read by an interface to a format
corresponding to that used by software or memory in the gaming
machine; c) accessing memory to configure or reconfigure game
parameters in memory according to indicia read from the device; d)
communicating with interfaces, various peripheral devices 222
and/or I/O devices 21 1; e) operating peripheral devices 222 such
as, for example, card reader 225 and paper ticket reader 227; f)
operating various 1/0 devices such as, for example, display 235,
key pad 230 and a light panel 216; etc. For instance, processor 210
may send messages including configuration and reconfiguration
information to display 235 to inform casino personnel of
configuration progress. As another example, logic device 213 may
send commands to light panel 237 to display a particular light
pattern and to speaker 239 to project a sound to visually and
aurally convey configuration information or progress. Light panel
237 and speaker 239 may also be used to communicate with authorized
personnel for authentication and security purposes.
[0056] Peripheral devices 222 may include several device interfaces
such as, for example: card reader 225, bill validator/paper ticket
reader 227, hopper 229, etc. Card reader 225 and bill
validator/paper ticket reader 227 may each comprise resources for
handling and processing configuration indicia such as a
microcontroller that converts voltage levels for one or more
scanning devices to signals provided to processor 210. In one
embodiment, application software for interfacing with peripheral
devices 222 may store instructions (such as, for example, how to
read indicia from a portable device) in a memory device such as,
for example, non-volatile memory, hard drive or a flash memory.
[0057] Gaming machine 200 also includes memory 216 which may
include, for example, volatile memory (e.g., RAM 209), non-volatile
memory 219 (e.g., FLASH memory, EPROMs, battery backed RAM, etc.),
unalterable memory (e.g., EPROMs 208), alternate storage 217 (e.g.,
non-volatile memory implemented using disk drive(s), flash memory,
remote storage, etc.), etc. The memory may be configured or
designed to store, for example: 1) configuration software 214 such
as all the parameters and settings for a game playable on the
gaming machine; 2) associations 218 between configuration indicia
read from a device with one or more parameters and settings; 3)
communication protocols allowing processor 210 to communicate with
peripheral devices 222 and I/O devices 211; 4) a secondary memory
storage device 215 such as a non-volatile memory device, configured
to store gaming software related information (the gaming software
related information and memory may be used to store various audio
files and games not currently being used and invoked in a
configuration or reconfiguration); 5) communication transport
protocols (such as, for example, TCP/IP, USB, Firewire, IEEE1394,
Bluetooth, IEEE 802.11x (IEEE 802.11 standards), hiperlan/2,
HomeRF, etc.) for allowing the gaming machine to communicate with
local and non-local devices using such protocols; etc. Typically,
the master gaming controller 212 communicates using a serial
communication protocol. A few examples of serial communication
protocols that may be used to communicate with the master gaming
controller include but are not limited to USB, RS-232 and Netplex
(a proprietary protocol developed by IGT, Reno, Nev.).
[0058] A plurality of device drivers 242 may be stored in memory
216 or separately as shown. Example of different types of device
drivers may include device drivers for gaming machine components,
device drivers for peripheral components 222, etc. Typically,
device drivers 242 utilize a communication protocol of some type
that enables communication with a particular physical device. The
device driver abstracts the hardware implementation of a device.
For example, a device driver may be written for each type of card
reader that may be potentially connected to the gaming machine.
Examples of communication protocols used to implement device
drivers 259 include Netplex 260, USB 265, Serial 270, Ethernet 275,
Firewire 285, I/O debouncer 290, direct memory map, serial, PCI 280
or parallel. Netplex is a proprietary IGT standard while the others
are open standards. According to a specific embodiment, when one
type of a particular device is exchanged for another type of the
particular device, a new device driver may be loaded from memory
216 by processor 210 to allow communication with the device. For
instance, one type of card reader in gaming machine 200 may be
replaced with a second type of card reader where device drivers for
both card readers are stored in the memory 216.
[0059] In some embodiments, gaming machine 200 may also include
various authentication and/or validation components 244 which may
be used for authenticating/validating specified gaming machine
components such as, for example, hardware components, software
components, firmware components, information stored in the gaming
machine memory 216, etc.
[0060] In some embodiments, the software units stored in the memory
216 may be upgraded as needed. For instance, when the memory 216 is
a hard drive, new games, game options, various new parameters, new
settings for existing parameters, new settings for new parameters,
device drivers, and new communication protocols may be uploaded to
the memory from the master gaming controller 104 or from some other
external device. As another example, when the memory 216 includes a
CD/DVD drive including a CD/DVD designed or configured to store
game options, parameters, and settings, the software stored in the
memory may be upgraded by replacing a first CD/DVD with a second
CD/DVD. In yet another example, when the memory 216 uses one or
more flash memory 219 or EPROM 208 units designed or configured to
store games, game options, parameters, settings, the software
stored in the flash and/or EPROM memory units may be upgraded by
replacing one or more memory units with new memory units which
include the upgraded software. In another embodiment, one or more
of the memory devices, such as the hard-drive, may be employed in a
game software download process from a remote software server.
[0061] FIG. 4 is a block diagram showing components of a hybrid
memory component that may be used in a gaming machine or in
gaming-related components, such as accounting systems and player
tracking systems, in accordance with one embodiment of the present
invention. Various types of gaming data, described in greater
detail below, are received from a master gaming controller (or CPU)
402 or other appropriate component in a gaming machine at a
non-volatile memory manager 404 which may be implemented as a
hardware component or as a software module. Thus, box 404 may
represent a hardware or software component or a combination of
both. In other embodiments, memory manager 404 may not be required.
For example, a more generic data logger component or any component
suitable, such as those described above, for managing the writing
of all types of game-related data to the non-volatile memory may be
used.
[0062] A non-volatile memory component 406 may consist of at least
two components: a byte-addressable non-volatile memory 408 and a
block-addressable non-volatile memory 410. For ease of illustration
and discussion, block-addressable non-volatile memory 410 may be
referred to as "flash memory" or "flash," in specific embodiments
(and may be a different component from the flash memories described
above). For example, it may be implemented as a flash chip or as a
compact flash card, although it is understood that other suitable
types of memory devices may be used in place of flash memory, such
as hard disks, as discussed below. Thus, flash memory is used in
but one embodiment of the hybrid memory and spin buffering
techniques of the present invention.
[0063] FIG. 5 is a block diagram showing in greater detail
byte-addressable non-volatile memory 408 and flash memory 410. In
one embodiment, byte-addressable non-volatile memory 408 has a
series of three or more buffers. The number of buffers needed may
depend on the volume of data being sent from the gaming machine
components and the manner in which such data is received (e.g., the
frequency of "data bursts" from the gaming machine). In one
embodiment, a buffer can store 512 bytes. The capacity of a buffer
A 502, for example, may depend directly on the size of the block or
sectors in flash memory 410 (e.g., 512k, 1024k, 4096k, etc.).
Details on deriving the adequate or appropriate size of a buffer to
meet the gaming system's needs and the jurisdictional requirements
are described below. Also stored in byte-addressable non-volatile
memory 408 are "housekeeping" or administrative data 504. In an
alternative embodiment, non-volatile memory 408 may have management
firmware. In the primary embodiment, the operations of
byte-addressable non-volatile memory 408 and flash memory 410
(described below) are managed by memory manager 404.
[0064] Flash memory 410 may consist of multiple blocks, such as
Block A 508, which in one embodiment has a capacity of 512 bytes.
As described below, in other embodiments, the size of a memory
block in flash 410 may vary, but is typically a multiple of the
sector size. In other embodiments, a hard disc or other rotating
platter-type memory device may be used.
[0065] FIG. 5 also shows exchange of data from memory 408 to 410
and confirmations from memory 410 to memory manager 404 or directly
to byte-addressable memory 408, which are described in the flow
diagrams below. In brief, gaming data is written to
block-addressable non-volatile memory 410 for persistent storage
and confirmations are sent from it to byte-addressable non-volatile
memory 408 at specific stages in the operation.
[0066] FIG. 6 is a flow diagram of a process of writing data from
byte-addressable non-volatile memory to flash memory in accordance
with one embodiment of the spin buffering methods of the present
invention. It will be understood that not every step provided for
is necessary, that other steps might be included, such as start or
reboot processes, and that the order of steps might be rearranged
as desired for a given application. At step 602 non-volatile memory
manager 404 determines whether a buffer in byte-addressable
non-volatile memory is in a FULL state by checking housekeeping
data. If the buffer is full, the state of the buffer is changed to
BUSY (or something similar) in preparation of the writing operation
of the data to flash memory (or block-addressable non-volatile
memory). At step 606 the data in it is written to a block in
block-addressable non-volatile memory. If at step 602 it is
determined that the buffer is not FULL, data is continued to be
written to the buffer at step 603. In one embodiment at step 602,
the non-volatile memory manager 404 continues to check the buffer
until the buffer is in a FULL state.
[0067] At step 608 memory manager 404 or a logic component in
byte-addressable non-volatile memory 406 determines whether the
write operation is complete, for example, by checking the contents
of the buffer. If the buffer write operation is not complete, the
memory manager continues checking. If it is determined that the
write operation is complete, the block-addressable non-volatile
memory checks whether the data has been stored persistently or made
permanent in the flash memory at step 609. If it has not, given
that writing is complete, flash memory continues to check whether
the data is stored safely. If it has, at step 610 block-addressable
memory 410 transmits a confirmation to the byte-addressable buffer
or, more generally, sends a confirmation to the non-volatile memory
manager 404.
[0068] As noted above, if there is a power failure or other
disruption during the write operation, none of the data is lost
because of the characteristics of byte-addressable non-volatile
memory 408 which will continue to store the data that is being
written in case of an abnormal event. In other words, the data
remains persistent in the buffer until there is a confirmation. In
contrast, data in the block may be lost if there is a disruption
during the write operation. By sending a confirmation (i.e., data
received and persistently stored) to non-volatile memory manager
404, the flash memory is essentially informing byte-addressable
non-volatile memory 408 that it is now safe to erase the data and
mark the buffer as FREE. Thus, at step 612, the buffer is placed in
the FREE state and a block index or pointer is incremented so that
non-volatile memory 408 will write to a free block in the next
write operation. At this stage the process returns to checking if a
buffer is full at step 602.
[0069] FIG. 7 is a flow diagram of a process of writing data to
byte-addressable non-volatile memory from other components in the
gaming machine in accordance with one embodiment. At step 702
non-volatile memory manager 404 or other component in the
byte-addressable non-volatile memory 408 reads housekeeping or
administrative data for the memory in order to select the next free
buffer for receiving data. At step 704 the state of the selected
buffer is BUSY or equivalent indicating that it is storing data and
no longer free. At step 705 incoming game data is written to the
selected buffer. As described in greater detail below, game data is
intended to encompass a broad range of types and categories of
data, including game state and machine event data, such as actions
that occur asynchronously, including button pushes, door opens,
bonus events, and the like, among many others.
[0070] At step 706 memory manager 404 determines whether the buffer
has reached capacity, the size of which may vary in different
embodiments. If the buffer is not full, the writing or storing
process continues at step 705. If the buffer is full, the state of
the buffer is changed to FULL or unavailable at step 708 and the
process is complete.
[0071] FIG. 8 is a flow diagram of a process of recovering from an
incomplete write operation or any type of error in accordance with
one embodiment. This process takes place before any normal
operations (or before any atypical operations) are allowed to
proceed on the gaming machine. It may be run at boot up or start up
of the gaming machine after a power failure, tilt, or any other
unexpected interruption in the gaming machine operations that may
effect the writing of data from byte-addressable non-volatile
memory to flash memory 410 and thereby may violate the integrity of
data that, by gaming regulation and/or casino policy, is required
to be stored.
[0072] At step 802 the appropriate component, such as the
non-volatile memory manager 404 or master gaming controller 402
determines whether there was a write operation between a
byte-addressable buffer and a block in flash memory when the
failure occurred. This may be done by checking a state variable of
the buffers. The byte-addressable non-volatile memory housekeeping
data may also have a block address as well. In one embodiment, the
byte-addressable memory housekeeping data or similar data may
indicate that "This is where each buffer was at the moment of
failure and this is what each buffer was doing (i.e., it was empty,
being written to, or being read from) when the failure
occurred."
[0073] If there was a write operation in progress, then in one
embodiment, portions of data that were written to the block are
erased from flash memory. If a hard disc is being used to log the
data, the erasing step may not be necessary. Housekeeping data in
flash or byte-addressable memory may have data indicating which
portions or sectors of flash should be erased. At step 806 the data
from the buffer, which is unaffected from the failure, is
re-written to the block in flash memory. This process is generally
the same as the process described above in FIGS. 6 and 7. In one
embodiment, the data is written to the same block in flash that was
being used before the power failure or disruption. Housekeeping
data may be used to re-initiate the data writing process from the
buffer to the block. As noted above, data in the byte-addressable
non-volatile memory buffer is not lost. After the write operation
is completed and confirmation from flash memory is received, the
buffer is marked as FREE so that it may begin storing new data at
step 808 at which stage the process is complete.
[0074] FIG. 9 is a logical block diagram showing a configuration of
a hybrid memory unit that may be used to implement one embodiment.
A memory chip 902 has a byte-addressable non-volatile memory
component 904 that may be, for example, a non-volatile RAM, such as
CMOS, MRAM, PRAM, and other memory types known to those skilled in
the art that will continue to store data in the absence of
electrical power. Some of these may be battery backed, such as CMOS
nvRAM. Also contained in memory chip 902 is a block-addressable
memory 906 or, what has been referred to herein as, flash memory.
One suitable type of flash memory is single-level per cell
NAND-FLASH. For example, a Compact FLASH Card (CF-Card) may be
used. The two memory components 904 and 906 are in communication
with each other via an FPGA component 908, one implementation of
non-volatile memory manager 404 that enables data transfer between
the two memory components, maintains housekeeping data, and
communicates with other components in the gaming machine. In this
manner, the hybrid memory and spin buffering technique of the
present invention may be modularized in a single memory single
integrated circuit or a component comprising multiple integrated
circuits that can be removed from a gaming machine or, conversely,
kept in a gaming machine while other components, such as those on
or off the main processor board are removed. Of course, other
embodiments implementing the hybrid memory may be used in a gaming
machine and FIG. 9 shows only one example. For example, a hybrid
memory of the present invention may be implemented as a plug-in
card or chip.
[0075] As described above, one reason the hybrid memory of the
present invention is beneficial is because data that is required to
be stored (as dictated by gaming regulations) is not lost during a
power interruption, during a write operation, or lost due to flash
sector damage, if flash memory is used as one component in the
hybrid memory. In various embodiments, a buffer in the
byte-addressable non-volatile memory 408 is 512 bytes, 1024 bytes,
2048 (2k) bytes, or 4096 (4k) bytes.
[0076] Sufficient capacity is needed to satisfy potential, however
unlikely, gaming situations and maintain adherence with gaming
control board regulations. For example, a gaming jurisdiction may
require that transactional data on 100 games, each having a
possible 100 secondary games, be stored and accessible at all
times. Thus, storage capacity for gaming data for 10,000 games
should be available, even if the likelihood that all of it will be
needed is small.
[0077] In one embodiment, the byte-addressable non-volatile memory,
for example, Freescale's magnetoresistive RAM (MRAM), does not
require a battery. In another embodiment, it may be a
battery-backed CMOS-SRAM or an nvRAM from Simtek. In another
embodiment, it may be a phase-change RAM or PRAM.
[0078] In one embodiment, the byte-addressable and the
block-addressable non-volatile memories are on a main processor
board, along with the master gaming controller board in the gaming
machine. In another embodiment, it is on a compact flash card with
its own controller, for example implemented as an FPGA as shown in
FIG. 9 (and shown in FIG. 2). In another embodiment, a portion of
the block-addressable memory may be a hard drive, on a server in
the gaming network, or on the Internet.
[0079] As noted above, a buffer (also referred to in the art as
"heaps") in the byte-addressable non-volatile memory has a state.
In one embodiment, these states include FREE, BUSY, FULL, and
WRITE. In other embodiments, there may be more states. With respect
to buffer size, the size of the buffer may depend on several
factors. These include size of a block or sector in flash memory,
the amount of data generated, and other relevant factors, discussed
in greater detail below.
[0080] When a buffer reaches full capacity, non-volatile memory
manager software 404 may request a next free buffer in the buffer
chain. In one embodiment, a pointer is moved to point to the next
available buffer. Concurrently, another buffer may be writing to a
block in flash memory, thereby placing the buffer in a WRITE state.
When it has finished, the state of the buffer is changed to
FREE.
[0081] If there is a need to burst a large volume of data within
the gaming machine, it is preferable to have more than three
buffers (e.g., buffers 502) in the byte-addressable non-volatile
memory. Large bursts of data may occur in the gaming machine
context under circumstances such as when a data packet is
transmitted or "pumped" for each synchronous or asynchronous event.
In one scenario, a tilt may cause another tilt until the machine
stops operating, triggering a multitude of asynchronous events each
represented by one or more data packets, which may be greater than
512 bytes. In one embodiment, the size of the buffer is in accord
with the granularity of the block size in the block-addressable
non-volatile memory device. For example, a flash memory block size
may be 512 bytes, 1024 bytes or 2048 bytes for some flash devices.
Some higher density flash devices may have 16k block sizes. In one
embodiment, an entire write operation (from byte-addressable memory
to block-addressable memory) is performed in one operation to the
block device.
[0082] In one embodiment, the flash memory or, more broadly, the
block-addressable memory, and the byte-addressable memory are kept
in the cabinet of the gaming machine while other components of the
gaming machine are changed. They may also be kept in other areas of
a gaming machine (described in more detail in FIGS. 1 and 2). It is
preferable that they be kept together in the event there is a power
off during data transfer and the transfer is not complete. For
example, the byte-addressable and block-addressable memories can be
kept on the main processing board (or on a separate board that is
permanently attached to the machine) as a pair, so even if
components such as the electronics, slot tray, and the like are
changed or replace, then the memory pair may stay with the
machine.
[0083] One use for non-volatile memory is to preserve a game
history or state of the gaming machine. Such a gaming machine
history or state can include many details and data items regarding
information from a game presentation and/or outcome, including one
or more frames from a sequence of frames used in the game outcome
or presentation. Such frames may be copied to non-volatile memory
from frame buffers residing on video controller 62 or at another
location in the gaming machine.
[0084] Non-volatile memory plays a significant role in the normal
operation of a gaming machine. It may store data classified as
permanent or temporary data. The permanent type of data is
described herein as critical data. Critical data comprises data
considered to be highly important and relates to the current or
previous state(s) of a gaming machine. Examples of critical data
include game history information, security information, accounting
information, player tracking information, wide area progressive
information, game state information, game usage information, game
transactional information, game meter information, bonus of game
information, player input information, and license information.
Some of these types of data are described in greater detail below,
or any "critical" game related data. Critical data such as the
amount of funds credited to or paid out from a gaming machine may
be stored permanently in non-volatile memory as accounting
information. This critical accounting information would reflect its
current and prior states over successive rounds of play.
[0085] Among the types of commonly preserved data is so-called
"critical data" or "critical game information," which must be
maintained by casinos or other gaming machine establishment. Such
data may be stored as simple text and/or graphics. In some cases,
entire frames of video data may be captured for this purpose.
[0086] Examples of critical game transactions include, but are not
limited to, reading credit information from a debit card, adding an
amount of credit to a gaming machine, and accepting currency from a
player. The critical game transaction may require the use of
non-volatile memory either temporarily or more permanently. The
non-volatile memory may store values temporarily as an intermediate
step in the calculation of critical data. For example, when
accepting currency from a player, a bill validator may determine
the value of the currency as an integer number of dollars. This
information may be stored into non-volatile memory temporarily, as
an intermediate operational step, prior to determining the number
of credits credited in the gaming machine. If the game comprises a
25 cent game, the number of credits calculated would correspond to
forty credits if the player inserts a ten dollar bill. In this
example, the critical data stored permanently in non-volatile
memory may comprise the number of credits (forty), although the
number of dollars (ten) would comprise an intermediate operational
value in the calculation of the number of credits. As a
consequence, the intermediate value ten may comprise data that is
stored temporarily in non-volatile memory and is deleted upon the
calculation of the critical data value forty which may be stored
permanently in non-volatile memory.
[0087] Game history information may provide a record of outcomes
for a number of rounds of play for a game in a gaming machine. For
example, game history information may be used to verify the payouts
of a gaming machine so that a verification of a winning jackpot may
be performed before a payout is made if suspicious activity is
recognized. Game history may also be used, for example, to audit
the types of jackpots generated over a specified number of rounds
of play or to provide evidence that a gaming machine has been
tampered with. Hence, this type of information is critical to the
casino or gaming machine owner.
[0088] Information that provides a running count or history of the
credits that go in and out of the gaming machine may provide
valuable accounting information. For example, a gaming machine's
cumulative number of credits may be based on the bills or coins
collected, the amount of credits generated from the insertion of a
credit card, or bonus credits created by inputting a PIN (personal
identification number). This type of data may be very useful to a
gaming operator because it provides the revenue a gaming machine
generates over a period of time.
[0089] Security information may provide information related to a
tampering event on the gaming machine. Details of this information
may include time of day, type of game, the amount wagered, the
specific outcome, and any operational information, such as
diagnostics related to the condition of the gaming machine when
tampering occurred.
[0090] Player tracking information is also vital to providing
valuable feedback regarding a player's preferences. A casino may
track player information to provide the best and most desirable
playing environment to the player. Whether it be type of game,
denomination of game, length of play, amount played, or the like,
these factors provide useful information to the gaming operator it
can better attract and maintain game play from a player.
[0091] A few specific examples of critical data may include, for
example, one or more of the following: (1) Main door/Drop door/Cash
door openings and closings, (2) Bill insert message with the
denomination of the bill, (3) Hopper tilt, (4) Bill jam, (5) Reel
tilt, (6) Coin in and Coin out tilts, (7) Power loss, (8) Card
insert, (9) Card removal, (10) Jackpot, (11) Abandoned card (12)
querying the non-volatile memory for the current credit available
on the gaming machine, (13) reading the credit information from a
player's card, (14) adding an amount of credits to the gaming
machine, (15) writing to a player's card via the card reader and
the device drivers to deduct the amount added to gaming machine
from the card, and (16) copying the new credit information to the
non-volatile memory. Such information may be required, based on
jurisdictional gaming regulations, to be stored for a certain
period of time, e.g., 75 game plays after the information was
accumulated.
[0092] As described above, non-volatile memory may be configured or
designed to maintain the contents of its memory over time through
the use of a battery as a power source, thereby allowing it to be
independent of externally supplied power. As a result, non-volatile
memory can continue to store data such as accumulated information
as long as power is supplied.
[0093] The accumulative data to be saved may take the form of text,
graphics, frames, video clips, etc. In the simplest case, it is
merely textual data describing a game's state, history, statistics,
etc. A more memory-intensive form of data storage stores frames
(essentially bit maps of video still shots) for selected portions
of the game presentation; e.g., frames associated with user inputs
and presentation of game outcomes. Some of these frames may have
embedded or associated data providing specific details such as
state, statistics, etc. as described above. Yet another way to save
relevant game play information is via a game play sequence that
represents the game as it appeared originally. This involves
presentation of a series of frames and associated events,
including, for example, user interactive events. Such may be
implemented using a series of critical or desired snapshots and/or
screenshots, a movie or video clips of a game play, and/or other
mechanisms representing the game play information. To implement
this type of replay, it may be desirable to preserve essential
state information about the game and then re-execute the game code
using such state information.
[0094] During the course of game play, a gaming machine may undergo
a number of different events, such as receiving currency, hopper
tilt, reel tilt, protective tilt, power loss, player's card input,
player's card removal, personal identification input, reel spin,
multi-denomination change, jackpot tilt, and the like. During these
transactional events, the temporary or permanent non-volatile
memory or non-volatile storage requirements of the game or the
gaming machine may change. Accordingly, memory space allocations
are continuously monitored.
[0095] Gaming regulators, such as the Nevada gaming commission,
require that gaming machines prohibit the writing of code, data
and/or other gaming information to gaming machine disk drives by
sources other than trusted memory sources which have been properly
verified and authenticated. Because of such regulatory constraints,
it has been conventional practice in the gaming industry to design
and implement mechanisms for preserving critical data in the gaming
machine's non-volatile memory without utilizing memory storage at
the gaming machine's disk drive(s).
[0096] While the invention has been particularly shown and
described with reference to specific embodiments thereof, it will
be understood by those skilled in the art that changes in the form
and details of the disclosed embodiments may be made without
departing from the spirit or scope of the invention. However, it
will be understood that embodiments in which such games are
developed without such templates are within the scope of the
invention. In addition, the host of a game development environment
implemented according to the present invention does not necessarily
need to be a gaming machine provider or manufacturer to remain
within the scope of the invention. And as discussed above, any of a
wide range of technologies may be employed to implement and provide
access to such a game development environment.
[0097] Finally, although various advantages, aspects, and objects
of the present invention have been discussed herein with reference
to various embodiments, it will be understood that the scope of the
invention should not be limited by reference to such advantages,
aspects, and objects. Rather, the scope of the invention should be
determined with reference to the appended claims.
* * * * *