U.S. patent application number 12/026342 was filed with the patent office on 2009-08-06 for heating center pcram structure and methods for making.
This patent application is currently assigned to Macronix International Co., Ltd.. Invention is credited to Shih-Hung Chen.
Application Number | 20090194758 12/026342 |
Document ID | / |
Family ID | 40930781 |
Filed Date | 2009-08-06 |
United States Patent
Application |
20090194758 |
Kind Code |
A1 |
Chen; Shih-Hung |
August 6, 2009 |
HEATING CENTER PCRAM STRUCTURE AND METHODS FOR MAKING
Abstract
Memory devices are described along with manufacturing methods. A
memory device as described herein includes a bottom electrode and a
first phase change layer comprising a first phase change material
on the bottom electrode. A resistive heater comprising a heater
material is on the first phase change material. A second phase
change layer comprising a second phase change material is on the
resistive heater, and a top electrode is on the second phase change
layer. The heater material has a resistivity greater than the most
highly resistive states of the first and second phase change
materials.
Inventors: |
Chen; Shih-Hung; (Elmsford,
NY) |
Correspondence
Address: |
MACRONIX;C/O HAYNES BEFFEL & WOLFELD LLP
P. O. BOX 366
HALF MOON BAY
CA
94019
US
|
Assignee: |
Macronix International Co.,
Ltd.
Hsinchu
TW
|
Family ID: |
40930781 |
Appl. No.: |
12/026342 |
Filed: |
February 5, 2008 |
Current U.S.
Class: |
257/4 ;
257/E45.002; 438/102 |
Current CPC
Class: |
G11C 2213/79 20130101;
G11C 2013/008 20130101; H01L 45/148 20130101; H01L 45/1666
20130101; H01L 45/144 20130101; H01L 45/06 20130101; H01L 45/1233
20130101; H01L 45/1286 20130101; G11C 11/5678 20130101; G11C
13/0004 20130101 |
Class at
Publication: |
257/4 ; 438/102;
257/E45.002 |
International
Class: |
H01L 45/00 20060101
H01L045/00 |
Claims
1. A memory device comprising: a dielectric layer having a top
surface; a via extending from the top surface of the dielectric
layer and having a bottom portion and a top portion; a bottom
electrode within the bottom portion of the via; a first phase
change layer comprising a first phase change material within the
top portion of the via and contacting the bottom electrode, the
first phase change material having at least two solid phases; a
resistive heater layer comprising a heater material on the first
phase change layer; a second phase change layer comprising a second
phase change material on the resistive heater layer, the second
phase change material having at least two solid phases; and a top
electrode on the second phase change layer; wherein the heater
material has a resistivity greater than the most highly resistive
states of the first and second phase change materials.
2. The device of claim 1, wherein the first phase change layer has
a width less than a minimum feature size for a lithographic process
used to form the memory device.
3. The device of claim 2, wherein the resistive heater layer,
second phase change layer, and top electrode form a multi-layer
stack overlying the top surface of the dielectric layer.
4. The device of claim 1, wherein the resistive heater layer has a
thickness less than or equal to about 10 nm.
5. The device of claim 1, wherein the heater material has a
resistivity between about 1.5 and 100 times greater than the most
highly resistive states of the first and second phase change
materials.
6. The device of claim 5, wherein the heater material has a
resistivity between about 4 and 50 times greater than the most
highly resistive states of the first and second phase change
materials.
7. The device of claim 1, wherein the heater material comprises one
of doped TiN, TaN, TiW, TiSiN, or TaSiN.
8. The device of claim 1, wherein the first and second phase change
materials comprise the same phase change material.
9. The device of claim 1, wherein the first and second phase change
materials comprise different phase change material.
10. The device of claim 1, wherein each of the first and second
phase change materials comprise a combination of two or more
materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu,
Pd, Pb, Ag, S, Si, O, P, As, N and Au.
11. A method for manufacturing a memory device, the method
comprising: providing a bottom electrode extending to a top surface
of a dielectric layer; removing a portion of the bottom electrode
to form a recess; filling the recess with a first phase change
material layer having at least two solid phases; forming a layer of
heater material on the first phase change layer; forming a second
phase change material layer on the layer of heater material, the
second phase change material layer having at least two solid
phases; and forming a top electrode material layer on the second
phase change layer; wherein the heater material has a resistivity
greater than the most highly resistive state of the first and
second phase change materials.
12. The method of claim 11, wherein the filling the recess step
comprises: forming the first phase change material layer in the
recess and on the top surface of the dielectric layer; and
planarizing the first phase change material layer to expose the top
surface of the dielectric layer.
13. The method of claim 12, further comprising etching the layer of
heater material, the second phase change material layer, and the
top electrode material layer, thereby forming a multi-layer stack
overlying the top surface of the dielectric layer.
14. The method of claim 11, wherein the first phase change material
layer has a width less than a minimum feature size for a
lithographic process used to form the memory device.
15. The method of claim 11, wherein the resistive heater layer has
a thickness less than about 10 nm.
16. The method of claim 11, wherein the heater material has a
resistivity between about 1.5 and 100 times greater than the most
highly resistive states of the first and second phase change
materials.
17. The method of claim 11, wherein the heater material comprises
one of doped TiN, TaN, TiW, TiSiN, or TaSiN.
18. The method of claim 11, wherein the first and second phase
change materials comprise the same phase change material.
19. The method of claim 11, wherein the first and second phase
change materials comprise different phase change material.
20. The method of claim 11, wherein each of the first and second
phase change materials comprise a combination of two or more
materials from the group of Ge, Sb, Te, Se, In, Ti, Ga, Bi, Sn, Cu,
Pd, Pb, Ag, S, Si, O, P, As, N and Au.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to high density memory devices
based on phase change based memory materials, including
chalcogenide based materials and on other programmable resistive
materials, and to methods for manufacturing such devices.
[0003] 2. Description of Related Art
[0004] Phase change based memory materials are widely used in
read-write optical disks. These materials have at least two solid
phases, including for example a generally amorphous solid phase and
a generally crystalline solid phase. Laser pulses are used in
read-write optical disks to switch between phases and to read the
optical properties of the material after the phase change.
[0005] Phase change based memory materials, like chalcogenide based
materials and similar materials, also can be caused to change phase
by application of electrical current at levels suitable for
implementation in integrated circuits. The generally amorphous
state is characterized by higher electrical resistivity than the
generally crystalline state, which can be readily sensed to
indicate data. These properties have generated interest in using
programmable resistive material to form nonvolatile memory
circuits, which can be read and written with random access.
[0006] The change from the amorphous to the crystalline state is
generally a lower current operation. The change from crystalline to
amorphous, referred to as reset herein, is generally a higher
current operation, which includes a short high current density
pulse to melt or break down the crystalline structure, after which
the phase change material cools quickly, quenching the phase change
process and allowing at least a portion of the phase change
material to stabilize in the amorphous state. It is desirable to
minimize the magnitude of the reset current used to cause the
transition of the phase change material from the crystalline state
to the amorphous state. The memory cells using phase change
material include an "active region" in the bulk of the phase change
material of the cell in which the actual phase transitions are
located. Techniques are applied to make the active region small, so
that the amount of current needed to induce the phase change is
reduced. Also, techniques are used to thermally isolate the active
region in the phase change cell so that the resistive heating
needed to induce the phase change is confined to the active
region.
[0007] The magnitude of the current needed to induce a phase change
during reset can be reduced by increasing the resistivity of the
phase change material because the phase change occurs as a result
of heating and the temperature increase due to self-heating is
proportional to the resistivity of the phase change material
(ignoring heat sink effects). However, a small read current will
also be needed to insure that the phase change material does not
undergo an undesired phase change during the reading of data from
the memory cell. Issues associated with a small read current
include a slow read process. Additionally, increasing the
resistivity of the phase change material will result in a higher
overall resistance for the memory cell and does not have provide
any benefit for power consumption of the memory cell. Furthermore,
it has been observed that a higher overall memory cell resistance
may result in a lower SET speed.
[0008] The magnitude of the current needed for reset can also be
reduced by reducing the size of the phase change material element
in the cell and/or the contact area between electrodes and the
phase change material, such that higher current densities are
achieved with small absolute current values through the phase
change material element.
[0009] One direction of development has been toward forming small
pores in an integrated circuit structure, and using small
quantities of programmable resistive material to fill the small
pores. Patents illustrating development toward small pores include:
Ovshinsky, "Multibit Single Cell Memory Element Having Tapered
Contact," U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et
al., "Method of Making Chalogenide [sic] Memory Device," U.S. Pat.
No. 5,789,277, issued Aug. 4, 1998; Doan et al., "Controllable
Ovonic Phase-Change Semiconductor Memory Device and Methods of
Fabricating the Same," U.S. Pat. No. 6,150,253, issued Nov. 21,
2000.
[0010] Another technology developed by the assignee of the present
application is referred to as a phase change bridge cell, in which
a very small patch of memory material is formed as a bridge across
a thin film insulating member located between electrodes. The phase
change bridge is easily integrated with logic and other types of
circuitry on integrated circuits. See, U.S. application Ser. No.
11/155,067, filed 17 Jun. 2005, entitled "Thin Film Fuse Phase
Change RAM and Manufacturing Method," by Lung et al., incorporated
by reference as if fully set forth herein, which application was
owned at the time of invention and is currently owned by the same
assignee.
[0011] Yet another approach to controlling the size of the active
area in a phase change cell is to devise very small electrodes for
delivering current to a body of phase change material. This small
electrode structure induces phase change in the phase change
material in a small area like the head of a mushroom, at the
location of the contact. See, U.S. Pat. No. 6,429,064, issued Aug.
6, 2002, to Wicker, "Reduced Contact Areas of Sidewall Conductor;"
U.S. Pat. No. 6,462,353, issued Oct. 8, 2002, to Gilgen, "Method
for Fabricating a Small Area of Contact Between Electrodes;" U.S.
Pat. No. 6,501,111, issued Dec. 31, 2002, to Lowrey,
"Three-Dimensional (3D) Programmable Device;" U.S. Pat. No.
6,563,156, issued Jul. 1, 2003, to Harshfield, "Memory Elements and
Methods for Making Same."
[0012] One approach to the heat flow problem is seen in U.S. Pat.
No. 6,815,704, entitled "Self Aligned Air-Gap Thermal Insulation
for Nano-scale Insulated Chalcogenide Electronics (NICE) RAM", in
which an attempt is made to isolate the memory cell using gaps or
voids on the sides of the phase change material. It has also been
proposed to use thermally insulating materials to improve the
confinement of heat to the active region.
[0013] Also, approaches to improving thermal isolation include
forming the phase change element in a way that tends to isolate the
active region from the electrodes, as shown for example in U.S.
patent application Ser. No. 11/348,848, filed 7 Feb. 2006, entitled
"I-Shaped Phase Change Memory Cell" by Chen et al., incorporated by
reference as if fully set forth herein, which application was owned
at the time of invention and is currently owned by the same
assignee.
[0014] Problems have arisen in manufacturing devices with very
small dimensions, and with variations in process that meet tight
specifications needed for large-scale memory devices. It is
therefore desirable to provide a memory cell structure having small
dimensions and low reset currents, as well as a structure that
addresses the heat flow problem, and methods for manufacturing such
structure that meets tight process variation specifications needed
for large-scale memory devices. Furthermore, it is desirable to
produce memory devices having a small active phase change
region.
SUMMARY OF THE INVENTION
[0015] A memory device as described herein includes a bottom
electrode and a first phase change layer comprising a first phase
change material on the bottom electrode. A resistive heater
comprising a heater material is on the first phase change material.
A second phase change layer comprising a second phase change
material is on the resistive heater, and a top electrode is on the
second phase change layer. The heater material has a resistivity
greater than the most highly resistive states of the first and
second phase change materials.
[0016] In embodiments illustrated, a memory cell includes a
dielectric layer having a top surface and a via extending from the
top surface of the dielectric layer. The bottom electrode is within
a bottom portion of the via and the first phase change layer is
within the top portion of the via.
[0017] A method for manufacturing a memory device as described
herein includes providing a bottom electrode extending to a top
surface of a dielectric layer, and removing a portion of the bottom
electrode to form a recess. The method includes filling the recess
with a first phase change material layer, and forming a layer of
heater material on the first phase change layer. A second phase
change layer is formed on the layer of heater material, and a top
electrode material layer on the second phase change layer.
[0018] A memory cell as described herein results in an active
region that can be made very small and provides some thermal
isolation from the top and bottom electrodes, thereby reducing the
amount of current needed to induce a phase change. The first phase
change layer has a width less than the width of the second phase
change layer, the width of the first phase change layer preferably
less than a minimum feature size for a process, typically a
lithographic process, used to form the memory cell. The difference
in widths concentrates current in the first phase change layer,
thereby reducing the magnitude of current needed to induce a phase
change in the active region of the memory cell. Additionally, the
heater material has a resistivity greater than that of the phase
change materials of the first and second phase change layers, thus
raising the temperature of the portions of the first and second
phase change layers adjacent the heater layer relative to the other
portions of the first and second phase change layers. This can
result in the active region being spaced away from the top and
bottom electrodes, which allows the remaining portions of the first
and second phase change layers to provide some thermal isolation to
the active region, which also helps to reduce the amount of current
necessary to induce a phase change.
[0019] Other aspects and advantages of the invention are described
below with reference to the figures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 illustrates a cross-sectional view of a "mushroom"
phase change memory cell.
[0021] FIG. 2 illustrates a cross-sectional view of a "pillar-type"
phase change memory cell.
[0022] FIG. 3 illustrates a cross-sectional view of a memory cell
in accordance with an embodiment.
[0023] FIG. 4A illustrates a cross-sectional view of a memory cell
similar to that of FIG. 3 with the heater layer omitted.
[0024] FIG. 4B illustrates the heat generated in the phase change
layer of the memory cell illustrated in FIG. 4A during
operation.
[0025] FIG. 4C illustrates the heat loss in the phase change layer
of the memory cell illustrated in FIG. 4A during operation.
[0026] FIGS. 5-8 illustrate an embodiment of a process flow for
manufacturing memory cells described herein.
[0027] FIG. 9 is a simplified block diagram of an integrated
circuit in accordance with an embodiment.
[0028] FIG. 10 is schematic illustration of a memory array
implemented using memory cells as described herein.
DETAILED DESCRIPTION
[0029] The following description of the invention will typically be
with reference to specific structural embodiments and methods. It
is understood that there is no intention to limit the invention to
the specifically disclosed embodiments and methods but that the
invention may be practiced using other features, elements, methods,
and embodiments. Preferred embodiments are described to illustrate
the present invention, not to limit its scope, which is defined by
the claims. Those of ordinary skill in the art will recognize a
variety of equivalent variations on the description that follows.
Like elements in various embodiments are commonly referred to with
like reference numerals.
[0030] A detailed description is provided with reference to FIGS.
1-10.
[0031] FIG. 1 illustrates a cross-sectional view of a prior art
"mushroom" memory cell having a bottom electrode 120 extending
through a dielectric layer 110, a layer of phase change material
130 on the bottom electrode 120, and a top electrode 140 on the
phase change material 130. A dielectric layer 160 surrounds the
layer of phase change material 130. As can be seen in FIG. 1, the
bottom electrode 120 has a width 125 less than the width 145 of the
top electrode 140 and phase change material 130. Due to the
differences in the widths 125 and 145, in operation the current
density will be largest in the region of the phase change layer 130
adjacent the bottom electrode 120, resulting in the active region
150 of the phase change material having a "mushroom" shape as shown
in FIG. 1.
[0032] Because the phase change in the active region 150 occurs as
a result of heating, the thermal conductivity of the bottom
electrode 120 will act to draw heat away from the active region
150, thus resulting in a need for higher current to induce the
desired phase change in the active region 150.
[0033] FIG. 2 illustrates a cross-sectional view of a prior art
"pillar-type" memory cell 200. The memory cell 200 includes a
bottom electrode 220 in a dielectric layer 210, a pillar of phase
change material 230 on the bottom electrode 220, and a top
electrode 240 on the pillar of phase change material 230. A
dielectric layer 260 surrounds the pillar of phase change material
230. As can be seen in the Figure the top and bottom electrodes
240, 220 have the same width 275 as that of the pillar of phase
change material 230. Thus, the active region 250 can be spaced away
from the top and bottom electrodes 240, 220, resulting in a reduced
heat sink effect by the top and bottom electrodes 240, 220.
However, there is heat loss through the sidewalls 232 of the phase
change material 230 to the dielectric layer 260 due to the
proximity of the active region 250 to the dielectric layer 260.
[0034] Additionally, the pillar of phase change material 230 may be
formed by depositing a phase change material layer on the bottom
electrode 220 and dielectric 210 and subsequently etching the phase
change material layer to form the pillar 230. Problems have arisen
in manufacturing such devices due to etch damage to the sidewalls
232 of the pillar of memory material 230 and alignment tolerance
issues between the pillar of memory material 230 and the bottom
electrode 220.
[0035] FIG. 3 illustrates a cross-sectional view of a memory cell
300 in accordance with an embodiment, the memory cell having a
resistive heater layer 305 between first and second phase change
layers 330, 335. The resistive heater layer 305 comprises heater
material having a resistivity greater than the most highly
resistive state of the phase change materials of the first and
second phase change layers 330, 335.
[0036] A via 360 extends from a top surface 312 of the dielectric
310, and the first phase change layer 330 is within a top portion
of the via 360 and a bottom electrode 320 is within a bottom
portion of the via 360.
[0037] The bottom electrode 320 contacts the first phase change
layer 330 and extends through the dielectric 310 to underlying
access circuitry. The bottom electrode 320 may comprise, for
example, TiN or TaN. TiN may be preferred in embodiments in which
the phase change layer comprises GST (discussed below) because it
makes good contact with GST, it is a common material used in
semiconductor manufacturing, and it provides a good diffusion
barrier at the higher temperatures at which GST transitions,
typically in the 600-700.degree. C. range. Alternatively, the
bottom electrode 320 may be TiAlN or TaAlN, or comprises, for
further examples, one or more elements selected from the group
consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, N, O and Ru
and combinations thereof.
[0038] A top electrode 340 is on the second phase change layer 335
and may comprise, for example, any of the materials described above
with reference to the bottom electrode 320.
[0039] In operation, voltages on the top electrode 340 and bottom
electrode 320 can induce current to flow from the bottom electrode
320 to the top electrode 340, or vice versa, via the first phase
change layer 330, the heater layer 305, and the second phase change
layer 335.
[0040] The active region 333 is the region of the memory cell 300
in which memory material is induced to change between at least two
solid phases. As can be appreciated the active region 333 can be
made extremely small in the illustrated structure, thus reducing
the magnitude of current needed to induce a phase change. The first
phase change layer 330 has a width 331 less than the width 336 of
the second phase change layer 335, the width 331 preferably less
than a minimum feature size for a process, typically a lithographic
process, used to form the memory cell 300. The difference in the
widths 331, 336 concentrates current density in the first phase
change layer 330, thereby reducing the magnitude of current needed
to induce a phase change in the active region 333. Additionally,
the heater material of the heater layer 305 has a resistivity
greater than that of the phase change materials of the first and
second phase change layers 330, 335, thus raising the temperature
of the portions of the first and second phase change layers 330,
335 adjacent the heater layer 305 relative to the other portions of
the first and second phase change layers 330, 335. As can be seen
in the Figure, the active region 333 is spaced away from both the
top and bottom electrodes 340, 320, which allows the remaining
portions of the first and second phase change layers 330, 335 to
provide some thermal isolation to the active region 330, which also
helps to reduce the amount of current necessary to induce a phase
change.
[0041] The resistance of the heater layer 305 is proportional to
the thickness 307 and to the resistivity of the heater material.
Increasing the resistance of the heater layer 305 will increase the
overall resistance of the memory cell 300, which does not provide
any benefits for power consumption of the memory cell 300 and can
result in a slower read process of the memory cell 300. However, as
explained in more detail below, during operation the increase in
temperature in the heater layer 305 is proportional to the
resistivity of the heater material. Thus increasing the resistivity
of the heater material is desirable since this can reduce the
magnitude of the current needed to induce a phase change in the
active region 333. Therefore, the thickness 307 of the heater layer
305 is preferably very thin while the resistivity of the heater
material is high.
[0042] Ignoring heat sink effects, the change in temperature of a
self-heated element due to a current I can be given by:
.DELTA. T = I 2 R t M s ( 1 ) ##EQU00001##
where M is the mass of the element, s is the specific heat content
of the material, T is temperature, I is the electrical current, R
is the electrical resistance, and t is time. Furthermore, the mass
M, current I, and resistance R can be represented respectively
by:
M = A h D ( 2 ) I = J A ( 3 ) R = .rho. h A ( 4 ) ##EQU00002##
where A is the cross-sectional area of the current flow in the
element, h is the height of the element, D is the density of the
material, J is the current density, and .rho. is the resistivity of
the material. Combining equations (2) to (4) into equation (1)
results in:
.DELTA. T = J 2 .rho. t s d ( 5 ) ##EQU00003##
[0043] Therefore, as can be seen in equation (5) above the change
in temperature is proportional to the resistivity of the
material.
[0044] In one embodiment the resistivity of the heater material is
between about 1.5 and 100 times greater than the most highly
resistive states of the phase change materials of the first and
second phase change layers 330, 335, and in another example is
between about 4 and 50 times greater.
[0045] Additionally, the thickness 307 of the resistive heater
layer 305 is preferably less than that of the first phase change
layer 330. In some embodiments the thickness 307 is less than or
equal to 10 nm, for example being between about 1 nm and 5 nm.
[0046] The resistive heater layer 305 is doped with impurities in
some embodiments to modify resistivity, and may comprise, for
example, highly doped TiN, TaN, TiW, TiSiN, or TaSiN. Impurities
used in doping to increase the resistivity may include, for
example, nitrogen, carbon, or silicon. In embodiments in which the
resistive heater layer 305 is formed by a plasma vapor deposition
PVD process, increased doping may be accomplished, for example, by
using a high doped target and/or increasing the N2 flow. In a
chemical vapor deposition CVD or atomic vapor deposition ALD
process, the increased doping may be achieved, for example, by
increasing the N2 flow and/or reducing the operation temperature of
these processes.
[0047] In one embodiment the resistive heater layer 305 is formed
by depositing TiN using a TDMAT (Ti[N(CH.sub.3).sub.2].sub.4)
precursor, resulting in a significant amount of impurities (mainly
Carbon) and causing a high resistivity. An H.sub.2 plasma treatment
can be used to remove the carbon and reduce the resistivity.
[0048] Embodiments of the memory cell 300 include phase change
based memory materials, including chalcogenide based materials and
other materials, for the first and second phase change layers 330,
335. The first and second phase change layers 530, 535 may comprise
the same or different phase change materials. Chalcogens include
any of the four elements oxygen (O), sulfur (S), selenium (Se), and
tellurium (Te), forming part of group VI of the periodic table.
Chalcogenides comprise compounds of a chalcogen with a more
electropositive element or radical. Chalcogenide alloys comprise
combinations of chalcogenides with other materials such as
transition metals. A chalcogenide alloy usually contains one or
more elements from column six of the periodic table of elements,
such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys
include combinations including one or more of antimony (Sb),
gallium (Ga), indium (In), and silver (Ag). Many phase change based
memory materials have been described in technical literature,
including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te,
In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te,
Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a
wide range of alloy compositions may be workable. The compositions
can be characterized as Te.sub.aGe.sub.bSb.sub.100-(a+b).
[0049] Chalcogenides and other phase change materials are doped
with impurities in some embodiments to modify conductivity,
transition temperature, melting temperature, and other properties
of memory elements using the doped chalcogenides. Representative
impurities used for doping chalcogenides include nitrogen, silicon
oxygen, silicon dioxide, silicon nitride, copper, silver, gold,
aluminum, aluminum oxide, tantalum, tantalum oxide, tantalum oxide,
tantalum nitride, titanium and titanium oxide. See, for example
U.S. Pat. No. 6,800,504, and U.S. Patent Application Publication
No. US 2005/0029502.
[0050] One researcher has described the most useful alloys as
having an average concentration of Te in the deposited materials
well below 70%, typically below about 60% and ranged in general
from as low as about 23% up to about 58% Te and most preferably
about 48% to 58% Te. Concentrations of Ge were above about 5% and
ranged from a low of about 8% to about 30% average in the material,
remaining generally below 50%. Most preferably, concentrations of
Ge ranged from about 8% to about 40%. The remainder of the
principal constituent elements in this composition was Sb. These
percentages are atomic percentages that total 100% of the atoms of
the constituent elements. (Ovshinsky '112 patent, cols 10-11.)
Particular alloys evaluated by another researcher include
Ge.sub.2Sb.sub.2Te.sub.5, GeSb.sub.2Te.sub.4 and
GeSb.sub.4Te.sub.7. (Noboru Yamada, "Potential of Ge--Sb--Te
Phase-Change Optical Disks for High-Data-Rate Recording", SPIE v.
3109, pp. 28-37 (1997).) More generally, a transition metal such as
chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium
(Pd), platinum (Pt) and mixtures or alloys thereof may be combined
with Ge/Sb/Te to form a phase change alloy that has programmable
resistive properties. Specific examples of memory materials that
may be useful are given in Ovshinsky '112 at columns 11-13, which
examples are hereby incorporated by reference.
[0051] Phase change alloys are capable of being switched between a
first structural state in which the material is in a generally
amorphous solid phase, and a second structural state in which the
material is in a generally crystalline solid phase in its local
order in the active channel region of the cell. These alloys are at
least bistable. The term amorphous is used to refer to a relatively
less ordered structure, more disordered than a single crystal,
which has the detectable characteristics such as higher electrical
resistivity than the crystalline phase. The term crystalline is
used to refer to a relatively more ordered structure, more ordered
than in an amorphous structure, which has detectable
characteristics such as lower electrical resistivity than the
amorphous phase. Typically, phase change materials may be
electrically switched between different detectable states of local
order across the spectrum between completely amorphous and
completely crystalline states. Other material characteristics
affected by the change between amorphous and crystalline phases
include atomic order, free electron density and activation energy.
The material may be switched either into different solid phases or
into mixtures of two or more solid phases, providing a gray scale
between completely amorphous and completely crystalline states. The
electrical properties in the material may vary accordingly.
[0052] Phase change alloys can be changed from one phase state to
another by application of electrical pulses. It has been observed
that a shorter, higher amplitude pulse tends to change the phase
change material to a generally amorphous state. A longer, lower
amplitude pulse tends to change the phase change material to a
generally crystalline state. The energy in a shorter, higher
amplitude pulse is high enough to allow for bonds of the
crystalline structure to be broken and short enough to prevent the
atoms from realigning into a crystalline state. Appropriate
profiles for pulses can be determined empirically or by modeling,
and specifically adapted to a particular phase change alloy. In
following sections of the disclosure, the phase change material is
referred to as GST, and it will be understood that other types of
phase change materials can be used. A material useful for
implementation of a PCRAM described herein is
Ge.sub.2Sb.sub.2Te.sub.5.
[0053] Representative chalcogenide material can be characterized as
follows: Ge.sub.xSb.sub.yTe.sub.z, where x:y:z=2:2:5. Other
compositions can be used with x: 0.about.5; y: 0.about.5; z:
0.about.10. GeSbTe with doping, such as N-, Si-, Ti-, or other
element doping may also be used. These materials can be formed by
PVD sputtering or magnetron-sputtering with reactive gases of Ar,
N.sub.2, and/or He, etc. and chalcogenide at the pressure of 1
mtorr.about.100 mtorr. The deposition is usually done at room
temperature. A collimator with an aspect ratio of 1.about.5 can be
used to improve the fill-in performance. To improve the fill-in
performance, the DC bias of several tens of volts to several
hundred volts is also used. Also, the combination of DC bias and
the collimator can be used simultaneously. The post deposition
annealing treatment with vacuum or N2 ambient is sometimes needed
to improve the crystallize state of chalcogenide material. The
annealing temperature typically ranges 100.degree. C. to
400.degree. C. with an anneal time of less than 30 minutes.
[0054] As was described above, the heater material of the heater
layer 305 has a resistivity greater than that of the phase change
materials of the first and second phase change layers 330, 335,
thus raising the temperature of the portions of the first and
second phase change layers 330, 335 adjacent the heater layer 305
relative to the other portions of the first and second phase change
layers 330, 335 and reducing the heat sink effect due to the top
and bottom electrodes 340, 320.
[0055] FIG. 4A illustrates a cross-sectional view of a memory cell
400 similar to that illustrated in FIG. 3 with the heater layer 305
omitted. Without the heater layer 305, the large current density in
the region 432 of the phase change material 430 below the top
surface 412 of the dielectric 410 will result in significant heat
generated adjacent to the bottom electrode 420, as shown in FIG. 4B
with the darker colors indicating higher heat generation. Due to
the high thermal conductivity of the bottom electrode 420 there
will also be a significant amount of heat loss within the region
432 as shown in FIG. 4C, with the darker colors indicating higher
heat loss. The high heat loss within the region 432 results in a
need for higher current to induce the desired phase change during
operation of the memory cell 400.
[0056] FIGS. 5-8 illustrate steps in a fabrication sequence in
accordance with an embodiment for manufacturing memory cells as
described herein. The following description does not repeat certain
explanations regarding materials, thicknesses, and the like, as set
out above.
[0057] FIG. 5 illustrates a cross-sectional view of a structure
formed as a first stage of the fabrication sequence, the structure
including a bottom electrode 500 extending from the top surface 312
of dielectric layer 310 to couple to access circuitry (not shown)
such as access transistors or diodes and word lines, etc. The
bottom electrode 500 has a diameter 331 which is preferably less
than a minimum feature size for a process, generally a lithographic
process, used to manufacture the access circuitry (not shown).
[0058] The bottom electrodes 500 having a sublithographic diameter
331 and the dielectric layer 310 can be formed, for example, using
methods, materials, and processes as disclosed in U.S. patent
application Ser. No. 11/764,678 filed on 18 Jun. 2007 entitled
"Method for Manufacturing a Phase Change Memory Device with Pillar
Bottom Electrode" (Attorney Docket Number 1791-2), which is
incorporated by reference herein. For example, a layer of electrode
material can be formed on the top surface of access circuitry (not
shown), followed by patterning of a layer of photoresist on the
electrode layer using standard photo lithographic techniques so as
to form a mask of photoresist overlying the locations of the bottom
electrode 500. Next the mask of photoresist is trimmed, using for
example oxygen plasma, to form mask structures having
sublithographic dimensions overlying the locations of the bottom
electrodes 500. Then the layer of electrode material is etched
using the trimmed mask of photoresist, thereby forming the bottom
electrodes 500 having sublithographic diameters 331. Next
dielectric material 310 is formed and planarized, resulting in the
structure illustrated in FIG. 5.
[0059] As another example, the bottom electrode 500 and dielectric
layer 310 can be formed using methods, materials, and processes as
disclosed in U.S. patent application Ser. No. 11/855,979 filed on
14 Sep. 2007 entitled "Phase Change Memory Cell in Via Array with
Self-Aligned, Self-Converged Bottom Electrode and Method for
Manufacturing" (Attorney Docket Number 1803-1), which is
incorporated by reference herein. For example, the dielectric layer
310 can be formed on the top surface of access circuitry followed
by sequentially forming an isolation layer and a sacrificial layer.
Next, a mask having openings close to or equal to the minimum
feature size of the process used to create the mask is formed on
the sacrificial layer, the openings overlying the locations of the
bottom electrode 500. The isolation layer and the sacrificial
layers are then selectively etched using the mask, thereby forming
vias in the isolation and sacrificial layers and exposing a top
surface of the dielectric layer 310. After removal of the mask, a
selective undercutting etch is performed on the vias such that the
isolation layer is etched while leaving the sacrificial layer and
the dielectric layer 310 intact. A fill material is then formed in
the vias, which due to the selective undercutting etch process
results in a self-aligned void in the fill material being formed
within each via. Next, an anisotropic etching process is performed
on the fill material to open the voids, and etching continues until
the dielectric layer 310 is exposed in the region below the void,
thereby forming a sidewall spacer comprising fill material within
each via. The sidewall spacers have an opening dimension
substantially determined by the dimensions of the void, and thus
can be less than the minimum feature size of a lithographic
process. Next, the dielectric layer 310 is etched using the
sidewall spacers as an etch mask, thereby forming openings in the
dielectric layer 310 having a diameter less than the minimum
feature size. Next, an electrode layer is formed within the
openings in the dielectric layer 144. A planarizing process, such
as chemical mechanical polishing CMP, is then performed to remove
the isolation layer and the sacrificial layer and to form the
bottom electrode 500, resulting in the structure illustrated in
FIG. 5.
[0060] Next, a portion of the bottom electrode 500 is etched from
the structure illustrated in FIG. 5, resulting in the structure
illustrated in FIG. 6 having a recess 600 above a bottom electrode
320.
[0061] Next, a phase change layer comprising a first phase change
material is formed in the recess 600 in FIG. 6 and planarized,
resulting in the structure illustrated in FIG. 7 having a first
phase change layer 330 on the bottom electrode 320.
[0062] Next a multi-layer structure is formed on the structure
illustrated in FIG. 8 comprising sequentially forming a layer of
resistive heater material, a layer of second phase change material,
and a layer top electrode material and patterning to form the
memory cell 300 illustrated in FIG. 9 having a resistive heater 305
comprising resistive heater material, a second phase change layer
335 comprising second phase change material, and a top electrode
340 comprising top electrode material.
[0063] FIG. 9 is a simplified block diagram of an integrated
circuit in accordance with an embodiment. The integrated circuit
1000 includes a memory array 1005 implemented using memory cells as
described herein having a heating center PCRAM structure. A row
decoder 1010 having read, set and reset modes is coupled to a
plurality of word lines 1015 arranged along rows in the memory
array 1005. A column decoder 1020 is coupled to a plurality of bit
lines 1025 arranged along columns in the memory array 1005 for
reading, setting and resetting memory cells in the memory array
1005. Addresses are supplied on bus 1060 to column decoder 1020 and
row decoder 1010. Sense amplifiers and data-in structures in block
1030, including current sources for the read, set and reset modes,
are coupled to the column decoder 1020 via data bus 1035. Data is
supplied via the data-in line 1040 from input/output ports on the
integrated circuit 1000 or from other data sources internal or
external to the integrated circuit 1000, to the data-in structures
in block 1030. In the illustrated embodiment, other circuitry 1065
is included on the integrated circuit 1000, such as a general
purpose processor or special purpose application circuitry, or a
combination of modules providing system-on-a-chip functionality
supported by the phase change memory cell array. Data is supplied
via the data-out line 1045 from the sense amplifiers in block 1030
to input/output ports on the integrated circuit 1000, or to other
data destinations internal or external to the integrated circuit
1000.
[0064] A controller implemented in this example using bias
arrangement state machine 1050 controls the application of bias
arrangement supply voltages and current sources 1055, such as read,
set, reset and verify voltages and or currents for the word lines
and bit lines, and controls the word line/source line operation
using an access control process. The controller can be implemented
using special-purpose logic circuitry as known in the art. In
alternative embodiments, the controller comprises a general-purpose
processor, which may be implemented on the same integrated circuit,
which executes a computer program to control the operations of the
device. In yet other embodiments, a combination of special-purpose
logic circuitry and a general-purpose processor may be utilized for
implementation of the controller.
[0065] FIG. 10 is a schematic illustration of a memory array 1100,
which can be implemented using memory cells as described herein.
Four memory cells 1102, 1104, 1106, and 1108 having respective
memory elements 1112, 1114, 1116, and 1118 each having respective
first and second phase change layers with a resistive heater
therebetween are illustrated in FIG. 11, representing a small
section of an array that can include millions of memory cells.
[0066] In the schematic illustration of FIG. 10, common source line
1120 and word lines 1122, 1124 are arranged generally parallel in
the y-direction. Bit lines 1126, 1128 are arranged generally
parallel in the x-direction. Thus, a y-decoder and a word line
driver 1150, having set, reset, and read modes, are coupled to the
word lines 1122, 1124. Bit line current sources 1152 for set,
reset, and read modes, a decoder and sense amplifiers (not shown)
are coupled to the bit lines 1126, 1128. The common source line
1120 is coupled to the source line termination circuit 1154, such
as a ground terminal. The source line termination circuit 1154 may
include bias circuits such as voltage sources and current sources,
and decoding circuits for applying bias arrangements, other than
ground, to the source lines in some embodiments.
[0067] The common source line 1120 is coupled to the source
terminals of memory cells 1102, 1104, 1106, and 1108. The word line
1122 is coupled to the gate terminals of memory cells 1102, 1106.
The word line 1124 is coupled to the gate terminals of memory cells
1104, 1108.
[0068] Memory cells 1102, 1104 including respective memory elements
1112, 1114 are representative. The memory element 1112 couples the
drain of memory cell 1102 to bit line 1126. Likewise, memory
element 1114 couples the drain of memory cell 1104 to bit line
1126. In operation, current sources 1152 operate in a lower current
read mode, one or more intermediate current set modes, and a higher
current reset mode. During the higher current reset mode, a current
path 1180 through the selected memory cell (e.g. memory cell 1102
including memory element 1112) is established by applying a voltage
and current to the bit line 1126, and voltages on the word line
1122 and source line 1120 sufficient to turn on the access
transistor to memory cell 1102, so that the current flows through
the source line 1120.
[0069] Likewise, during the lower current read mode, a current path
1182 through the selected memory cell (see the memory cell 1104
including memory element 1114) is established by applying a voltage
and current to the bit line 1126, and voltages on the word line
1124 and source line 1120 sufficient to turn on the access
transistor of memory cell 1104 and provide for current flow to the
source line 1120.
[0070] During set mode, used for one or more intermediate current
levels, an access transistor is enabled, as just described with
respect to the read mode.
[0071] Advantages described herein include memory cells having
reduced cell sizes, as well as a structure that addresses the heat
conductivity problem, providing an array architecture supporting
high-density devices, and a method for manufacturing such structure
that meets tight process variation specifications needed for
large-scale memory devices.
[0072] The invention has been described with reference to specific
exemplary embodiments. Various modifications, adaptations, and
changes may be made without departing from the spirit and scope of
the invention. Accordingly, the specification and drawings are to
be regarded as illustrative of the principles of this invention
rather than restrictive, the invention is defined by the following
appended claims.
[0073] Any and all patents, patent applications and printed
publications referred to above are incorporated by reference.
* * * * *