U.S. patent application number 12/015939 was filed with the patent office on 2009-07-23 for non-volatile memory and methods for fabricating the same.
This patent application is currently assigned to MACRONIX INTERNATIONAL CO., LTD.. Invention is credited to Ming-Chang Kuo.
Application Number | 20090186212 12/015939 |
Document ID | / |
Family ID | 40876713 |
Filed Date | 2009-07-23 |
United States Patent
Application |
20090186212 |
Kind Code |
A1 |
Kuo; Ming-Chang |
July 23, 2009 |
NON-VOLATILE MEMORY AND METHODS FOR FABRICATING THE SAME
Abstract
A non-volatile memory including a substrate, source/drain
regions, a first insulating layer, a charge storage layer, a second
insulating layer, and a conductive layer is provided. The
source/drain regions are respectively disposed in the substrate
apart from each other. The first insulating layer is disposed on
the substrate between the source/drain regions. The charge storage
layer is disposed on the first insulating layer. The second
insulating layer is disposed on the charge storage layer, and a
thickness of a peripheral region of the second insulating layer is
greater than a thickness of an internal region of the second
insulating layer. The conductive layer is disposed on the second
insulating layer.
Inventors: |
Kuo; Ming-Chang; (Hsinchu,
TW) |
Correspondence
Address: |
J C PATENTS, INC.
4 VENTURE, SUITE 250
IRVINE
CA
92618
US
|
Assignee: |
MACRONIX INTERNATIONAL CO.,
LTD.
Hsinchu
TW
|
Family ID: |
40876713 |
Appl. No.: |
12/015939 |
Filed: |
January 17, 2008 |
Current U.S.
Class: |
428/336 ;
427/96.1 |
Current CPC
Class: |
Y10T 428/265 20150115;
H01L 29/40117 20190801; H01L 29/792 20130101; H01L 29/513
20130101 |
Class at
Publication: |
428/336 ;
427/96.1 |
International
Class: |
G11B 5/62 20060101
G11B005/62; B05D 5/12 20060101 B05D005/12 |
Claims
1. A non-volatile memory, comprising: a substrate; a first
insulating layer disposed over the substrate and disposed between
two source/drain regions; a second insulationg layer provided with
a peripheral region and a internal region; a charge storage layer
disposed between the first insulating layer and the second
insulationg layer, wherein the peripheral region of the second
insulating layer is thicker than the internal region of the second
insulating layer; and a conductive layer disposed over the second
insulating layer.
2. The non-volatile memory as claimed in claim 1, wherein the
thickness of the internal region of the second insulating layer
ranges from 80 angstrom to 100 angstrom, while the thickness of the
peripheral region of the second insulating layer ranges from 90
angstrom to 120 angstrom.
3. The non-volatile memory as claimed in claim 1, wherein a
thickness of the first insulating layer ranges from 50 angstrom to
60 angstrom.
4. The non-volatile memory as claimed in claim 1, wherein a
thickness of the charge storage layer ranges from 60 angstrom to 80
angstrom.
5. The non-volatile memory as claimed in claim 1, wherein the first
insulating layer is a oxide layer that comprising silicon
oxide.
6. The non-volatile memory as claimed in claim 1, wherein the
charge storage layer is a dielectric material.
7. The non-volatile memory as claimed in claim 6, wherein the
dielectric material providing charge trapping ability.
8. The non-volatile memory as claimed in claim 6, wherein the
dielectric material is nitride material that comprising silicon
nitride.
9. The non-volatile memory as claimed in claim 1, wherein the
second insulating layer is a oxide layer that comprising silicon
oxide.
10. A method for fabricating a non-volatile memory, the method
comprising: providing a substrate; forming a first insulating layer
over the substrate and disposed between two source/drain regions;
providing a second insulationg layer having a peripheral region and
a internal region; forming a charge storage layer between the first
insulating layer and the second insulationg layer, wherein the
peripheral region of the second insulating layer is thicker than
the internal region of the second insulating layer; and forming a
conductive layer over the second insulating layer.
11. The method for fabricating the non-volatile memory as claimed
in claim 10, wherein the thickness of the internal region of the
second insulating layer ranges from 80 angstrom to 100 angstrom,
while the thickness of the peripheral region of the second
insulating layer ranges from 90 angstrom to 120 angstrom.
12. The method for fabricating the non-volatile memory as claimed
in claim 10, wherein a thickness of the first insulating layer
ranges from 50 angstrom to 60 angstrom.
13. The method for fabricating the non-volatile memory as claimed
in claim 10, wherein a thickness of the charge storage layer ranges
from 60 angstrom to 80 angstrom.
14. The method for fabricating the non-volatile memory as claimed
in claim 10, wherein the charge storage layer is a dielectric
material and the dielectric material providing charge trapping
ability.
15. The method for fabricating the non-volatile memory as claimed
in claim 14, wherein the dielectric material is nitride material
that comprising silicon nitride.
16. A method for fabricating a non-volatile memory, the method
comprising: forming a stacked structure and a cosuming layer in
sequence over a substrate; performing a converting process at a
peripheral region of the consuming layer to form a first insulating
layer; removing the consuming layer; and forming a conductive layer
over the stacked layer and the first insulating layer.
17. The method for fabricating the non-volatile memory as claimed
in claim 16, wherein the stacked structure comprises a second
insulating layer, a charge storage layer, and a third insulating
layer formed in sequence over the substrate.
18. The method for fabricating the non-volatile memory as claimed
in claim 17, wherein a thickness of the third insulating layer
ranges from 80 angstrom to 100 angstrom, while a thickness of the
first insulating layer ranges from 10 angstrom to 20 angstrom.
19. The method for fabricating the non-volatile memory as claimed
in claim 17, wherein a thickness of the second insulating layer
ranges from 50 angstrom to 60 angstrom.
20. The method for fabricating the non-volatile memory as claimed
in claim 17, wherein a thickness of the charge storage layer ranges
from 60 angstrom to 80 angstrom.
21. The method for fabricating the non-volatile memory as claimed
in claim 17, wherein the charge storage layer is a dielectric
material and the dielectric material providing charge trapping
ability.
22. The method for fabricating the non-volatile memory as claimed
in claim 17, wherein the dielectric material is nitride material
that comprising silicon nitride.
23. The method for fabricating the non-volatile memory as claimed
in claim 16, wherein the converting process is an oxidation
process.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a structure of an
integrated circuit (IC) and methods for fabricating the same. More
particularly, the present invention relates to a structure of a
non-volatile memory and methods for fabricating the same.
[0003] 2. Description of Related Art
[0004] A non-volatile memory is characterized by maintaining stored
data even when the power is off, and thus has become a mandatory
device in many electronic products for providing normal operation
when the electronic products are booted. Recently, the non-volatile
memory has been widely adopted in personal computers (PCs) and
other electronic equipment.
[0005] FIG. 1 is a schematic cross-sectional view of a conventional
non-volatile memory. Referring to FIG. 1, the non-volatile memory
includes a substrate 100, a source region 102a and a drain region
102b disposed in the substrate 100, and a gate stacked structure
112. The gate stacked structure 112 is constituted by a silicon
oxide layer 104, a silicon nitride layer 106, another silicon oxide
layer 108, and a gate 110 all having a uniform thickness. In the
conventional non-volatile memory, one bit is respectively stored in
the silicon nitride layer 106 around the source region 102a and the
drain region 102b, such that a two-bit/cell memory is formed.
[0006] However, when programming the conventional two-bit/cell
non-volatile memory, the two bits in the same memory cell are
mutually affected. If one bit has been stored in a part near the
drain region in the conventional non-volatile memory, a second-bit
effect occurs when a reading operation is performed, such that a
voltage in the portion where a high current is expected may drop.
In other words, when the memory cell is being read, the existing
bit poses a direct impact on the memory cell, thus increasing a
barrier and a threshold voltage (Vt) for reading.
[0007] In view of the above, the second-bit effect not only
substantially implicates the operation of devices, but also reduces
the device reliability. Moreover, because the second-bit effect
reduces a sense margin and a Vt window for operating the left bit
and the right bit, thus an operation of multi-level cell memory is
more difficult.
[0008] One of the current solutions is directed to increasing a
drain voltage (Vd) for enhancing a drain-induced barrier lowering
(DIBL), and thereby the increased barrier and the increased Vt
arisen from the second-bit effect can be decreased. Nevertheless,
since a dimension of the device is continuously shrinking, an
excessive drain voltage will result in the operation difficulties
as well.
SUMMARY OF THE INVENTION
[0009] In light of the foregoing, the present invention is directed
to a non-volatile memory capable of reducing a second-bit effect
and resolving problems derived therefrom.
[0010] The present invention is further directed to several methods
for fabricating a non-volatile memory capable of preventing cross
interference of two bits in a memory cell of the non-volatile
memory, such that the reliability of a memory device is
enhanced.
[0011] The present invention provides a non-volatile memory
including a substrate, a first insulating layer, a charge storage
layer, a second insulating layer, and a conductive layer. The first
insulating layer is disposed over the substrate and disposed
between the source/drain regions. The second insulationg layer is
provided with a peripheral region and an internal region. The
charge storage layer is disposed between the first insulating layer
and the second insulating layer. And, the peripheral region of the
second insulating layer is thicker than the internal region of the
second insulating layer. The conductive layer is disposed on the
second insulating layer.
[0012] According to an embodiment of the present invention, the
thickness of the internal region of the second insulating layer
ranges from 80 angstrom to 100 angstrom, while the thickness of the
peripheral region of the second insulating layer ranges from 90
angstrom to 120 angstrom. A thickness of the first insulating layer
ranges from 50 angstrom to 60 angstrom. A thickness of the charge
storage layer ranges from 60 angstrom to 80 angstrom.
[0013] According to an embodiment of the present invention, the
first insulating layer is a oxide layer that comprising silicon
oxide. The charge storage layer is a dielectric material provides
charge trapping ability and the dielectric material is nitride
material that comprising silicon nitride. The second insulating
layer is a oxide layer that comprising silicon oxide.
[0014] The present invention further provides a method for
fabricating a non-volatile memory. The method includes providing a
substrate at first. A first insulating layer is formed over the
substrate and disposed between two source/drain regions. A second
insulationg layer is provided with a peripheral region and a
internal region. A charge storage layer is formed between the first
insulating layer and the second insulationg layer. The peripheral
region of the second insulating layer is thicker than the internal
region of the second insulating layer. A conductive layer is formed
over the second insulating layer.
[0015] According to another embodiment of the present invention,
the thickness of the internal region of the second insulating layer
ranges from 80 angstrom to 100 angstrom, while the thickness of the
peripheral region of the second insulating layer ranges from 90
angstrom to 120 angstrom. A thickness of the first insulating layer
ranges from 50 angstrom to 60 angstrome. A thickness of the charge
storage layer ranges from 60 angstrom to 80 angstrom.
[0016] According to an embodiment of the present invention, the
first insulating layer is a oxide layer that comprising silicon
oxide. The charge storage layer is a dielectric material provides
charge trapping ability and the dielectric material is nitride
material that comprising silicon nitride. The second insulating
layer is a oxide layer that comprising silicon oxide.
[0017] The present invention further provides a method for
fabricating a non-volatile memory. The method includes forming a
stacked structure and a cosuming layer in sequence over a substrate
at first. A converting process is performed at a peripheral region
of the consuming layer to form a first insulating layer. The
consuming layer is removed. A conductive layer is formed over the
stacked layer and the first insulating layer.
[0018] According to another embodiment of the present invention,
the stacked structure comprises a second insulating layer, a charge
storage layer, and a third insulating layer formed in sequence over
the substrate. A thickness of the third insulating layer ranges
from 80 angstrom to 100 angstrom, while a thickness of the first
insulating layer ranges from 10 angstrom to 20 angstrom. A
thickness of the second insulating layer ranges from 50 angstrom to
60 angstrom. A thickness of the charge storage layer ranges from 60
angstrom to 80 angstrom.
[0019] According to another embodiment of the present invention,
the second insulating layer is a oxide layer that comprising
silicon oxide. The charge storage layer is a dielectric material
provides charge trapping ability and the dielectric material is
nitride material that comprising silicon nitride. The third
insulating layers is a oxide layer that comprising silicon
oxide.
[0020] According to another embodiment of the present invention,
the first insulating layers is a oxide layer that comprising
silicon oxide.
[0021] According to another embodiment of the present invention,
the consuming layer is a polysilicon layer.
[0022] According to another embodiment of the present invention,
the converting process is an oxidation process.
[0023] The present invention further provides a method for
fabricating a non-volatile memory. The method includes forming a
stacked structure and a cosuming layer in sequence over a substrate
at first. A converting process is performed at a peripheral region
of the consuming layer to form a first insulating layer. The
cosuming layer is removed. A second insulating layer is conformally
formed on the stacked structure and the first insulating layer. A
conductive layer is formed on the second insulating layer.
[0024] According to another embodiment of the present invention, a
thickness of the first insulating layer ranges from 10 angstrom to
20 angstrom, while a thickness of the second insulating layer
ranges from 80 angstrom to 100 angstrom.
[0025] According to another embodiment of the present invention,
the stacked structure comprises a third insulating layer and a
charge storage layer formed in sequence over the substrate. A
thickness of the third insulating layer ranges from 50 angstrom to
60 angstrom. A thickness of the charge storage layer ranges from 60
angstrom to 80 angstrom. The third insulating layer is a oxide
layer that comprising silicon oxide. The charge storage layer is a
dielectric material provides charge trapping ability, and the
dielectric material is nitride material that comprising silicon
nitride.
[0026] According to another embodiment of the present invention,
the first insulating layer is a oxide layer that comprising silicon
oxide and the second insulating layers is a oxide layer that
comprising silicon oxide.
[0027] According to another embodiment of the present invention,
the consuming layer is a polysilicon layer.
[0028] According to another embodiment of the present invention,
the converting process is an oxidation process.
[0029] In the present invention, the stacked structure comprising
the insulating layer/the charge storage layer/the insulating layer
is disposed between the conductive layer and the substrate. The
insulating layer disposed between the conductive layer and the
dielectric layer has a greater thickness of the peripheral region
than the thickness of the internal region of the insulating layer.
Accordingly, the thickness of the peripheral region of the
insulating layer results in a greater DIBL, which effectively
reduces the second-bit effect. On the other hand, the non-volatile
memory of the present invention can be further applied to a
multi-bit memory device.
[0030] In order to make the above and other objects, features and
advantages of the present invention more comprehensible, several
embodiments accompanied with figures are described in detail
below.
BRIEF DESCRIPTION OF THE DRAWINGS
[0031] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention.
[0032] FIG. 1 is a schematic cross-sectional view of a conventional
non-volatile memory.
[0033] FIG. 2 is a schematic cross-sectional view of a non-volatile
memory according to an embodiment of the present invention.
[0034] FIGS. 3A and 3B are schematic views illustrating a
programming operation of a right bit and a left bit of a memory
cell of the non-volatile memory according to the present
invention.
[0035] FIGS. 4A and 4B are schematic views illustrating an erasing
operation of the right bit and the left bit of the memory cell of
the non-volatile memory according to the present invention.
[0036] FIGS. 5A and 5B are schematic views illustrating a reading
operation of the right bit and the left bit of the memory cell of
the non-volatile memory according to the present invention.
[0037] FIGS. 6A through 6F are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a first
embodiment of the present invention.
[0038] FIGS. 7A through 7G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a
second embodiment of the present invention.
[0039] FIGS. 8A through 8G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a third
embodiment of the present invention.
[0040] FIGS. 9A through 9G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a
fourth embodiment of the present invention.
DESCRIPTION OF EMBODIMENTS
[0041] FIG. 2 is a schematic cross-sectional view of a non-volatile
memory according to an embodiment of the present invention.
[0042] Referring to FIG. 2, the non-volatile memory includes a
substrate 200, source/drain regions 202a and 202b, an insulating
layer 204, a charge storage layer 206, another insulating layer
208, and a conductive layer 210. The substrate 200 is, for example,
a silicon substrate or any other appropriate semiconductor
substrates. The source/drain regions 202a and 202b are respectively
disposed in the substrate 200 apart from each other.
[0043] The insulating layer 204 of the non-volatile memory is
disposed on the substrate 200 between the source/drain regions 202a
and 202b. The insulating layer 204 is a oxide layer which a
material of that is, for example, silicon oxide, and a thickness of
the insulating layer 204, for example, ranges from 50 angstrom to
60 angstrom, and is preferably about 54 angstrom. The charge
storage layer 206 is disposed on the insulating layer 204. Here,
the charge storage layer 206 is a dielectric material provides
charge trapping ability, and the dielectric material is nitride
material which is silicon nitride, for example. A thickness of the
charge storage layer 206, for example, ranges from 60 angstrom to
80 angstrom, and is preferably about 70 angstrom. The insulating
layer 208 is disposed on the charge storage layer 206, and the
insulating layer 208 is a oxide layer which a material of that is
silicon oxide, for example. The conductive layer 210 is disposed on
the insulating layer 208, and a material of the conductive layer
210 is polysilicon, for example. Here, the conductive layer 210
serves as a gate of the non-volatile memory.
[0044] Note that the difference between the non-volatile memory
proposed in the present embodiment and the conventional
non-volatile memory lies in that the insulating layer 208 of the
non-volatile memory in the present embodiment is not in a uniform
thickness. The thickness of the peripheral region (regions 207a
surrounded by dotted lines in FIG. 2) of the insulating layer 208
is greater than the thickness of the internal region (a region
labeled as 207b in FIG. 2) of the insulating layer 208. Here, the
thickness of the internal region 207b of the insulating layer 208,
for example, ranges from 80 angstrom to 100 angstrom, and is
preferably about 90 angstrom. By contrast, the thickness of the
peripheral region 207a of the insulating layer 208 ranges from 90
angstrom to 120 angstrom, for example.
[0045] It should be noted that since the non-uniform insulating
layer 208 has the greater thickness of the peripheral region 207a
than at the internal region 207b, a Vt of the non-volatile memory
is affected by the thickness of the insulating layer 208 above the
charge storage layer 206, resulting in a relatively significant
DIBL. Thereby, the second-bit effect is reduced, and a Vt window is
increased as well.
[0046] The non-volatile memory depicted in FIG. 2 is taken to
elaborate a progranming operation of the non-volatile memory of the
present invention, an erasing operation thereof, and a reading
operation thereof.
[0047] Please refer to FIGS. 3A and 3B which are schematic views
illustrating the programming operation of a right bit and a left
bit of a memory cell of the non-volatile memory according to the
present invention. As shown in FIG. 3A, when the programming
operation of the right bit is performed, a voltage Vg is applied to
the conductive layer 210, a voltage Va is applied to the
source/drain region 202a, and a voltage Vb is applied to the
source/drain region 202b. Here, the voltage Vg ranges from 5 V to
10 V, the voltage Va is 0 V, and the voltage Vb ranges from 4 V to
6 V, for example. Said programming operation is performed by
injecting channel hot electrons (CHEs). In addition, as indicated
in FIG. 3B, when the programming operation of the left bit is
performed, the voltage Vg is applied to the conductive layer 210,
the voltage Va is applied to the source/drain region 202a, and the
voltage Vb is applied to the source/drain region 202b. Here, the
voltage Vg ranges from 5 V to 10 V, the voltage Va ranges from 4 V
to 6 V, and the voltage Vb is 0 V, for example. Said programming
operation is performed by injecting the CHEs as well.
[0048] Please refer to FIGS. 4A and 4B which are schematic views
illustrating the erasing operation of the right bit and the left
bit of the memory cell of the non-volatile memory according to the
present invention. As shown in FIG. 4A, when the erasing operation
of the right bit is performed, the voltage Vg is applied to the
conductive layer 210, the voltage Va is applied to the source/drain
region 202a, and the voltage Vb is applied to the source/drain
region 202b. Here, the voltage Vg ranges from -10 V to -5 V, the
voltage Va is 0 V, and the voltage Vb ranges from 4 V to 6 V, for
example. Said erasing operation is performed through a band to band
hot hole (BTBHH) effect. In addition, as indicated in FIG. 4B, when
the erasing operation of the left bit is performed, the voltage Vg
is applied to the conductive layer 210, the voltage Va is applied
to the source/drain region 202a, and the voltage Vb is applied to
the source/drain region 202b. Here, the voltage Vg ranges from -10
V to -5 V, the voltage Va ranges from 4 V to 6 V, and the voltage
Vb is 0 V, for example. Said erasing operation is performed through
the BTBHH effect as well.
[0049] Please refer to FIGS. 5A and 5B which are schematic views
illustrating the reading operation of the right bit and the left
bit of the memory cell of the non-volatile memory according to the
present invention. As shown in FIG. 5A, when the reading operation
of the right bit is performed, the voltage Vg is applied to the
conductive layer 210, the voltage Va is applied to the source/drain
region 202a, and the voltage Vb is applied to the source/drain
region 202b. Here, the voltage Vg ranges from 3 V to 5 V, the
voltage Va ranges from 1 V to 1.8 V, and the voltage Vb is 0 V, for
example. In addition, as indicated in FIG. 5B, when the reading
operation of the left bit is performed, the voltage Vg is applied
to the conductive layer 210, the voltage Va is applied to the
source/drain region 202a, and the voltage Vb is applied to the
source/drain region 202b. Here, the voltage Vg ranges from 3 V to 5
V, the voltage Vb ranges from 1 V to 1.8 V, and the voltage Va is 0
V, for example.
[0050] Next, several embodiments are enumerated hereinafter for
elaborating methods for fabricating the non-volatile memory of the
present invention.
First Embodiment
[0051] FIGS. 6A through 6F are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a first
embodiment of the present invention.
[0052] First, as shown in FIG. 6A, a substrate 600 is provided. The
substrate 600 is, for example, a silicon substrate or any other
appropriate semiconductor substrates. Next, an insulating layer 602
is formed on the substrate 600. The insulating layer 602 is a oxide
layer which a material of that is, for example, silicon oxide, and
the insulating layer 602 is formed by performing a chemical vapor
deposition (CVD) process, for example. A thickness of the
insulating layer 602, for example, ranges from 50 angstrom to 60
angstrom, and is preferably about 54 angstrom. Next, a charge
storage layer 604 is formed on the insulating layer 602. The charge
storage layer 604 is a dielectric material provides charge trapping
ability, and the dielectric material is nitride material which is
silicon nitride, for example. The charge storage layer 604 is
formed by performing the CVD process, for example. A thickness of
the charge storage layer 604, for example, ranges from 60 angstrom
to 80 angstrom, and is preferably about 70 angstrom. Thereafter,
another insulating layer 606 is formed on the charge storage layer
604. A material of the insulating layer 606 is, for example,
silicon oxide, and the insulating layer 606 is formed by performing
the CVD process, for example. A thickness of the insulating layer
606, for example, ranges from 80 angstrom to 100 angstrom, and is
preferably about 90 angstrom.
[0053] Thereafter, referring to FIG. 6A, a consuming layer 608 is
formed on the insulating layer 606 by performing the CVD process,
for example. The consuming layer 608 is a polysilicon layer, for
example. After that, a mask layer 610 is formed on the consuming
layer 608. A material of the mask layer 610 is, for example,
silicon nitride, and a method for forming the mask layer 610
includes carrying out the CVD process, for example.
[0054] Next, referring to FIG. 6B, a patterning process is
performed on the mask layer 610, the consuming layer 608, the
insulating layer 606, the dielectric layer 604, and the insulating
layer 602, so as to form a stacked structure 611.
[0055] Afterwards, referring to FIG. 6C, an isolation layer 612 is
formed on the substrate 600 atthe sides ofthe stacked structure
611. Here, amaterial of the isolation layer 612 is silicon oxide,
for example. Thereafter, two source/drain regions 614 are formed in
the substrate 600 below the isolation layer 612. The source/drain
regions 614 are formed by performing an ion implantation process,
for example.
[0056] Next, referring to FIG. 6D, a portion of the mask layer 610
is removed, so as to cover an internal region 615 of the consuming
layer 608 and expose surfaces of a peripheral region 616 of the
consuming layer 608. The portion of the mask layer 610 is removed
by performing an etching process, for example.
[0057] After that, referring to FIG. 6E, a converting process which
is, for example, an oxidation process is carried out, such that the
consuming layer 608 of the peripheral region 616 is oxidized, and
an insulating layer 618 is then formed. A thickness of the
insulating layer 618 ranges from 10 angstrom to 20 angstrom, for
example. Here, the insulating layers 606 and 618 serve as an upper
insulating layer above the dielectric layer 604. After the
formation of the insulating layer 618, one etching process is then
carried out to remove the mask layer 610 and the polysilicon layer
608 disposed below the mask layer 610.
[0058] Thereafter, referring to FIG. 6F, a conductive layer 620 is
formed on the insulating layers 606 and 618. A material of the
conductive layer 620 is polysilicon, for example, and the
conductive layer 620 is formed by performing the CVD process, for
example. The fabrication of the non-volatile memory is then
completed.
Second Embodiment
[0059] FIGS. 7A through 7G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a
second embodiment of the present invention.
[0060] First, as shown in FIG. 7A, a substrate 700 is provided. The
substrate 700 is, for example, a silicon substrate or any other
appropriate semiconductor substrates. Next, an insulating layer 702
is formed on the substrate 700. The insulating layer 702 is a oxide
layer which a material of that is, for example, silicon oxide, and
the insulating layer 702 is formed by performing the CVD process,
for example. A thickness of the insulating layer 702, for example,
ranges from 50 angstrom to 60 angstrom, and is preferably about 54
angstrom.
[0061] Thereafter, referring to FIG. 7A, a charge storage layer 704
is formed on the insulating layer 702. The charge storage layer 704
is a dielectric material provides charge trapping ability, and the
dielectric material is nitride material which is silicon nitride,
for example. The charge storage layer 704 is formed by performing
the CVD process, for example. A thickness of the charge storage
layer 704, for example, ranges from 60 angstrom to 80 angstrom, and
is preferably about 70 angstrom. Afterwards, a consuming layer 706
is formed on the charge storage layer 704 by performing the CVD
process, for example. The consuming layer is a polysilicon layer,
for example. After that, a mask layer 708 is formed on the
consuming layer 706. A material of the mask layer 708 is, for
example, silicon nitride, and a method for forming the mask layer
708 includes carrying out the CVD process, for example.
[0062] Next, referring to FIG. 7B, the patterning process is
performed on the mask layer 708, the consuming layer 706, the
charge storage layer 704, and the insulating layer 702, so as to
form a stacked structure 709.
[0063] Afterwards, referring to FIG. 7C, an isolation layer 710 is
formed on the substrate 700 at the sides of the stacked structure
709. Here, a material of the isolation layer 710 is silicon oxide,
for example. Thereafter, two source/drain regions 712 are formed in
the substrate 700 below the isolation layer 710. The source/drain
regions 712 are formed by performing the ion implantation process,
for example.
[0064] Next, referring to FIG. 7D, a portion of the mask layer 708
is removed, so as to cover an internal region 715 of the consuming
layer 706 and expose surfaces of a peripheral region 714 of the
consuming layer 706. The portion of the mask layer 708 is removed
by performing the etching process, for example.
[0065] After that, referring to FIG. 7E, a converting process which
is, for example, an oxidation process is carried out, such that the
consuming layer 706 of the peripheral region 714 is oxidized, and
an insulating layer 716 is then formed. A thickness of the
insulating layer 716 ranges from 10 angstrom to 20 angstrom, for
example. Next, the etching process is performed to remove the mask
layer 708 and the consuming layer 706 disposed below the mask layer
708.
[0066] Thereafter, referring to FIG. 7F, another insulating layer
718 is conformally formed above the insulating layer 716 and the
charge storage layer 704. The insulating layer 718 is a oxide layer
which a material of that is, for example, silicon oxide, and the
insulating layer 718 is formed by performing the CVD process, for
example. A thickness of the insulating layer 718, for example,
ranges from 80 angstrom to 100 angstrom, and is preferably about 90
angstrom. Here, the insulating layers 716 and 718 serve as the
upper insulating layer above the charge storage layer 704.
[0067] After that, referring to FIG. 7G, a conductive layer 720 is
formed on the insulating layer 718. A material of the conductive
layer 720 is polysilicon, for example,. and the conductive layer
720 is formed by performing the CVD process, for example. The
fabrication of the non-volatile memory is then completed.
Third Embodiment
[0068] FIGS. 8A through 8G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a third
embodiment of the present invention.
[0069] First, as shown in FIG. 8A, a substrate 800 is provided. The
substrate 800 is, for example, a silicon substrate or any other
appropriate semiconductor substrates. Next, an insulating layer 802
is formed on the substrate 800. The insulating layer 802 is a oxide
layer which a material of that is, for example, silicon oxide, and
the insulating layer 802 is formed by performing the CVD process,
for example. A thickness of the insulating layer 802, for example,
ranges from 50 angstrom to 60 angstrom, and is preferably about 54
angstrom.
[0070] Thereafter, referring to FIG. 8A, a charge storage layer 804
is formed on the insulating layer 802. The charge storage layer 804
is a dielectric material provides charge trapping ability, and the
dielectric material is nitride material which is silicon nitride,
for example. The charge storage layer 804 is formed by performing
the CVD process, for example. Athickness of the charge storage
layer 804, for example, ranges from 60 angstrom to 80 angstrom, and
is preferably abour 70 angstrom. Thereafter, another insulating
layer 806 is formed on the charge storage layer 804. The insulating
layer 806 is a oxide layer which a material of that is, for
example, silicon oxide, and the insulating layer 806 is formed by
performing the CVD process, for example. A thickness of the
insulating layer 806, for example, ranges from 80 angstrom to 100
angstrom, and is preferably about 90 angstrom. After that, a mask
layer 808 is formed on the insulating layer 806. A material of the
mask layer 808 is, for example, silicon nitride, and a method for
forming the mask layer 808 includes carrying out the CVD process,
for example.
[0071] Next, referring to FIG. 8B, the patterning process is
performed on the mask layer 808, the insulating layer 806, the
charge storage layer 804, and the insulating layer 602, so as to
form a stacked structure 809.
[0072] Afterwards, referring to FIG. 8C, an isolation layer 810 is
formed on the substrate 800 at the sides of the stacked structure
809. Here, a material of the isolation layer 810 is silicon oxide,
for example. Thereafter, two source/drain regions 812 are formed in
the substrate 800 below the isolation layer 810. The source/drain
regions 812 are formed by performing the ion implantation process,
for example.
[0073] Afterwards, referring to FIG. 8D, a portion of the mask
layer 808 is removed, so as to cover a internal region 815 of the
second insulating layer 806 and expose surfaces of a peripheral
region 814 of the insulating layer 806. The portion of the mask
layer 808 are removed by performing the etching process, for
example.
[0074] Next, referring to FIG. 8E, another insulating layer 816 is
formed above the mask layer 808 and the peripheral region 814 of
the insulating layer 806. A material of the insulating layer 816
is, for example, silicon oxide, and the insulating layer 816 is
formed by performing the CVD process, for example.
[0075] After that, referring to FIG. 8F, a portion of the
insulating layer 816 is removed, such that an insulating layer 818
remains. The insulating layer 818 covers the side regions 814 ofthe
insulating layer 806. A thickness ofthe insulating layer 818 ranges
from 10 angstrom to 20 angstrom, for example. Here, the insulating
layers 806 and 818 serve as the upper insulating layer above the
charge storage layer 804. After the formation of the insulating
layer 818, the etching process is performed to remove the mask
layer 808.
[0076] Thereafter, referring to FIG. 8G, a conductive layer 820 is
formed on the insulating layers 806 and 818. A material of the
conductive layer 820 is polysilicon, for example, and the
conductive layer 820 is formed by performing the CVD process, for
example. The fabrication of the non-volatile memory is then
completed.
Fourth Embodiment
[0077] FIGS. 9A through 9G are cross-sectional views illustrating a
process of fabricating the non-volatile memory according to a
fourth embodiment of the present invention.
[0078] First, as shown in FIG. 9A, a substrate 900 is provided. The
substrate 900 is, for example, a silicon substrate or any other
appropriate semiconductor substrates. Next, an insulating layer 902
is formed on the substrate 900. The insulating layer 902 is a oxide
layer which material of that is, for example, silicon oxide, and
the insulating layer 902 is formed by performing the CVD process,
for example. A thickness of the insulating layer 902, for example,
ranges from 50 angstrom to 60 angstrom, and is preferably about 54
angstrom. Next, a charge storage layer 904 is formed on the
insulating layer 902. The charge storage layer 904 is a dielectric
material provides charge trapping ability, and the dielectric
material is nitride material which is silicon nitride, for example.
The charge storage layer 904 is formed by performing the CVD
process, for example. A thickness of the charge storage layer 904,
for example, ranges from 60 angstrom to 80 angstrom, and is
preferably about 70 angstrom. Thereafter, another insulating layer
906 is formed on the charge storage layer 904. The insulating layer
906 is a oxide layer which a material of that is, for example,
silicon oxide, and the insulating layer 906 is formed by performing
the CVD process, for example. A thickness of the insulating layer
906, for example, ranges from 80 angstrom to 100 angstrom, and is
preferably about 90 angstrom.
[0079] Thereafter, referring to FIG. 9A, a consuming layer 908 is
formed on the insulating layer 906 by performing the CVD process,
for example. The consuming layer is a polysilicon layer, for
example. After that, a mask layer 910 is formed on the consuming
layer 908. A material of the mask layer 910 is, for example,
silicon nitride, and a method for forming the mask layer 910
includes carrying out the CVD process, for example.
[0080] Next, referring to FIG. 9B, the patterning process is
performed on the mask layer 910, the consuming layer 908, the
insulating layer 906, the charge storage layer 904, and the
insulating layer 902, so as to form a stacked structure 911.
[0081] Next, referring to FIG. 9C, a portion of the mask layer 910
is removed, so as to cover a intemal region 913 of the consuming
layer 908 and expose surfaces of a peripheral region 912 of the
consuming layer 908. The portion of the mask layer 910 is removed
by performing the etching process, for example.
[0082] As illustrated in FIG. 9D, the converting process which is,
for example, an oxidation process is then performed, such that the
consuming layer 908 of the peripheral region 912 is oxidized for
forming an insulating layer 914. Another insulating layer 916 is
also formed on a surface of the substrate 900 at the sides of the
stacked structure 911.
[0083] Afterwards, referring to FIG. 9E, two source/drain regions
918 are formed in the substrate 900 below the insulating layer 916.
The source/drain regions 918 are formed by performing the ion
implantation process, for example. Next, another insulating layer
920 is conformally formed above the mask layer 910, the insulating
layer 914, and the insulating layer 916. The insulating layer 920
is a oxide layer which a material of that is, for example, silicon
oxide, and the insulating layer 920 is formed by performing the CVD
process, for example.
[0084] After that, referring to FIG. 9F, a portion of the
insulating layer 920 is removed, such that an insulating layer 922
remains. The insulating layer 922 and the insulating layer 914
together construct another insulating layer 924. A thickness of the
insulating layer 924 ranges from 10 angstrom to 20 angstrom, for
example. Here, the insulating layers 906 and 924 serve as the upper
insulating layer above the charge storage layer 904. On the other
hand, the insulating layers 922 and 916 together form a so-called
isolation layer 926. Next, the mask layer 910 is removed.
[0085] Thereafter, referring to FIG. 9G, a conductive layer 928 is
formed on the insulating layer 924 and the consuming layer 908. A
material of the conductive layer 928 is polysilicon, for example,
and the conductive layer 928 is formed by performing the CVD
process, for example. The fabrication of the non-volatile memory is
then completed.
[0086] To sum up, in the present invention, the stacked structure
comprising the insulating layer/the charge storage layer/the
insulating layer is disposed between the conductive layer and the
substrate. The insulating layer disposed between the conductive
layer and the charge storage layer has a greater thickness of the
peripheral region than the thickness of the internal region of the
insulating layer. Accordingly, the thickness of the peripheral
region of the insulating layer results in a greater DIBL, which
effectively reduces the second-bit effect and resolves the problems
derived therefrom. Moreover, the device reliability and the Vt
window for operating the left bit and the right bit are increased.
Furthermore, the non-volatile memory of the present invention can
be applied to a multi-bit memory device as well.
[0087] The present invention has been disclosed above in the
preferred embodiments, but is not limited to those. It is known to
persons skilled in the art that some modifications and innovations
may be made without departing from the spirit and scope of the
present invention. Therefore, the scope of the present invention
should be defined by the following claims.
* * * * *