U.S. patent application number 12/347618 was filed with the patent office on 2009-07-16 for wide dynamic range pinned photodiode active pixel sensor (aps).
Invention is credited to Junichi Nakamura.
Application Number | 20090180015 12/347618 |
Document ID | / |
Family ID | 32297028 |
Filed Date | 2009-07-16 |
United States Patent
Application |
20090180015 |
Kind Code |
A1 |
Nakamura; Junichi |
July 16, 2009 |
WIDE DYNAMIC RANGE PINNED PHOTODIODE ACTIVE PIXEL SENSOR (APS)
Abstract
An image apparatus and method is disclosed for extending the
dynamic range of an image sensor. A first linear pixel circuit
produces a first pixel output signal based on charge integration by
a first photo-conversion device over a first integration period. A
second linear pixel circuit produces a second pixel output signal
based on charge integration by a second photo-conversion device
over a second integration period, where the second integration
period is shorter than the first integration period. A
sample-and-hold circuit captures signals representing the first and
second pixel output signals.
Inventors: |
Nakamura; Junichi; (Tokyo,
JP) |
Correspondence
Address: |
DICKSTEIN SHAPIRO LLP
1825 EYE STREET NW
Washington
DC
20006-5403
US
|
Family ID: |
32297028 |
Appl. No.: |
12/347618 |
Filed: |
December 31, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10294686 |
Nov 15, 2002 |
7489352 |
|
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12347618 |
|
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Current U.S.
Class: |
348/308 ;
348/E5.091 |
Current CPC
Class: |
H04N 5/35563 20130101;
H04N 5/35554 20130101; H04N 5/37457 20130101 |
Class at
Publication: |
348/308 ;
348/E05.091 |
International
Class: |
H04N 5/335 20060101
H04N005/335 |
Claims
1. An imaging apparatus, comprising: a first pixel circuit,
comprising a first transfer pulse line, coupled to a gate of a
first transfer transistor, wherein first transfer transistor
transfers charge from a first photodiode to a first floating
diffusion node, and wherein said first floating diffusion node is
further coupled to a gate of a first source-follower transistor; a
second pixel circuit, comprising a second transfer pulse line,
coupled to a gate of a second transfer transistor, wherein second
transfer transistor transfers integrated charge from a second
photodiode and to a second floating diffusion node, and wherein
said second floating diffusion node is further coupled to a gate of
a second source-follower transistor; a reset pulse line, connected
to the gate of a first and second reset transistor, wherein the
first reset transistor is coupled to reset the first floating
diffusion node to a predetermined voltage state, and the second
reset transistor is coupled to reset the second floating diffusion
node to a predetermined voltage state; and a first and second
row-select transistor, respectively coupled to the first and second
source-follower transistors for respectively coupling said first
and second source follower transistors to a first column signal
line and a second column signal line, said first transfer pulse
line receiving a signal which operates said first photodiode to
integrate charge for a first time period and said second transfer
pulse line receiving a signal which operates said second photodiode
to integrate charge for a second time period different from said
first time period.
2. The apparatus according to claims 1, wherein the first and
second photodiodes are pinned photodiodes.
3. The apparatus according to claim 2, wherein the pinned
photodiodes are coupled to ground.
4. The apparatus according to claim 1, further comprising a first
capacitor coupled to a first floating diffusion node and a second
capacitor coupled to the second floating diffusion node.
5. The apparatus according to claim 4, wherein the first and second
capacitors are further coupled to ground.
6-10. (canceled)
11. An apparatus as in claim 1, further comprising an output
transistor having a gate connected to receive said signals
representing said first and second pixel output signals for
providing a combined pixel output to said column line.
12. An apparatus as in claim 11, wherein said sample-and-hold
circuit is coupled to said common column line and captures said
combined pixel output signal.
13. An apparatus as in claim 1, wherein each of said first and
second pixel circuits comprise a transfer transistor for
transferring charge integrated by an associated photo-conversion
device to an associated diffusion node.
14. An apparatus as in claim 13, wherein the transfer transistor of
said first and second pixel circuit have respective gates for
receiving respective transfer control signals which set the
integration time for each pixel circuit.
15. An apparatus as in claim 1, wherein each said pixel circuit
comprises: a pinned photodiode as said photo-conversion device; a
diffusion node; a transfer device, for transferring integrated
charge from said photodiode to said diffusion node; a reset device
for resetting said diffusion node to a known state before said
charge transfer; and an output transistor having a gate connected
to said diffusion node.
16. An apparatus as in claim 15, wherein each of said pixel
circuits further comprises a row select transistor for selectively
coupling an associated output transistor to a respective pixel
output line, said sample and hold circuit having input portions
respectively coupled to said pixel output line.
17. An apparatus as in claim 16, wherein the gates of said row
select transistors are coupled together such that said signal
representing said first and second pixel output signals are
respectively output from said first and second pixel circuit to
said respective output line.
18. A method for operating an image apparatus, comprising:
producing a first pixel output signal based on charge integration
by a first photo-conversion device over a first integration period;
producing a second pixel output signal based on charge integration
by a second photo-conversion device over a second integration
period, wherein second integration period is shorter than the first
integration period; and capturing signals representing said first
and second pixel output signals.
19. A method as in claim 18, further comprising respectively
transmitting said first and second pixel output signals to a first
and second column line.
20. A method as in claim 19, wherein said act of capturing
comprises capturing said first and second pixel output signals from
said first and second column line.
21. A method as in claim 18, further comprising transmitting said
first and second pixel output signals to a common column line.
22. A method as in claim 21, wherein said act of capturing
comprises capturing said signals representing said first and second
pixel output signals sequentially from said common line.
23-27. (canceled)
28. An imaging apparatus, comprising: a first pixel circuit,
comprising a first transfer pulse line, coupled to a gate of a
first transfer transistor, wherein first transfer transistor
transfers charge from a first photodiode to a first floating
diffusion node, and wherein said first floating diffusion node is
further coupled to a first reset transistor, a first capacitor, and
a second capacitor, said second capacitor being coupled to a common
floating gate line; a second pixel circuit, comprising a second
transfer pulse line, coupled to a gate of a first transfer
transistor, wherein first transfer transistor transfers charge from
a second photodiode to a second floating diffusion node, and
wherein said second floating diffusion node is further coupled to a
second reset transistor, a third capacitor, and a fourth capacitor,
said fourth capacitor being coupled to the common floating gate
line; a reset pulse line, connected to the gates of the first and
second reset transistor, wherein the first and second reset
transistors are coupled to respectively reset the first and second
floating diffusion node to a predetermined voltage state; a
floating gate pulse line, connected to a floating gate transistor,
wherein the floating gate transistor is further coupled to the
common floating gate line; and a source-follower transistor,
coupled to the common floating gate line for respectively coupling
said first and second pixel circuits to a column signal line, said
first transfer pulse line receiving a signal which operates said
first photodiode to integrate charge for a first time period and
said second transfer pulse line receiving a signal which operates
said second photodiode to integrate charge for a second time period
different from said first time period.
29. The apparatus according to claim 28, wherein the first and
second photodiodes are pinned photodiodes.
30. The apparatus according to claim 29, wherein the pinned
photodiodes are coupled to ground.
31. The apparatus according to claim 28, wherein a first thermal
noise (kTC) voltage is transmitted and added to the floating gate
line potential when the floating gate transistor is initially
turned off.
32. The apparatus according to claim 31, wherein a second thermal
noise (kTC) voltage is transmitted and added to the first and
second floating diffusion node voltages when the first and second
reset transistors are turned off, and wherein the first and second
thermal noise voltages are added to a floating gate voltage present
on the floating gate line to form a summed floating gate
voltage.
33. The apparatus according to claim 32, wherein the summed
floating gate voltage is sampled by a sample-and-hold circuit.
34. The apparatus according to claim 32, wherein the transferred
charge from the first and second photodiode is added to the summed
floating gate voltage.
35. The apparatus according to claim 28, wherein a floating gate
threshold voltage is applied to the floating gate transistor.
36. The apparatus according to claim 35, wherein a source-follower
threshold voltage is applied to the source-follower transistor.
37. The apparatus according to claim 36, wherein the floating gate
threshold voltage is lower than the source-follower threshold
voltage.
38. A processing system, comprising: a processor; and a CMOS
imaging device, coupled to said processor, said imaging device
comprising: a first pixel circuit, comprising a first transfer
pulse line, coupled to a gate of a first transfer transistor,
wherein first transfer transistor transfers charge from a first
photodiode to a first floating diffusion node, and wherein said
first floating diffusion node is further coupled to a gate of a
first source-follower transistor; a second pixel circuit,
comprising a second transfer pulse line, coupled to a gate of a
second transfer transistor, wherein second transfer transistor
transfers integrated charge from a second photodiode and to a
second floating diffusion node, and wherein said second floating
diffusion node is further coupled to a gate of a second
source-follower transistor; a reset pulse line, connected to the
gate of a first and second reset transistor, wherein the first
reset transistor is coupled to reset the first floating diffusion
node to a predetermined voltage state, and the second reset
transistor is coupled to reset the second floating diffusion node
to a predetermined voltage state; and a first and second row-select
transistor, respectively coupled to the first and second
source-follower transistors for respectively coupling said first
and second source follower transistors to a first column signal
line and a second column signal line, said first transfer pulse
line receiving a signal which operates said first photodiode to
integrate charge for a first time period and said second transfer
pulse line receiving a signal which operates said second photodiode
to integrate charge for a second time period different from said
first time period.
39. The system according to claims 38, wherein the first and second
photodiodes are pinned photodiodes.
40. The system according to claim 39, wherein the pinned
photodiodes are coupled to ground.
41. The system according to claim 38, further comprising a first
capacitor coupled to a first floating diffusion node and a second
capacitor coupled to the second floating diffusion node.
42. The system according to claim 41, wherein the first and second
capacitors are further coupled to ground.
43. A processing system, comprising: a processor; and a CMOS
imaging device, coupled to said processor, said imaging device
comprising: a first linear pixel circuit for producing a first
pixel output signal based on charge integration by a first
photo-conversion device over a first integration period; a second
linear pixel circuit for producing a second pixel output signal
based on charge integration by a second photo-conversion device
over a second integration period, wherein second integration period
is shorter than the first integration period; and a sample-and-hold
circuit for capturing signals representing said first and second
pixel output signals.
44. An system as in claim 43, further comprising first and second
column lines, respectively coupled to receive said signals
representing said first and second pixel output signals.
45. An system as in claim 44, wherein said sample-and-hold circuit
comprises a first sample-and-hold circuit portion coupled to said
first column line for capturing said signal representing said first
pixel output signal and a second sample-and-hold circuit portion
coupled to said second column line capturing said signal
representing said second pixel output signal.
46. An system as in claim 43, further comprising a column line
commonly connected to receive said signal representing said first
and second pixel output signals.
47. An system as in claim 46, wherein said sample-and-hold circuit
is coupled to said common column line and sequentially captures
said signals representing said first and second pixel output
signals.
48. An system as in claim 46, further comprising an output
transistor having a gate connected to receive said signals
representing said first and second pixel output signals for
providing a combined pixel output to said column line.
49. An system as in claim 48, wherein said sample-and-hold circuit
is coupled to said common column line and captures said combined
pixel output signal.
50. An system as in claim 43, wherein each of said first and second
pixel circuits comprise a transfer transistor for transferring
charge integrated by an associated photo-conversion device to an
associated diffusion node.
51. A system as in claim 50, wherein the transfer transistor of
said first and second pixel circuit have respective gates for
receiving respective transfer control signals which set the
integration time for each pixel circuit.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] The present application is a continuation of U.S.
application Ser. No. 10/294,686, filed Nov. 15, 2002, the
disclosure of which is herewith incorporated by reference in its
entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to the pixel structure used in
a CMOS active pixel array.
BACKGROUND OF THE INVENTION
[0003] The dynamic range (DR) for an image sensor is commonly
defined as the ratio of the largest nonsaturating signal to the
standard deviation of noise under dark conditions. The quality of
an image sensor is largely defined by its dynamic range--as it
increases, the sensor can detect a wider range of illuminations and
consequently produce images of greater detail and quality.
[0004] Several pixel architectures have been developed in an effort
to produce good dynamic range. However, conventional pixel
architectures are subject to one or more of the drawbacks of high
photodiode dark current, thermal (kTC) noise, fixed light
sensitivity ratio and charge leakage. Moreover, when logarithmic
architectures are used to increase dynamic range, a more
complicated color pixel processing is required.
BRIEF SUMMARY OF THE INVENTION
[0005] The present invention provides a pixel architecture which
seeks to mitigate many of the noted drawbacks and employs a dual
pixel pinned photodiode architecture operating in a dual charge
integration. The two pixels enable a dual sensitivity pixel array
in which one pixel functions to reproduce normal images, while the
other pixel functions to reproduce images with high illumination
levels. The dual charge integration mode and dual sensitivity, in
combination, produce a pixel architecture having good dynamic range
without having to resort to a logarithmic pixel architecture.
[0006] Various dual pixel, dual integration mode embodiments are
provided together with associated operating methods. These and
other features and advantages of the invention will be more closely
described from the following detailed description provided in
connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] FIG. 1 is a schematic diagram of a first embodiment of a
pixel in accordance with the invention;
[0008] FIG. 2 is a timing diagram illustrating operation of the
embodiment shown in FIG. 1;
[0009] FIG. 3 is a schematic diagram of a second embodiment of a
pixel circuit in accordance with the invention;
[0010] FIG. 4 is a timing diagram illustrating operation of the
embodiment shown in FIG. 3;
[0011] FIG. 5 is a schematic diagram of a third embodiment of a
pixel circuit in accordance with the invention;
[0012] FIG. 6 is a timing diagram illustrating operation of the
FIG. 5 embodiment; and
[0013] FIG. 7 is a graph illustrating an example of signal transfer
characteristics according with the present invention;
[0014] FIG. 8 is an example of pixel and on-chip microlens
placement.
[0015] FIG. 9 is an example system according to an embodiment
described herein.
DETAILED DESCRIPTION OF THE INVENTION
[0016] FIG. 1 illustrates a first embodiment of the present
invention, wherein the circuit comprises an upper pixel circuit 130
and a lower pixel circuit 131. The upper pixel circuit is defined
by pinned photodiode PPD1 (110), transfer transistor 100, floating
diffusion node "A," a capacitor 108 coupled to node "A", source
follower transistor 102 having a gate connected to node "A" and a
row select transistor 103. The pixel circuit includes a reset
transistor 101, which operates in response to a reset pulse signal
.phi..sub.RS applied to its gate. Row select transistor 103 is
further coupled to the first of two column signal lines (COL. 1)
and receives a row select pulse signal .phi..sub.RD at its gate.
Transfer transistor 100 is responsive to a transfer pulse signal
.phi..sub.T1 applied to its gate to transfer charge from the pinned
photodiode 110 to diffusion node "A." The upper pixel circuit is
operated to handle "normal" light conditions (i.e., from low light
to medium light levels) and has high sensitivity characteristics by
use of a longer integration time (T.sub.INT1, FIG. 2). Capacitor
108 may be the parasitic capacitance of node "A" or a discrete
capacitor.
[0017] The lower pixel circuit 131 is defined by pinned photodiode
PPD2 (111), transfer transistor 107, floating diffusion node "B,"
capacitor 109, coupled to node "B," source follower transistor 105
having a gate connected to node "B" and a row select transistor
104. Pixel circuit 131 also includes reset transistor 106, having a
gate which receives a reset pulse signal .phi..sub.RS. Row select
transistor 104 is further coupled to the second of two column
signal lines (COL. 2). Transfer transistor 107 is responsive to a
transfer pulse signal .phi..sub.T2 applied to its gate to transfer
charge from pinned photodiode 111 to floating diffusion node "B."
The lower pixel circuit is operated to have a lower sensitivity to
handle very high light levels by use of a shorter integration time
T.sub.INT2 (FIG. 2). Capacitor 109 may be the parasitic capacitance
of node "B" or a discrete capacitor.
[0018] Both column lines (COL. 1, COL. 2) are output to respective
sample-and-hold circuits 120, 121 for obtaining respective pairs of
an integrated pixel (V.sub.SIG1, V.sub.RST1) for pixel circuit 130,
and (V.sub.SIG2, V.sub.RST2) for pixel circuit 131. With the
2-column signal line configuration shown in FIG. 1, common reset
.phi..sub.RS, row select .phi..sub.RD, sample reset signal
.phi..sub.SHR and sample integration pixel .phi..sub.SHS can be
used for both pixels. An exemplary timing diagram disclosing
operation of the circuit of FIG. 1, is illustrated in FIG. 2. The
timing diagram illustrates the relationship between signals
.phi..sub.RS, .phi..sub.T1, .phi..sub.T2, .phi..sub.RD,
.phi..sub.SHR1, .phi..sub.SHS1, .phi..sub.SHR2, and .phi..sub.SHS2.
An integration time shown in FIG. 2 corresponds to the period
between the falling edge and the rising edge of transfer pulse
.phi..sub.T. In the illustrated embodiment, the pixel signal
integration time occurs during a frame time between horizontal
blanking periods (H-BL) corresponding to a respective row.
[0019] Since signal charge accumulates on each pinned photodiode
during the integration period (typically a few 10 s of a ms), and
the time for the signal charge to stay on the floating diffusion is
very short (a few .mu.s during blank-out period H-BL), signal
degradation due to leakage current is negligible. This is true even
if the leakage current on the floating diffusion node is relatively
large (assuming the leakage current of the pinned diode is
sufficiently low). During the integration period, reset pulse
.phi..sub.RS is turned ON so that the floating diffusion acts as a
lateral overflow drain. When a Correlated Double Sampling (CDS)
operation is used in which both reset (V.sub.RST) and charge
integration (V.sub.SIG) signals are taken during the same image
frame, little kTC noise appears with the proper pulse timing, and a
very low dark current exists as a result.
[0020] Turning to FIG. 2, during the charge integration period
(T.sub.INT1 for pixel 130, and T.sub.INT2 for pixel 131), electrons
accumulate across the pinned photodiodes 110 and 111. As reset
pulse signal .phi..sub.RS is brought high during the blanking
period, it turns reset transistors 101 and 106 on and resets the
floating diffusion nodes A and B in pixel circuits 130, 131 from
any previous integration cycle. Thus, a potential on floating
diffusion nodes A and B is set at V.sub.RS.
[0021] After the reset signal .phi..sub.RS is returned to its
initial low potential, the sample and hold circuitry (120, 121)
briefly samples the potential of the floating diffusion nodes A and
B. As can be seen from FIG. 2, .phi..sub.SHR1 and .phi..sub.SHR2
sample signals are pulsed concurrently.
[0022] As shown in FIG. 2, the integration period T.sub.INT1 for
pixel 130 begins first when the transfer gate signal .phi..sub.T1
is low. During integration period T.sub.INT1, charge is accumulated
by photodiode 110. The integration period T.sub.INT2 for pixel 131
begins after that of pixel 130 when transfer signal .phi..sub.T2
goes low. During integration period T.sub.INT2 charge is
accumulated by photodiode 111. Then, transfer pulses .phi..sub.T1
and .phi..sub.T2 are turned on and the charge stored on pinned
photodiodes are transferred to the floating diffusion nodes
(110.fwdarw.A, 111.fwdarw.B). After the transfer pulses
.phi..sub.T1 and .phi..sub.T2 are returned to their initial low
potential, the sample and hold circuitry (120, 121) briefly samples
the potential of the floating diffusion nodes A and B. As can be
seen from FIG. 2, .phi..sub.SHS1 and .phi..sub.SHS2 sample signals
are pulsed concurrently. Once the sample signals V.sub.SIG1,
V.sub.SIG2 are obtained, the pixel circuits 130, 131 are ready to
begin a charge integration period.
[0023] FIG. 3 illustrates a second embodiment of the present
invention, wherein one column signal line (310) is being used to
output the signals from two pixels 320, 321. The circuit of FIG. 3
obtains two sets of output signals (V.sub.RST1, V.sub.SIG1;
V.sub.RST2, V.sub.SIG2), and the charge transfer operation for the
two pixels is performed sequentially (as shown by the timing
diagram in FIG. 4).
[0024] The upper pixel circuit 320 of the pixel configuration
includes a transfer transistor 300, having a source coupled to
pinned photodiode PPD1 307, a drain coupled to floating diffusion
node "A," a capacitor 305 having one terminal coupled to diffusion
node "A" and to the drain of transfer transistor 300 and another
terminal coupled to ground. An anode of pinned photodiode 307 is
also coupled to ground. The gate of transfer transistor 300
receives transfer control signal .phi..sub.T1. Reset transistor 301
is coupled to both the upper and lower pixel circuits 320, 321 at
node "A", and is triggered by reset pulse signal .phi..sub.RS. The
upper pixel circuit 320 is operated to handle normal light
conditions, and is set to have high sensitivity characteristics by
use of a longer integration time T.sub.INT1 (FIG. 4). Capacitor 305
may be the parasitic capacitance of node "A" or a discrete
capacitor.
[0025] The lower pixel circuit 321 includes transfer transistor
304, having a source coupled to pinned photodiode PPD2 (308), and a
drain coupled to floating diffusion node "A". The pinned photodiode
308 is also coupled to ground. The gate of transfer transistor 304
receives transfer control signal .phi..sub.T2. The lower pixel
circuit 321 is operated to have lower light sensitivity to handle
very high light levels by use of a shorter integration time
T.sub.INT2 (FIG. 4).
[0026] The upper pixel and lower pixel circuits 320, 321 output
respective reset signals (V.sub.RST1, V.sub.RST2) and integration
signals (V.sub.SIG1, V.sub.SIG2) to a source follower transistor
302, which is further coupled to row select switch 303. The gate of
row select switch 303 is coupled a row select pulse signal
.phi..sub.RD, and the source of switch 303 is coupled to the column
signal line (COL). The column signal line outputs the signals
V.sub.SIG1, V.sub.SIG2, as well as reset signals V.sub.RST1,
V.sub.RST2.
[0027] An exemplary timing diagram depicting operation of the
circuit in FIG. 3 is shown in FIG. 4. The sample and hold circuit
330 for the FIG. 3 embodiment operates in response to applied
sample signals .phi..sub.SHR1, .phi..sub.SHS1, .phi..sub.SHR2, and
.phi..sub.SHS2 to sample and hold the pixel signal V.sub.RST1,
V.sub.SIG1, V.sub.RST2 and V.sub.SIG2. Similar to the timing
diagram in FIG. 2, the two integration times T.sub.INT1 (long) and
T.sub.INT2 (short) are respectively set by the transfer pulse
signals .phi..sub.T1, .phi..sub.T2.
[0028] Starting with reset, the floating node "A" is twice reset
during the horizontal blanking period (H-BL) by the two pulse
signals .phi..sub.RS, which turn on reset transistor 301. The row
select signal .phi..sub.RD turns on row select transistor 303
during the entire blanking period. The reset voltage V.sub.RST2 of
pixel 321 is sampled by applying the .phi..sub.SHR2 signal to
sample and hold circuit 330. Then the transfer pulse for the lower
pixel circuit .phi..sub.T2 turns on and the charge stored on the
pinned photodiode 308 is transferred to the node "A". When the
integration period T.sub.INT2 ends by signal .phi..sub.T2 returning
high and transferring charge to node "A," the integration charge
signal V.sub.SIG2 is sampled and held by sample and hold circuit
330 in response to sample signal .phi..sub.SHS2. After V.sub.SIG2
is sampled and held, the reset pulse is again turned on, thereby
clearing the charge on the floating diffusion node "A". The reset
voltage V.sub.RST1 of pixel 320 is sampled by applying the
.phi..sub.SHR1 signal to sample and hold circuit 330. Then the
transfer pulse for the upper pixel circuit .phi..sub.T1 turns on
and the charge stored on the pinned photodiode 307 is transferred
to the node "A". When the integration period T.sub.INT1 ends by
signal .phi..sub.T1 returning high and transferring charge to node
"A," the integration charge signal V.sub.SIG1 is sampled and held
by sample and hold circuit 330 in response to sample signal
.phi..sub.SHS1. Charge integration for pixel 320 begins when
transfer signal .phi..sub.T1 goes low to begin the longer
integration period T.sub.INT1, while charge integration for pixel
321 begins when transfer signal .phi..sub.T2 goes low sometime in
the frame time to begin the shorter integration period T.sub.INT2.
Thus, a single column line (COL) and sample and hold circuit 330
can be used for the two pixel circuits 320, 321 to provide the
pixel signals V.sub.RST1, V.sub.SIG1, and V.sub.RST2,
V.sub.SIG2.
[0029] A third embodiment of the present invention is illustrated
in FIG. 5, where the circuit comprises an upper and lower pixel
circuits 520, 521, with the upper pixel circuit 520 including
pinned photodiode PPD1 (510), transfer transistor 502, coupled
between the photodiode 510 and floating diffusion node FD1, and the
capacitor 507 having one terminal connected to floating diffusion
node FD1 and another terminal coupled to ground, reset transistor
500 coupled between a reset voltage V.sub.RS and node FD1, and
capacitor 506 having one terminal coupled to capacitor 507 and the
terminal coupled to a floating gate line 560 shared with lower
pixel circuit 521. The reset transistor 500 receives a reset
control signal .phi..sub.RS at its gate. The upper pixel circuit
520 provides an output on line 560 coupled to transistor 501 which
has one side connected to voltage V.sub.RFG and another side
connected to common floating gate line 560. The gate of transistor
501 receives a control signal .phi..sub.RFG.
[0030] The lower pixel circuit includes pinned photodiode PPD2
(511), transfer transistor 505, coupled between the photodiode 511
and floating diffusion node FD2, a capacitor 509 having one
terminal connected to node FD2 and another terminal connected to
ground, reset transistor 504 coupled between a reset voltage
V.sub.RS and node FD2, a capacitor 508 having one terminal
connected to node FD2 and another terminal connected to floating
gate line 560. Reset transistor 504 also has a gate connected to
reset control signal .phi..sub.RS. Transfer transistors 502 and 505
are respectively controlled by transfer control signals
.phi..sub.T1 and .phi..sub.T2.
[0031] In the third embodiment, the two pinned photodiodes (510,
511) accumulate signal charge during the integration times
T.sub.INT1 and T.sub.INT2 respectively. Then, during the horizontal
blanking period (H-BL), the accumulated charges at the photodiodes
510, 511 are transferred to the floating diffusion nodes ("FD1",
"FD2") respectively, wherein the signal voltages are added at the
gate of transistor 503 (node V.sub.FG) and sampled and held by
sample signal .phi..sub.SHS. The diffusion regions FD1 and FD2 are
reset by respective reset transistors 500 and 504, which have their
gates commonly connected to receive reset control signal
.phi..sub.RS. The reset signals from the two pixels are combined at
the gate of the transistor 503 and sampled and held by sample
signal .phi..sub.SHR. Voltages at the V.sub.FG node and FD1 and FD2
nodes are summarized in Table 1, shown below. The table shows the
on/off states of the timing signals of FIG. 6, and five different
operational states denoted by signal subscripts 0, 1, 2, 3, 4 for
pixel circuits 520 (i=1) and 521 (i=2).
TABLE-US-00001 TABLE 1 V.sub.FG and V.sub.FD, i (i = 1, 2) Timing
V.sub.FG V.sub.FD, i .phi..sub.RS = ON .phi..sub.RFG = ON
V.sub.FG.sub.--0 = V.sub.RFG V.sub.FD, i.sub.--0 = V.sub.RS
.phi..sub.RS = ON .phi..sub.RFG = OFF V.sub.FG.sub.--1 = V.sub.RFG
+ V.sub.FD, i.sub.--1 = V.sub.RS v.sub.kTC, FG .phi..sub.RS = OFF
.phi..sub.RFG = OFF V.sub.FG.sub.--2 = V.sub.FG1 + V.sub.FD,
i.sub.--2 = V.sub.RS + .alpha. (v.sub.kTC, FD1) + v.sub.kTC, FD, i
.beta. (v.sub.kTC, FD2) .phi..sub.T1 = ON .phi..sub.T2 = ON
V.sub.FG.sub.--3 = V.sub.FG.sub.--2 + V.sub.FD, i.sub.--3 =
V.sub.FD, i.sub.--2 + .alpha. V.sub.sig1 + .beta. V.sub.sig2
V.sub.sig, i .phi..sub.T1 = OFF .phi..sub.T2 = OFF V.sub.FG.sub.--4
= V.sub.FG.sub.--3 V.sub.FD, i.sub.--4 = V.sub.FD, i.sub.--3
[0032] During a first operational state (phase 0), the floating
diffusion nodes FD1 and FD2 are reset at V.sub.RS, while the
floating gate line is reset at V.sub.RFG. During a second
operational state (phase 1) the pulse .phi..sub.RFG is turned off,
and the kTC noise, v.sub.kTC,FG, appears on the floating gate line.
During a third operational state (phase 2), the reset pulse
.phi..sub.RS is turned off, and the kTC noise, v.sub.kTC,FD,i,
appears on the floating diffusion nodes FD1 and FD2. At this
moment, these kTC noise voltages, v.sub.kTC,FD,1, and
v.sub.kTC,FD,2, affect the floating gate line potential through
coupling capacitors 506 and 508, and the resulting floating gate
potential is shown in the third row of Table 1. This floating gate
potential is sampled and held by pulsing the reset sampling pulse
.phi..sub.SHR.
[0033] During a fourth operational state (phase 3), transfer pulses
.phi..sub.T1 and .phi..sub.T2 are turned on and the signal charge
stored on the photodiodes are transferred to the floating diffusion
nodes (510.fwdarw.FD1, 511.fwdarw.FD2). As a result, the floating
diffusion potential becomes
V.sub.FD,i.sub.--.sub.3=V.sub.FD,i.sub.--.sub.2+V.sub.sig,i. These
potentials again affect the floating gate potential through
coupling capacitors 506 and 508, and the resulting floating gate
potential is shown in the fourth row of Table 1. This floating gate
potential is sampled and held by pulsing the signal sampling pulse
.phi..sub.SHS.
[0034] During a fifth operational state (phase 4), no change occurs
from the state in phase 3. During the integration period,
.phi..sub.RS is preferably set at high so that the floating
diffusion nodes act as lateral overflow drains. Also, the pulse
.phi..sub.RFG is set high with V.sub.RFG being set below the
threshold voltage of the source follower transistor 503, so that a
row select transistor, which is used in the 1.sup.st and 2.sup.nd
embodiments, can be eliminated.
[0035] The sample-and-hold pulses (.phi..sub.SHR and .phi..sub.SHS)
sample the reset level (corresponds to V.sub.FG.sub.--.sub.2) and
the signal level (corresponds to V.sub.FG.sub.--.sub.3 or
V.sub.FG.sub.--.sub.4), respectively. The output voltage of the CDS
circuit is given by:
V.sub.OUT.sub.--.sub.CDS.varies.(V.sub.FG.sub.--.sub.4-V.sub.FG.sub.--.s-
ub.2)=.alpha.V.sub.sig1+.beta.V.sub.sig2 (1)
which calculates a weighted-sum operation, and where .alpha. and
.beta. are characterized by:
.alpha. = C C 1 C C 1 + C C 2 C G ( 2 ) .beta. = C C 2 C C 1 + C C
2 + C G ( 3 ) ##EQU00001##
where capacitors C.sub.C1 and C.sub.C2 are illustrated as
capacitors 506 and 508, respectively and C.sub.G is the parasitic
capacitance between the floating gate (i.e., the node at which
V.sub.FG accumulates) and the substrate. V.sub.sig1 and V.sub.sig2
are given by:
V sig , i = N sig , i C FD , i ( 4 ) ##EQU00002##
Where i=(1,2) for pixel circuit 520 and 521 respectively,
C.sub.FD,i represent the capacitance of capacitors 507 or 509, and
N.sub.sig,i represents the signal electrons accumulated on the
pinned photodiode 510 or 511.
[0036] As is shown in Table 1, by employing proper timing, a
correlated double sampling (CDS) sample and hold circuit 530 on a
column line eliminates the kTC noise from transistors 500, 504 and
501. In order to obtain the same saturation voltage, the photodiode
size and the floating diffusion size can be set as
A PPD 1 C FD 1 = A PPD 2 C FD 2 ( 5 ) ##EQU00003##
where C.sub.FD1 and C.sub.FD2 represent the capacitance of the
floating diffusion 510 and 511 and A.sub.PPD1 and A.sub.PPD2 are
the light sensitive area of the photodiodes 510 and 511.
[0037] For example, assuming that C.sub.FD1/C.sub.FD2=4,
A.sub.PPD1/A.sub.PPD2=4, T.sub.INT1=16 ms and T.sub.INT2=160 .mu.s
(see FIG. 6), the ratio of sensitivities will be 100 (+40 dB). An
example of the output transfer characteristic of the FIG. 5
embodiment is illustrated in FIG. 7. When the relationship of
equation (5) holds, the graph in FIG. 7 discloses the correlation
among signals V.sub.out, V.sub.sig1 and V.sub.sig2, as described
above. Since the floating gate node 560 can be set at a voltage
below the threshold of the source follower transistor 503 during
the integration period, a row select transistor can be removed from
the circuitry (FIG. 5). In the first and second embodiments, two
sets of output images for a pixel are obtained for the two pixel
pairs. In the embodiment in FIGS. 5-6, one output signal set
V.sub.FG.sub.--.sub.4, V.sub.FG.sub.--.sub.2 is obtained having
reset components of both pixels (V.sub.FG.sub.--.sub.2) and pixel
signal component of both pixels (V.sub.FG.sub.--.sub.4) with
linearly kneed characteristics (FIG. 7).
[0038] When an on-chip microlens array as shown in FIG. 8 is used,
it is possible to further increase the dynamic range of an imager
containing pixels constructed in accordance with the invention.
FIG. 8 provides an example of an on-chip microlens placement. Under
the configuration shown, most of the incident light passing through
the lens (801) array of a unit pixeL; 800 is focused onto PPD1 802,
the photodiode having the longer integration time in each of the
embodiments described above, while the remaining incident light is
unfocused and passed to photodiode PPD2 803, having the shorter
integration time. The increased effective area of PPD1 (A.sub.PPD1)
would further extend the dynamic range.
[0039] A typical processor based system that includes a CMOS imager
device according to the present invention is illustrated generally
in FIG. 9. A processor based system is exemplary of a system having
digital circuits that could include CMOS imager devices. Without
being limiting, such a system could include a computer system,
camera system, scanner, machine vision system, vehicle navigation
system, video telephone, surveillance system, auto focus system,
star tracker system, motion detection system, image stabilization
system and data compression system for high-definition television,
all of which can utilize the present invention.
[0040] A processor system, such as a computer system, for example
generally comprises a central processing unit (CPU) 944 that
communicates with an input/output (I/O) device 946 over a bus 952.
The CMOS imager 910 also communicates with the system over bus 952.
The computer system 900 also includes random access memory (RAM)
948, and, in the case of a computer system may include peripheral
devices such as a floppy disk drive 954 and a compact disk (CD) ROM
drive 956 which also communicate with CPU 944 over the bus 952. As
described above, CMOS imager 910 is combined with a pipelined JPEG
compression module in a single integrated circuit.
[0041] As can be seen in the embodiments described herein, the
present invention encompasses a unique two pixel structure that
employs pinned photodiodes to provide extended dynamic ranges for
imaging circuits. By using dual sensitivity and dual integration
time techniques in the circuitry along with the pinned photodiodes,
the dynamic range can effectively be extended without experiencing
excessive noise. Accordingly, image sensors employing this circuit
and method can detect a wider range of illuminations and
consequently produce images of greater detail and quality.
[0042] It should again be noted that although the invention has
been described with specific reference to CMOS imaging devices, the
invention has broader applicability and may be used in any imaging
apparatus. The above description and drawings illustrate preferred
embodiments of the present invention. It is not intended that the
present invention be limited to the illustrated embodiments. Any
modification of the present invention that comes within the spirit
and scope of the following claims should be considered part of the
present invention.
* * * * *