U.S. patent application number 12/401373 was filed with the patent office on 2009-07-09 for semiconductor device and fabricating method thereof.
This patent application is currently assigned to Dongbu Electronics Co. Ltd.. Invention is credited to Yong Keon CHOI.
Application Number | 20090174004 12/401373 |
Document ID | / |
Family ID | 34698938 |
Filed Date | 2009-07-09 |
United States Patent
Application |
20090174004 |
Kind Code |
A1 |
CHOI; Yong Keon |
July 9, 2009 |
SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF
Abstract
A semiconductor device including a semiconductor substrate
having first and second device regions. A first trench is formed in
the first region and a second trench is formed in the second
region. The first trench and the second trench have different
widths and different depths. The first trench and the second trench
define device isolation regions and active regions.
Inventors: |
CHOI; Yong Keon;
(Bucheon-city, KR) |
Correspondence
Address: |
LOWE HAUPTMAN HAM & BERNER, LLP
1700 DIAGONAL ROAD, SUITE 300
ALEXANDRIA
VA
22314
US
|
Assignee: |
Dongbu Electronics Co. Ltd.
Seoul
KR
|
Family ID: |
34698938 |
Appl. No.: |
12/401373 |
Filed: |
March 10, 2009 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11024748 |
Dec 30, 2004 |
7521771 |
|
|
12401373 |
|
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|
|
Current U.S.
Class: |
257/369 ;
257/501; 257/E27.062 |
Current CPC
Class: |
H01L 21/823878 20130101;
H01L 21/76229 20130101; H01L 21/76232 20130101 |
Class at
Publication: |
257/369 ;
257/501; 257/E27.062 |
International
Class: |
H01L 27/092 20060101
H01L027/092; H01L 23/58 20060101 H01L023/58 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 31, 2003 |
KR |
10-2003-0101929 |
Claims
1. A semiconductor device comprising: a semiconductor substrate
having high and low voltage regions; a first trench formed in the
high voltage region; a second trench formed in the low voltage
region; and a third trench formed below the first trench, wherein
said first trench and said third trench have different widths and
different depths, and said first trench and said second trench
define device isolation regions and active regions.
2. The semiconductor device of claim 1, wherein the high voltage
region includes a CMOS operated by high voltage and the low voltage
region includes a CMOS operated by low voltage.
3. The semiconductor device of claim 1, wherein the first trench
and the third trench have stepped sidewalls.
4. The semiconductor device of claim 3, wherein width of the first
trench is wider than that of the third trench.
5. The semiconductor device of claim 4, wherein the first trench is
formed with a depth identical to the second trench.
6. The semiconductor device of claim 1, wherein each trench is
filled with dielectric material.
7. The semiconductor device of claim 6, wherein the dielectric
material is an oxide layer.
8-23. (canceled)
24. The semiconductor device of claim 1, further comprising
first-conductivity-type wells formed to a depth selected to
withstand high voltage in the high voltage region of the
semiconductor substrate; and second-conductivity-type wells formed
in the low voltage region.
25. The semiconductor device of claim 24, wherein the depth of the
third trench is greater than the depth of the
first-conductivity-type wells.
26. The semiconductor device of claim 1, wherein the third trench
is formed deeper than the second trench.
27. The semiconductor device of claim 1, wherein the high voltage
region comprises an NMOS transistor region and PMOS transistor
region, and the first and third trenches are formed between the
NMOS and PMOS transistor regions.
28. The semiconductor device of claim 24, wherein the
second-conductivity-type wells are formed thinner and narrower than
the first-conductivity-type wells.
Description
BACKGROUND OF THE INVENTION
[0001] (a) Field of the Invention
[0002] The present invention relates to a semiconductor device, and
in particular, to a semiconductor device having a gate to which
different voltages are applied and a method for fabricating the
semiconductor device.
[0003] (b) Description of the Related Art
[0004] As semiconductor devices have been implemented for various
applications, different device characteristics are required. For
example, there can be a device such as a logic and central
processing unit (CPU) merged with Dynamic Random Access Memory
(DRAM) or Static Random Access Memory (SRAM). Accordingly, a high
voltage device and low voltage device are formed in a single
substrate.
[0005] The operation voltage of the chip varies according to the
characteristics of respective devices integrated in the single
chip. Thus, even though some components perform identical
functions, their volume and size differ from each other according
to the input voltages.
[0006] FIG. 1 is a cross sectional view illustrating a conventional
CMOS of a high voltage region.
[0007] Referring to FIG. 1, P and N wells 102 are formed in an
active region defined by a device isolation region 110 which is
formed by filling a trench (T) formed within a substrate 10. Below
the device isolation region 110, channel stop regions 112 are
formed by doping the impurity ions of a type identical to those of
the wells 102, respectively.
[0008] An NMOS transistor is formed in the P well of the high
voltage region. An active region divided by the device isolation
region 110 and a PMOS transistor is formed in the N well. In the
drawing only a gate 114 and a gate dielectric layer 113 of the
respective thin layer transistor are depicted. The channel stop
regions 112 are positioned below the device isolation region
between the P type transistor and the N type transistor and prevent
the two devices from affecting each other.
[0009] However, the conventional method has drawbacks in that the
fabrication processes are so complicated. The conventional
processes are also limited in miniaturizing the size of the device,
because the sizes of the device isolation region and the active
region should be designed in consideration of the channel stop
region.
SUMMARY OF THE INVENTION
[0010] The present invention has been made in an effort to solve
the above problems. It is an object of the present invention to
provide a semiconductor device and a fabrication method thereof,
which is capable of minimizing the semiconductor device as well as
simplifying the fabrication processes.
[0011] To achieve the above object, in the present invention the
trench defining a device isolation region between a high voltage
region and a low voltage region may be formed in double depths.
[0012] In one aspect of the present invention, the semiconductor
device includes a semiconductor substrate having first and second
device regions and trenches formed in the first and second device
regions, with different widths and different depths, which define
device isolation regions and active regions.
[0013] In an exemplary embodiment, the first device region is
provided with a CMOS to which high voltage is applied and the
second device region is provided with a CMOS to which low voltage
is applied.
[0014] In an exemplary embodiment, the trench of the first device
region is provided with stepped sidewalls.
[0015] In an exemplary embodiment, the trench of the first device
region includes a first region of a first width and a second region
of a second width.
[0016] In an exemplary embodiment, the first region is formed with
a depth identical to the depth of the device isolation region of
the second device region.
[0017] In an exemplary embodiment, the trench is filled with
dielectric material.
[0018] In an exemplary embodiment, the dielectric material is an
oxide layer.
[0019] In another aspect of the present invention, a method for
fabricating a semiconductor device includes forming first and
second trenches for defining device isolation regions in first and
second device regions of a semiconductor substrate, forming a third
trench by selectively etching a predetermined area of the substrate
within the first trench, and filling the first to third trenches
with dielectric material.
[0020] In an exemplary embodiment, the method further includes
forming an oxide layer by oxidizing inner walls of the first to
third trenches before filling the dielectric material.
[0021] In an exemplary embodiment, the third trench is formed
narrower than the first trench.
[0022] In an exemplary embodiment, the third trench is formed
deeper than the second trench.
[0023] In an exemplary embodiment, the third trench is formed below
the first trench and with stepped sidewalls.
[0024] It is to be understood that both the foregoing general
description of the invention and the following detailed description
are exemplary, but are not restrictive of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0025] FIG. 1 is a cross sectional view illustrating a conventional
CMOS of a high voltage region.
[0026] FIG. 2 is a cross sectional view illustrating a structure of
a semiconductor device according to an exemplary embodiment of the
present invention.
[0027] FIG. 3 to FIG. 5 are cross-sectional views illustrating
fabrication steps of the semiconductor device according to an
exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0028] A semiconductor device according to an exemplary embodiment
of the present invention will be described in detail with reference
to the accompanying drawings.
[0029] As shown in FIG. 2, the semiconductor device includes a
plurality of high voltage regions A and low voltage regions B. The
respective high and low voltage regions A and B are divided into
first and second high voltage active regions A1 and A2 and first
and second low voltage active regions B1 and B2 by respective
device isolation regions 21 and 23 formed by trenches T1 and
T2.
[0030] The device isolation region 21 of the high voltage region A
includes an oxide layer 16 formed thinly along inner walls of the
trenches T1 and T2, and a dielectric material layer 20 filling the
trench coated by the oxide layer 16. In a similar manner, the
device isolation region 23 of the low voltage region B includes the
oxide layer 16 formed thinly along inner walls of the trench T1,
and a dielectric material layer 22 filling the trench coated by the
oxide layer 16.
[0031] In more detail, the trenches T1 and T2 of the high voltage
region A are formed with different widths so as to have stepped
sidewalls, the widths of the trenches T1 and T2 being L1 and L2,
respectively. That is, the upper trench T1 is formed with a broad
width of L1 and the lower trench T1 is formed below the first
trench with a narrow width L2. The lower trench is formed deeply so
as to completely block the interaction between the neighboring
active regions. The depth of the lower trench T2 is greater than
the depth of the P and N wells.
[0032] In the first and second active regions A1 and A2 of the high
voltage region A, the P and N well regions 12 and 14 doped at a low
concentration level are formed, respectively. An NMOS transistor is
formed in the P well region 12 and a PMOS transistor is formed in
the N well region 14, which are roughly depicted in the
drawings.
[0033] The NMOS transistor is doped at a high concentration level
so as to define the channel region. The NMOS transistor includes a
source region (not shown) and a drain region 34 doped with the N
type impurity at a high concentration level, a low doping
concentration region 36 formed between the channel region and the
respective source and drain regions by doping with N type impurity,
and a gate oxide layer 30 and a gate 32 formed at the channel
region on the substrate in sequential order.
[0034] The gate 32 can be formed out of polycrystalline silicon or
metal. The gate oxide layer 30 between the substrate and the gate
32 can be formed by thermally oxidizing the substrate or depositing
silicon oxide through chemical vapor deposition.
[0035] The PMOS transistor formed in the N well region has an
identical structure to the NMOS transistor, however, the impurity
doped into the source region 35, the drain region (not shown), and
the low doping concentration region 37 is N type impurity.
[0036] Regarding the structure of the low voltage region B, the
device isolation region 23 is formed on the substrate 10 using an
STI technique, and the N type well 26 and the P type well 24 is
formed within the substrate 10.
[0037] In the N type well 26 a gate oxide layer 40 and a gate 42
having spacers 44 are formed. Below the spacers 44, low doping
concentration regions 46 are formed by doping the impurity ions at
a low concentration level. A source region 49 and a drain region
(not shown) are formed by doping the impurity ions at a high
concentration level so as to contact the low doping concentration
region 46. The low doping concentration region 46, the source
region, and the drain region are doped with P type impurity
ions.
[0038] Also, in the P type well 24 a gate oxide layer 40 and a gate
42 having spacers 44 are formed. Below the spacers 44, low doping
concentration regions 46 are formed by doping the N type impurity
ions at a low concentration level, and a source region 48 and the
drain region (not shown) are formed by doping the N type impurity
ions at a high concentration level, so as to contact the low doping
concentration regions 46.
[0039] The trench T1, defining the device isolation region of the
low voltage region B, is formed with a single width and shallow
depth in comparison with the trench T1 and T2 of the high voltage
region A. Also, the low doping concentration region 46 and the P
and N wells 24 and 26 are formed thinner and narrower than those of
the high voltage region A.
[0040] A method for fabricating the above structured semiconductor
device according to an exemplary embodiment invention will be
described herein after with reference to FIG. 3 to FIG. 5 together
with FIG. 2.
[0041] As shown in FIG. 3, P and N wells capable of withstanding
high voltage are formed on predetermined regions of a semiconductor
substrate 10 by injecting P and N type impurities, respectively.
The low doping concentration region is protected by a photoresist
film.
[0042] After forming the photoresist film on the substrate, a first
photoresist pattern is formed through a photolithographic process.
The substrate is etched using the first photoresist pattern as a
mask so as to form shallow trenches in the high voltage region A
and the low voltage region B, respectively.
[0043] After removing the first photoresist pattern (PR), thin
oxide layer 16 is formed on the inner walls of the shallow trench
T1 by oxidizing the substrate 10. The oxide layer 16 alleviates the
stress between the dielectric material to be buried in the
following process and the semiconductor substrate, and minimizes
errors caused by reflection during the exposure in the
photolithography process using the photoresist layer.
[0044] As shown in FIG. 4, the second photoresist pattern (PR)
exposes predetermined areas of the bottom surface of the shallow
trench T1 of the high voltage region A. This is accomplished by
forming the photoresist on the substrate and patterning the
photoresist through the photolithography process. The deep trench
T2 is formed by etching the exposed substrate below the shallow
trench T1 using the second photoresist pattern (PR) as a mask. The
width of the deep trench T2 is narrower than that of the shallow
trench T1.
[0045] As shown in FIG. 5, after removing the photoresist pattern
(PR), a thin oxide layer is formed on the inner walls of the deep
trench T2 by oxidizing the substrate 10. The oxide layer alleviates
the stress between the dielectric material to be buried in the
following process and the substrate 100, and can be optionally
formed as needed.
[0046] The trenches T1 and T2 are coated by the oxide layer 16 and
filled with the dielectric material. The dielectric material is
made smooth with a chemical mechanical polishing process, so as to
completely form the device isolation regions 21 and 23 for the high
voltage and low voltage regions.
[0047] The trenches T1 and T2 in the high voltage region are formed
with different widths. This makes it possible to form the device
isolation region 21 satisfying the required characteristic of the
high voltage region without changing the structure of the device
isolation region 23 of the low voltage region B. Also, the device
isolation region 21 of the high voltage region A is formed to the
depth of the wells 12 and 14. This makes it possible to simplify
the fabrication process, because there is no need to form a channel
stop layer below the device isolation region, which is formed by
doping the impurity ions.
[0048] In the semiconductor device fabrication method according to
an exemplary embodiment of the present invention, following
processes that are not directly related to the present invention
will be schematically explained.
[0049] As shown in FIG. 2, the gate oxide layers 30 and 40 and the
gates 32 and 42 having different thicknesses are formed in the
respective active regions A1, A2, B1, and B2. Before or after
forming the gate, the low doping concentration regions 36, 37, and
46 and the high doping concentration regions 36, 37, 48, and 49 are
formed.
[0050] As described above, the device isolation regions can be
formed with different depths and widths, such that it is not
required to form the channel stop layer. Accordingly, there is no
need to carry out the ion injection and photolithography process
for forming the channel stop layer, such that the fabrication
process of the semiconductor device becomes simplified.
[0051] Also, the device isolation regions having various contours
suitable for the respective high and low voltages regions can be
formed by changing the structure of the low voltage region.
[0052] Also, since the semiconductor device fabrication method of
the present invention does not require a process for forming a
channel stop layer, the fabrication process becomes simplified,
resulting in an increase in productivity.
[0053] As described above, the trench defining the device isolation
region of the high voltage region is formed in double depth such
that it is possible to reduce the width of the device isolation
region, resulting in miniaturization and integration of the
semiconductor device.
[0054] Korean Patent Application No. 10-2003-0101929, filed on Dec.
31, 2003, is incorporated herein by reference in its entirety.
[0055] Although exemplary embodiments of the present invention have
been described in detail hereinabove, it should be clearly
understood that many variations and/or modifications of the basic
invention concepts herein taught which may appear to those skilled
in the present art will still fall within the spirit and scope of
the present invention, as defined in the appended claims.
* * * * *