U.S. patent application number 12/255312 was filed with the patent office on 2009-06-11 for method for manufacturing semiconductor device.
This patent application is currently assigned to SEMICONDUCTOR ENERGY LABORATORY CO., LTD.. Invention is credited to Yoko Chiba, Saishi Fujikawa, Kunio Hosoya.
Application Number | 20090148970 12/255312 |
Document ID | / |
Family ID | 40722087 |
Filed Date | 2009-06-11 |
United States Patent
Application |
20090148970 |
Kind Code |
A1 |
Hosoya; Kunio ; et
al. |
June 11, 2009 |
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Abstract
To provide a manufacturing method of a highly reliable TFT, by
which a more refined pattern can be formed through a process using
four or three masks, and a semiconductor device. A channel-etched
bottom gate TFT structure is adopted in which a photoresist is
selectively exposed to light by rear surface exposure utilizing a
gate wiring to form a desirably patterned photoresist, and further,
a halftone mask or a gray-tone mask is used as a multi-tone mask.
Further, a step of lifting off using a halftone mask or a gray-tone
mask and a step of reflowing a photoresist are used.
Inventors: |
Hosoya; Kunio; (Atsugi,
JP) ; Fujikawa; Saishi; (Atsugi, JP) ; Chiba;
Yoko; (Atsugi, JP) |
Correspondence
Address: |
John F. Hayden;FISH & RICHARDSON P.C
11th Floor, 1425 K Street, N.W
Washington
DC
20005
US
|
Assignee: |
SEMICONDUCTOR ENERGY LABORATORY
CO., LTD.
Atsugi-shi
JP
|
Family ID: |
40722087 |
Appl. No.: |
12/255312 |
Filed: |
October 21, 2008 |
Current U.S.
Class: |
438/29 ;
257/E21.409; 257/E33.004; 438/151 |
Current CPC
Class: |
H01L 27/1288 20130101;
H01L 27/1214 20130101; H01L 29/66765 20130101 |
Class at
Publication: |
438/29 ; 438/151;
257/E21.409; 257/E33.004 |
International
Class: |
H01L 33/00 20060101
H01L033/00; H01L 21/336 20060101 H01L021/336 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 23, 2007 |
JP |
2007-275781 |
Claims
1. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate; etching the first
conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode; forming a
first semiconductor layer over the gate insulating film; forming a
second semiconductor layer including an impurity element imparting
one conductivity type over the first semiconductor layer;
performing rear surface exposure to form a second photoresist;
etching the first semiconductor layer and the second semiconductor
layer including the impurity element imparting one conductivity
type using the second photoresist, thereby forming a first
semiconductor island and a second semiconductor island including
the impurity element imparting one conductivity type; forming a
second conductive film over the substrate; forming a third
photoresist using a multi-tone mask over the second conductive
film; etching the second conductive film using the third
photoresist; ashing the third photoresist; etching the second
conductive film using the ashed third photoresist to form a source
electrode and a drain electrode; and etching the first
semiconductor island and the second semiconductor island including
the impurity element imparting one conductivity type using the
ashed third photoresist to form a channel region, a source region,
and a drain region.
2. The method for manufacturing a semiconductor device, according
to claim 1, wherein the multi-tone mask is a halftone mask or a
gray-tone mask.
3. The method for manufacturing a semiconductor device, according
to claim 1, wherein the rear surface exposure is performed through
the first semiconductor layer and the second semiconductor layer
including the impurity element imparting one conductivity type.
4. The method for manufacturing a semiconductor device, according
to claim 1, wherein the first semiconductor layer is an amorphous
semiconductor layer.
5. The method for manufacturing a semiconductor device, according
to claim 1, wherein the first semiconductor layer is an i-type
amorphous silicon layer.
6. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate; etching the first
conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode; forming a
first semiconductor layer over the gate insulating film; forming a
second semiconductor layer including an impurity element imparting
one conductivity type over the first semiconductor layer;
performing rear surface exposure to form a second photoresist;
etching, using the second photoresist, the first semiconductor
layer and the second semiconductor layer including the impurity
element imparting one conductivity type, thereby forming a first
semiconductor island and a second semiconductor island including
the impurity element imparting one conductivity type; forming a
second conductive film over the substrate; forming a third
photoresist using a multi-tone mask over the second conductive
film; etching, using the third photoresist, the second conductive
film, the second semiconductor island including the impurity
element imparting one conductivity type, and the first
semiconductor island to form a wiring; ashing the third
photoresist; etching the second conductive film using the ashed
third photoresist to form a source electrode and a drain electrode;
etching the second semiconductor island including the impurity
element imparting one conductivity type and the first semiconductor
island using the ashed third photoresist to form a channel region,
a source region, and a drain region; forming a protective film over
the substrate; forming a contact hole in the protective film using
a fourth photoresist; forming a third conductive film over the
protective film; and etching the third conductive film using a
fifth photoresist to form a pixel electrode.
7. The method for manufacturing a semiconductor device, according
to claim 6, wherein the multi-tone mask is a halftone mask or a
gray-tone mask.
8. The method for manufacturing a semiconductor device, according
to claim 6, wherein the rear surface exposure is performed through
the first semiconductor layer and the second semiconductor layer
including the impurity element imparting one conductivity type.
9. The method for manufacturing a semiconductor device, according
to claim 6, wherein the first semiconductor layer is an amorphous
semiconductor layer.
10. The method for manufacturing a semiconductor device, according
to claim 6, wherein the first semiconductor layer is an i-type
amorphous silicon layer.
11. The method for manufacturing a semiconductor device, according
to claim 6, wherein the pixel electrode is a transparent conductive
film.
12. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate; etching the first
conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode; forming a
first semiconductor layer over the gate insulating film; forming a
second semiconductor layer including an impurity element imparting
one conductivity type over the first semiconductor layer;
performing first rear surface exposure to form a second
photoresist; etching, using the second photoresist, the first
semiconductor layer and the second semiconductor layer including
the impurity element imparting one conductivity type, thereby
forming a first semiconductor island and a second semiconductor
island including the impurity element imparting one conductivity
type; forming a second conductive film over the substrate; forming
a third photoresist using a first multi-tone mask over the second
conductive film; etching, using the third photoresist, the second
conductive film, the second semiconductor island including the
impurity element imparting one conductivity type, and the first
semiconductor island; ashing the third photoresist; etching the
second conductive film using the ashed third photoresist to form a
source electrode and a drain electrode; etching the second
semiconductor island including the impurity element imparting one
conductivity type and the first semiconductor island using the
ashed third photoresist to form a channel region, a source region,
and a drain region; forming a fourth photoresist using a second
multi-tone mask; ashing the fourth photoresist; forming a third
conductive film over the second conductive film and the fourth
photoresist; removing the fourth photoresist and part of the third
conductive film formed thereon to form a pixel electrode; forming a
protective film over the substrate; performing second rear surface
exposure to form a fifth photoresist over the protective film;
performing a reflow process on the fifth photoresist; and etching
the protective film using the fifth photoresist subjected to the
reflow process.
13. The method for manufacturing a semiconductor device, according
to claim 12, wherein each of the first and second multi-tone masks
is a halftone mask or a gray-tone mask.
14. The method for manufacturing a semiconductor device, according
to claim 12, wherein the first rear surface exposure is performed
through the first semiconductor layer and the second semiconductor
layer including the impurity element imparting one conductivity
type.
15. The method for manufacturing a semiconductor device, according
to claim 12, wherein the first semiconductor layer is an amorphous
semiconductor layer.
16. The method for manufacturing a semiconductor device, according
to claim 12, wherein the first semiconductor layer is an i-type
amorphous silicon layer.
17. The method for manufacturing a semiconductor device, according
to claim 12, wherein the pixel electrode is a transparent
conductive film.
18. A method for manufacturing a semiconductor device, comprising:
forming a first conductive film over a substrate; etching the first
conductive film using a first photoresist to form a gate electrode
and a wiring; forming a gate insulating film over the gate
electrode and a first wiring; forming a first semiconductor layer
over the gate insulating film; forming a second semiconductor layer
including an impurity element imparting one conductivity type over
the first semiconductor layer; performing first rear surface
exposure to form a second photoresist; etching, using the second
photoresist, the first semiconductor layer and the second
semiconductor layer including the impurity element imparting one
conductivity type, thereby forming a first semiconductor island and
a second semiconductor island including the impurity element
imparting one conductivity type over the gate electrode and forming
a third semiconductor island and a fourth semiconductor island
including the impurity element imparting one conductivity type over
the first wiring; forming a second conductive film over the
substrate; forming a third photoresist using a first multi-tone
mask over the second conductive film; etching, using the third
photoresist, a part of the second conductive film and the fourth
semiconductor island including the impurity element imparting one
conductivity type and the third semiconductor island over the first
wiring; ashing the third photoresist; etching the second conductive
film using the ashed third photoresist to form a source electrode
and a drain electrode; etching the second semiconductor island
including the impurity element imparting one conductivity type and
the first semiconductor island using the ashed third photoresist to
form a channel region, a source region, and a drain region; forming
a fourth photoresist using a second multi-tone mask over the
substrate; etching part of the gate insulating film, which is not
covered with the fourth photoresist, using the fourth photoresist
to form a contact hole over the first wiring; ashing the fourth
photoresist; forming a third conductive film over the second
conductive film and the fourth photoresist; removing the fourth
photoresist and parts of the third conductive film formed on the
fourth photoresist to form a pixel electrode and a second wiring;
forming a protective film over the substrate; performing second
rear surface exposure to form a fifth photoresist over the
protective film; performing a reflow process on the fifth
photoresist; and etching the protective film using the fifth
photoresist subjected to the reflow process.
19. The method for manufacturing a semiconductor device, according
to claim 18, wherein each of the first and second multi-tone masks
is a halftone mask or a gray-tone mask.
20. The method for manufacturing a semiconductor device, according
to claim 18, wherein the first rear surface exposure is performed
through the first semiconductor layer and the second semiconductor
layer including the impurity element imparting one conductivity
type.
21. The method for manufacturing a semiconductor device, according
to claim 18, wherein the first semiconductor layer is an amorphous
semiconductor layer.
22. The method for manufacturing a semiconductor device, according
to claim 18, wherein the first semiconductor layer is an i-type
amorphous silicon layer.
23. The method for manufacturing a semiconductor device, according
to claim 18, wherein the pixel electrode is a transparent
conductive film.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for manufacturing
semiconductor devices, in particular, a method for manufacturing
active matrix display devices.
[0003] 2. Description of the Related Art
[0004] Heretofore, liquid crystal display devices utilizing, as
switching elements, TFTs each formed using amorphous silicon have
been often used as display devices which have been widely used,
such as liquid crystal televisions, displays of personal computers,
and cellular phones. A technique by which a TFT is formed using a
semiconductor thin film formed over a substrate having an
insulating surface has attracted attention. The TFT has been widely
applied to electronic devices such as ICs and electro-optical
devices and particularly developed as a switching element of an
image display device.
[0005] For a TFT using amorphous silicon, a layered structure has
been conventionally formed through a photolithography process using
five or more photomasks. Reduction in photolithography process
using photomasks has been desired. Heretofore, each of Patent
Document 1 (Japanese Published Patent Application No. 2000-131719)
and Patent Document 2 (Japanese Published Patent Application No.
2003-45893) has been known as a technique achieving reduction in
number of steps in a photolithography process using photomasks.
[0006] FIGS. 10A to 10E are structural views illustrating a
conventional TFT using amorphous silicon.
[0007] The manufacturing process thereof is described, A gate
electrode 501 is formed over a glass substrate 500 by a
photolithography step using a first photomask (FIG. 10A).
[0008] A gate insulating film 502, an i-type amorphous silicon
layer 503, and an n.sup.+-type amorphous silicon layer 504 are
formed. The i-type amorphous silicon layer 503 and the n.sup.+-type
amorphous silicon layer 504 form an island region by a
photolithography step using a second photomask (FIG. 10B).
[0009] A source electrode 508 and a drain electrode 509 are formed
by a photolithography step using a third photomask. At that time, a
photoresist formed by the third photomask is successively utilized
to etch the n.sup.+-type amorphous silicon layer so that a channel
region 505, a source region 506, and a drain region 507 are
formed.
[0010] A protective film 510 is formed, and a contact hole through
which a contact with a pixel electrode 511 is made is formed by a
photolithography step using a fourth photomask (FIG. 1C).
[0011] Indium tin oxide (ITO) is formed, and the pixel electrode
511 is formed by a photolithography step using a fifth photomask
(FIGS. 10D and 10E).
[0012] Photolithography steps using a photomask includes
application of a photoresist, pre-baking, a step of light exposure
using a metal photomask, a step of development, post-baking, a step
of etching, a step of resist separation, and the like. In addition,
many steps such as a step of cleaning and a step of inspection are
included in the photolithography steps. Thus, performing the
conventional process using five photomasks means that the steps are
repeated five times, which is a significant factor in the decrease
in throughput in the manufacturing process or the increase in
manufacturing cost.
SUMMARY OF THE INVENTION
[0013] Therefore, reduction in number of photomasks means reduction
in manufacturing time and manufacturing cost and thus has been
anticipated. In view of mass production, reduction in number of
photomasks has been a major object. Further, reduction in number of
steps is another object.
[0014] In order to achieve the above objects, the present invention
adopts a channel-etched bottom gate TFT structure in which a
photoresist is selectively exposed to light by rear surface
exposure utilizing a gate wiring to form a desirably patterned
photoresist, and further, in which a halftone mask or a gray-tone
mask is used as a multi-tone mask. Further, the present invention
includes a step of lifting off using a halftone mask or a gray-tone
mask and a step of performing a reflow process on a photoresist.
The step of lifting off is a method in which a pattern other than a
target pattern is formed of a photoresist or the like over a
substrate, a target thin film is formed, and then an unnecessary
portion which overlaps with the photoresist and the photoresist are
removed together so that the target pattern is left. The reflow
process is a step of processing a photoresist over a substrate by
heat treatment or chemical treatment. By repeating combination of
the step of lifting off and mask alignment, a thin film of which
thickness partially varies or a thin film in which substances
partially vary can be patterned.
[0015] According to an aspect of the present invention, a method
for manufacturing a semiconductor device includes the steps of
forming a first conductive film over a substrate; etching the first
conductive film using a first photoresist to form a gate electrode;
forming a gate insulating film over the gate electrode; forming a
first semiconductor layer (e.g. an i-type semiconductor layer) over
the gate insulating film; forming a second semiconductor layer
including the impurity element imparting one conductivity type
(e.g. an n.sup.+-type semiconductor layer) over the first
semiconductor layer; performing rear surface exposure to form a
second photoresist; etching the first semiconductor layer and the
second semiconductor layer to form a first semiconductor island and
a second semiconductor island using the second photoresist; forming
a second conductive film over the second semiconductor island;
forming a third photoresist using a multi-tone mask; etching the
second conductive film, the second semiconductor island, and the
first semiconductor island using the third photoresist; ashing the
third photoresist; etching the second conductive film using the
third photoresist having been ashed to form a source electrode and
a drain electrode; etching the second semiconductor island and the
first semiconductor island using the third photoresist having been
ashed to form a channel region, a source region, and a drain
region; forming an insulating film over the source electrode and
the drain electrode; forming a contact hole in the insulating film
using a fourth photoresist; forming a conductive film over the
insulating film; and etching the conductive film using a fifth
photoresist to form a pixel electrode.
[0016] According to another aspect of the present invention, a
method for manufacturing a semiconductor device includes the steps
of forming a first conductive film over a substrate; etching the
first conductive film using a first photoresist to form a gate
electrode; forming a gate insulating film over the gate electrode;
forming a first semiconductor layer (e.g. an i-type semiconductor
layer) over the gate insulating film; forming a second
semiconductor layer including the impurity element imparting one
conductivity type (e.g. an n.sup.+-type semiconductor layer) over
the first semiconductor layer; performing rear surface exposure to
form a second photoresist; etching the first semiconductor layer
and the second semiconductor layer to form a first semiconductor
island and a second semiconductor island using the second
photoresist; forming a second conductive film over the second
semiconductor layer; forming a third photoresist using a first
multi-tone mask; etching the second conductive film, the second
semiconductor layer, and the first semiconductor layer using the
third photoresist; ashing the third photoresist; etching the second
conductive film using the third photoresist having been ashed to
form a source electrode and a drain electrode; etching the second
semiconductor layer and the first semiconductor layer using the
third photoresist having been ashed to form a channel region, a
source region, and a drain region; forming a fourth photoresist
using a second multi-tone mask; forming a contact hole in the gate
insulating film using the fourth photoresist; ashing the fourth
photoresist; forming a conductive film over the fourth photoresist
having been ashed; removing the fourth photoresist having been
ashed and the conductive film formed over the fourth photoresist
together to form a pixel electrode; forming an insulating film over
the pixel electrode; performing rear surface exposure to form a
fifth photoresist over the insulating film; performing a reflow
process on the fifth photoresist; and etching the insulating film
using the fifth photoresist having been subjected to the reflow
process.
[0017] Owing to the advantageous effect of the present invention,
whereas a conventional amorphous silicon TFT is manufactured using
five photomasks, a TFT can be manufactured using four or three
photomasks and thus manufacturing time and cost can be reduced.
Further, since rear surface exposure is performed, a self-aligning
step is performed and thus a step of aligning the photomask is not
required. In the self-aligning step, it doesn't occur that the
photomask is out of position; therefore, a margin for misalignment
is not required and a more refined pattern can be formed. Further,
a channel region is protected from light from external by a gate
electrode, so that an increase of a leakage current when the TFT is
off can be suppressed.
[0018] Further, by adopting a reflow process, the TFT is entirely
covered with an insulating film and thus reliability of elements
can be improved. That is, an end portion of a source electrode can
be surely covered so that a TFT can be prevented from being
contaminated. An i-type amorphous silicon layer, an n.sup.+-type
amorphous silicon layer, a source metal, and a drain metal are
etched all at once by the conventional halftone technique.
Therefore, the i-type amorphous silicon layer is connected between
the elements. Meanwhile, in the present invention, before formation
of a source metal and a drain metal, only an i-type amorphous
silicon layer and an n.sup.+-type amorphous silicon layer are
formed into an island region by using a photoresist patterned
desirably by rear surface exposure; therefore, the i-type amorphous
silicon layer is cut and thus the elements can be more surely
separated from each other.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In the accompanying drawings:
[0020] FIGS. 1A to 1E are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0021] FIGS. 2A to 2D are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0022] FIGS. 3A to 3C are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0023] FIG. 4 is a cross-sectional view illustrating a method for
manufacturing a semiconductor device of the present invention;
[0024] FIGS. 5A and 5B are a top plan view and a cross-sectional
view illustrating a method for manufacturing a semiconductor device
of the present invention, respectively;
[0025] FIGS. 6A to 6E are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0026] FIGS. 7A to 7D are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0027] FIGS. 8A to 8C are cross-sectional views illustrating a
method for manufacturing a semiconductor device of the present
invention;
[0028] FIGS. 9A to 9D are cross-sectional views each illustrating a
periphery of a pixel portion of a semiconductor device of the
present invention;
[0029] FIGS. 10A to 10E are cross-sectional views illustrating a
method for manufacturing a conventional semiconductor device;
[0030] FIGS. 11A to 11C are diagrams each illustrating a
semiconductor device of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0031] Embodiment modes of the present invention will be described
below.
[0032] The present invention relates to a semiconductor device
manufactured using four or three photomasks to reduce the number of
steps in the conventional process using five photomasks and a
manufacturing method thereof.
[0033] FIGS. 1A to 1E, FIGS. 2A to 2D, FIGS. 3A to 3C, FIG. 4,
FIGS. 5A and 5B, FIGS. 6A to 6E, FIGS. 7A to 7D, FIGS. 8A to 8C,
and FIGS. 9A to 9D are views each illustrating a manufacturing
method of the present invention.
[0034] In this embodiment mode, a photoresist is selectively
exposed to light by rear surface exposure using a gate wiring
material as a photomask to obtain a desired pattern so that an
island region is formed. Further, a channel region, a source
region, a drain region, a source wiring, and a drain wiring are
formed by a halftone exposure technique. Although a halftone
exposure technique is used in this embodiment mode, a gray tone
exposure technique may be used. The combination of the features
enables the process using four photomasks which is fewer than five
photomasks used for the conventional process. Further, by using a
halftone exposure technique, the process using three photomasks
becomes possible.
Embodiment Mode 1
[0035] The process using four photomasks of the present invention
will be described with reference to FIGS. 1A to 1E, FIGS. 2A to 2D,
and FIGS. 3A to 3C.
[0036] In FIG. 1A, a metal film is stacked over a glass substrate
100 by a sputtering method. The glass substrate is allowable as
long as it has a light transmitting property. Barium borosilicate
glass or aluminoborosilicate glass, which is typified by the No.
7059 or No. 1737 glass manufactured by Corning Inc., may be used.
Alternatively, a light-transmitting substrate such as a quartz
substrate or a plastic substrate may be used. A first photomask is
used to form a desired photoresist and then the metal film is
etched, so that a gate electrode 101 and a gate wiring are formed.
The gate electrode 101 and the gate wiring are desirably formed of
a low resistant conductive material such as aluminum (Al) or copper
(Cu); however, since aluminum alone has disadvantages such as low
heat resistance and a tendency to be corroded, it is used in
combination with a material having both heat resistance and
conductivity to form the gate electrode 101 and the gate wiring. An
AgPdCu alloy may be used as a low resistant conductive material. As
a material having both heat resistance and conductivity, an element
selected from titanium (Ti), tantalum (Ta), tungsten (W),
molybdenum (Mo), chromium (Cr), and neodymium (Nd), an alloy
containing any of the above elements as its component, an alloy
film combining any of the above elements, or nitride containing any
of the above elements as its component. The gate electrode and the
gate wiring comprise a conductive film containing any of the above
elements or a layered structure of the abovementioned conductive
films. For example, a stack of titanium and copper or a stack of
tantalum nitride and copper can be used. In the case where a low
resistant conductive material is used in combination with a
material having both heat resistance and conductivity such as
titanium, silicon, chromium, or neodymium, flatness is improved,
which is preferable. Alternatively, only such materials having both
heat resistance and conductivity, for example, molybdenum and
tungsten, may be used in combination.
[0037] In FIG. 1B, an insulating film 102, an i-type amorphous
silicon layer 103, and an n.sup.+-type amorphous silicon layer 104
are sequentially formed over the gate electrode 101. The insulating
film 102 is to form the gate insulating film 102 later and formed
to have, for example, a single-layer structure of a silicon nitride
film, a silicon oxide film, or a silicon oxynitride film or a
layered structure of any of the above films. It is needless to say
that the material of the gate insulating film is not limited to the
above materials and may have a single-layer or layered structure
using any other insulating film such as a tantalum oxide film. The
i-type amorphous silicon layer 103 and the n.sup.+-type amorphous
silicon layer 104 are to form a channel region, a source region,
and a drain region later. The i-type amorphous silicon layer 103 is
a non-doped layer which does not contain an impurity imparting
conductivity. The i-type amorphous silicon layer 103 may contain a
very small amount of impurities. Also, the n.sup.+-type amorphous
silicon layer 104 is a semiconductor film containing an impurity
element imparting one conductivity type, in particular, an n-type
semiconductor layer containing phosphorus at high concentration.
The insulating film 102, the i-type amorphous silicon layer 103,
and the n.sup.+-type amorphous silicon layer 104 are formed by a
CVD method. A multi-chamber CVD apparatus enables even successive
film formation. They are thus formed by not being exposed to the
air, so that an impurity is prevented from being mixed. Although a
CVD method is used in this embodiment mode, a sputtering method or
the like may alternatively be used.
[0038] In FIG. 1C, a photoresist 121 formed over the n.sup.+-type
amorphous silicon layer 104 is selectively exposed to light by rear
surface exposure with the metal film of the gate electrode 101 and
the gate wiring as a photomask, so that a desirable photoresist
pattern is formed. By rear surface exposure, light transmits a thin
film and the photoresist 121 is exposed to light; therefore, the
layers other than the gate wiring 101, that is, the i-type
amorphous silicon layer 103 and the n.sup.+-type amorphous silicon
layer 104 are necessarily thin enough to be exposed to light. That
is to say, light transmits the i-type amorphous silicon layer 103
and the n.sup.+-type amorphous silicon layer 104 to expose the
photoresist 121. By using the photoresist pattern formed by rear
surface exposure, the i-type amorphous silicon layer 103 and the
n.sup.+-type amorphous silicon layer 104 are etched to form an
i-type amorphous silicon island 123 and an n.sup.+-type amorphous
silicon island 124 as shown in FIG. 1D. In the case of performing
rear surface exposure, a self-aligning step is performed and thus a
step of aligning the photomask is not required, so that etching can
be performed in a self-aligned manner while the photoresist pattern
after exposure is not misaligned.
[0039] In FIG. 1E, a metal film 105 is formed over an entire
surface of the substrate. The metal film 105 is to form a source
electrode, a drain electrode, and a source wiring later. The
material of the metal film 105 is allowable as long as it is a
metal material which can provide ohmic contact with the
n.sup.+-type amorphous silicon island 124, and an element selected
from aluminum, chromium, tantalum, and titanium, an alloy
containing any of the above elements as its component, an alloy
film combining any of the above elements, and the like are
given.
[0040] In FIG. 2A, a photoresist 1 is formed using a second
photomask. For the photoresist 1, a halftone exposure technique is
used. That is, a photoresist of which thickness varies is formed.
Parts which are to form a source electrode, a drain electrode, and
a source wiring are formed thick and a part which is to form a
channel is formed thin.
[0041] In FIG. 2B, etching is performed using the photoresist 1.
Thus, a wiring 106 is formed.
[0042] In FIG. 2C, the photoresist 1 is subjected to ashing
treatment to be processed such that the shape of the photoresist 1
is like that of a photoresist 2 of FIG. 2C. That is, the part of
the photoresist, which has been formed thin, is exposed.
[0043] In FIG. 2D, the photoresist 2 which has been processed by
ashing is used to etch the metal film 105 so that the source
electrode 110 and the drain electrode 111 are formed. Similarly,
the photoresist 2 is used to etch the n.sup.+-type amorphous
silicon island 124 and the i-type amorphous silicon island 123 so
that a channel region 107, a source region 108, and a drain region
109 are formed. The i-type amorphous silicon layer which overlaps
with the gate electrode 101 with the gate insulating film 102
interposed therebetween forms a channel formation region 107. After
that, the photoresist 2 is removed by separation.
[0044] In FIG. 3A, an insulating film is formed over an entire
surface of the substrate to serve as a protective film 112. The
insulating film serving as the protective film may be a silicon
nitride film, a silicon oxide film, or a stack of the films. The
silicon nitride film is particularly preferred because of high
passivation performance thereof.
[0045] In FIG. 3B, an opening of a contact portion, which exposes
the drain electrode 111, is formed by a photoresist 3 formed using
a third photomask.
[0046] In FIG. 3C, ITO is formed over an entire surface of the
substrate, a desired photoresist is formed using a fourth
photomask, and a pixel electrode 113 is formed using the
photoresist. Although ITO is used as a pixel electrode material in
this embodiment mode, tin oxide, indium oxide, nickel oxide, zinc
oxide, or a compound of any of the above may be used as a
transparent conductive material, for example.
[0047] Although the i-type amorphous silicon layer is used as a
channel region 107 in this embodiment mode, it is also possible
that a microcrystal semiconductor film (also referred to as a
semi-amorphous semiconductor film) be formed, a buffer layer be
formed over the microcrystal semiconductor film, and an
n.sup.+-type amorphous silicon layer be formed over the buffer
layer. The buffer layer may be an amorphous silicon layer and
preferably contains one or more of nitrogen, hydrogen, and halogen.
The amorphous silicon layer contains any one or more of nitrogen,
hydrogen, and halogen, so that a crystal grain contained in the
microcrystal semiconductor film can be prevented from being
oxidized. The buffer layer is formed between the source region and
the drain region; therefore, a TFT has higher mobility, a smaller
amount of leakage current, and a higher withstand voltage.
[0048] FIG. 4 illustrates a TFT in which a microcrystalline
semiconductor film 201 and a buffer layer 202 are formed in this
order as a channel region instead of the i-type amorphous silicon
layer. By using the microcrystalline semiconductor film 201 and the
buffer layer 202 instead of the i-type amorphous silicon layer, the
TFT can be formed to have higher mobility, a smaller amount of
leakage current, and a higher withstand voltage.
[0049] FIG. 5A illustrates a top plan view of the TFT of this
embodiment mode. Note that the same reference numerals are used for
the parts corresponding to those in FIGS. 1A to 1E, FIGS. 2A to 2D,
and FIGS. 3A to 3C. FIG. 5B corresponds to a cross sectional view
taken along line A-A' in FIG. 5A.
[0050] Thus, inverted-staggered n-channel TFTs can be completed
through the photolithography process using four photomasks. Then,
they are arranged in matrix corresponding to pixels so that a pixel
portion is formed, which can be a substrate for fabricating an
active matrix electrooptic device.
Embodiment Mode 2
[0051] Next, the process using three photomasks of the present
invention will be described with reference to FIGS. 6A to 6E, FIGS.
7A to 7D, and FIGS. 8A to 8C. Description will be made including
that of a terminal portion from a step using the second photomask,
which requires a halftone exposure technique in FIG. 1E. That is,
the step in FIG. 6A follows the step in FIG. 1E.
[0052] In FIG. 6A, a photoresist 4 is formed, using the second
photomask, over a glass substrate 100, a gate electrode 101, a
wiring 311, an insulating film 102, an i-type amorphous silicon
layer 123, a semiconductor layer including an impurity element
imparting one conductivity type, which is particularly an n.sup.+
amorphous silicon layer 124, and a metal layer 105. For the
photoresist 4, a halftone exposure technique is used. That is, a
photoresist of which thickness varies is formed. Parts which are to
form a drain electrode and a source wiring are formed thick and a
part which is to form a channel is formed thin.
[0053] In FIG. 6B, parts of the i-type amorphous silicon layer 303,
the n.sup.+-type amorphous silicon layer 304, and the metal film
105, which are not covered with the photoresist 4, are etched.
[0054] In FIG. 6C, the photoresist 4 is processed by ashing to form
a photoresist 5.
[0055] In FIG. 6D, a source electrode 309 and a drain electrode 310
are formed using the photoresist 5 processed by ashing. Similarly,
a channel region 306, a source region 307, and a drain region 308
are formed using the photoresist 5. After that, the photoresist 5
is removed. The i-type amorphous silicon layer 123 which overlaps
with the gate electrode with the gate insulating film interposed
therebetween forms the channel region 306.
[0056] In FIG. 6E, a photoresist 6 is formed using a third
photomask. A halftone exposure technique is also used here. Part of
the insulating film 102, which is not covered with the photoresist
6, is etched to form a contact hole 321 so that a wiring 311 is
exposed. The wiring 311 may comprise a single layer or a layered
structure using aluminum (Al), copper (Cu), titanium (Ti), tantalum
(Ta), tungsten (W), molybdenum (Mo), chromium (Cr), and neodymium
(Nd). This exposed part forms a connection portion with a
transparent conductive film on the terminal portion.
[0057] In FIG. 7A, the photoresist 6 is processed by ashing to form
a photoresist 7.
[0058] In FIG. 7B, a transparent conductive film 312 is formed over
the photoresist 7.
[0059] In FIG. 7C, the photoresist 7 and portions of the
transparent conductive film 312 formed on the photoresist 7 are
removed together by a step of lifting off, so that a pixel
electrode 313 and a wiring 320 are formed. After that, a protective
film 314 is formed over an entire surface of the substrate by a CVD
method. An insulating film which serves as the protective film may
be a silicon nitride film, a silicon oxide film, or a stack of
them. A silicon nitride film is particularly preferred because of
high passivation performance thereof.
[0060] In FIG. 7D, a photoresist is applied to the protective film
314 and selectively exposed to light by rear surface exposure, so
that a desirably patterned photoresist 8 is formed. Here, the
photoresist 8 is not formed over only transparent films, that is,
part including only the transparent conductive film 312 and the
insulating film 302 because light is transmitted. Since rear
surface exposure is performed, it is preferable that the gate
electrode 301, the source electrode 309, and the drain electrode
310 sufficiently overlap with each other in the channel region.
[0061] In FIG. 8A, the photoresist 8 formed by the rear surface
exposure is subjected to heat treatment as a reflow process. And
when seen in section, the photoresist 8 forms a photoresist 9 such
that an end portion of the photoresist 8 is extended slightly
outward. Further, the photoresist 8 is reduced in thickness to form
the photoresist 9 by the reflow process. Although not illustrated,
a range of the photoresist 8, which covers the substrate, is
slightly increased when seen from the top surface, so that the
photoresist 9 is formed. That is, the distance between the edge of
the photoresist and the edge of the source electrode and the
distance between the edge of the photoresist and the edge of the
drain electrode are increased. As the reflow process, chemical
treatment may be performed instead of heat treatment.
[0062] In FIG. 8B, the protective film 314 is etched using the
photoresist 9 formed by slightly extending an end portion of the
photoresist 8 outward and thus reducing the photoresist 8 in
thickness, so that the pixel electrode 313 is partly exposed. The
exposed region forms a pixel region. By the reflow process, the end
portion of the photoresist 8 is extended slightly outward.
Therefore, the protective film 324 after etching is extended so
that outer sides of the end portions of the source electrode and
the drain electrode can be protected. Thus, a TFT or an electrode
in a lower layer can be more surely protected. Further, in a
peripheral portion, the contact hole 321 can be surely protected by
the protective film 325.
[0063] FIG. 8C is a view in the case where an LCD panel is
manufactured using a TFT substrate in FIG. 8B. A counter substrate
319 is provided to face the glass substrate 100 over which TFTs are
formed. The counter substrate 319 is provided with a color filter
318. A liquid crystal 315 and a spacer 316 are provided between the
glass substrate 100 and the counter substrate 319 and are sealed
with a sealant 317.
[0064] Thus, inverted-staggered n-channel TFTs can be completed
through the photolithography process using three photomasks. Then,
they are arranged in matrix corresponding to pixels so that a pixel
portion is formed, which can be a substrate for fabricating an
active matrix electrooptic device.
Embodiment Mode 3
[0065] Next, the structure of a connection terminal portion
connected to a peripheral circuit provided on the periphery of a
pixel portion will be described taking FIGS. 9A to 9D as an
example.
[0066] FIGS. 9A and 9B each illustrate a structure in the case
where a source wiring is lead to an end portion of a substrate.
FIG. 9A illustrates the case of Embodiment Mode 1 and FIG. 9B
illustrates the case of Embodiment Mode 2. Note that the same
reference numerals are used for the parts corresponding to those in
FIGS. 1A to 1E, FIGS. 2A to 2D, FIGS. 3A to 3C, FIG. 4, FIGS. 5A
and 5B, FIGS. 6A to 6E, FIGS. 7A to 7D, and FIGS. 8A to 8C. In the
case of FIG. 9A, the protective film 112 is etched using the
photoresist 3 in FIG. 3B to expose the wiring 106 so that the
wiring 106 is in contact with the transparent conductive film 114.
In the case of FIG. 9B, the metal film 105 and the transparent
conductive film 312 are made to be in contact with each other using
the photoresist 7 in FIG. 7B. Then, the protective film 314 is
etched using the photoresist 9 to expose the transparent conductive
film 312. The transparent conductive films 114 and 312 form
connection terminals and are each connected to an FPC (flexible
printed circuit) with a conductive adhesive such as an anisotropic
conductive film interposed therebetween.
[0067] FIGS. 9C and 9D each illustrate a structure in the case
where a gate wiring is lead to an end portion of a substrate. FIG.
9C illustrates the case of Embodiment Mode 1 and FIG. 9D
illustrates the case of Embodiment Mode 2. Note that the same
reference numerals are used for the parts corresponding to those in
FIGS. 1A to 1E, FIGS. 2A to 2D, FIGS. 3A to 3C, FIG. 4, FIGS. 5A
and 5B, FIGS. 6A to 6E, FIGS. 7A to 7D, and FIGS. 8A to 8C. In the
case of FIG. 9C, the gate insulating film 102 is exposed using the
photoresist 1 in FIG. 2B, and the gate insulating film 102 and the
protective film 112 are etched using the photoresist 3 in FIG. 3B
so that the gate wiring is in contact with the transparent
conductive film 114. In the case of FIG. 9D, the gate electrode 301
is exposed using the photoresist 6 in FIG. 6E, and the gate
electrode 301 and the transparent conductive film 312 are made to
be in contact with each other using the photoresist 7 in FIG. 7B.
Then, the protective film 314 is etched using the photoresist 9 to
expose the transparent conductive film 312.
[0068] Thus, a semiconductor device can be manufactured by the
process using four or three photomasks, in which the number of
photomasks is reduced and the number of steps is also reduced, as
compared to the conventional process using five photomasks.
[0069] FIGS. 11A to 11C illustrate a television set, a portable
information terminal (such as a mobile computer, a cellular phone,
a mobile game console, or an electronic book), and a laptop
computer, respectively, as examples of a semiconductor device and
an electronic appliance of the present invention.
[0070] FIG. 11A illustrates a display device including a housing
1001, a display portion 1002, speakers 1003, a video input terminal
1004, a supporting base 1005, and the like. The display device is
manufactured using TFTs formed by the manufacturing method
described in any of the aforementioned embodiment modes for the
display portion 1002 and a driver circuit thereof. Note that as the
display device, a liquid crystal display device, a light emitting
device, and the like are given. Specifically, the display device
includes all display devices for information display, such as those
for computers, television broadcasting reception, and advertisement
display. According to the present invention, an inexpensive and
highly reliable display device can be realized.
[0071] A cellular phone illustrated in FIG. 11B includes control
switches 2001, a display portion 2002, and the like. According to
the present invention, an inexpensive and highly reliable cellular
phone can be realized.
[0072] FIG. 11C illustrates a laptop personal computer including a
main body 3001, a display portion 3002, and the like. According to
the present invention, an inexpensive and highly reliable laptop
personal computer can be realized.
[0073] This application is based on Japanese Patent Application
serial no. 2007-275781 filed with Japan Patent Office on Oct. 23,
2007, the entire contents of which are hereby incorporated by
reference.
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