Floating Gate of Flash Memory Device and Method of Forming the Same

Abstract

Disclosed is a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.

Description

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application is a divisional of U.S. patent application Ser. No. 11/647,021, filed Dec. 27, 2006, pending, which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a floating gate and a method of forming the same.

[0004] 2. Description of the Related Art

[0005] A flash memory is a kind of nonvolatile memory. Applications of the flash memory have been extended, and a chip integration density of the flash memory has also been improved.

[0006] Products in which a flash memory is embedded in a general logic have been applied in various fields. Accordingly, it is a problem to reduce manufacturing costs and power consumption.

[0007] To reduce manufacturing costs, a chip size must be reduced and a process must be simplified. However, the chip size has been currently reduced down to 0.10 .mu.m with the rapid development of a photo process in accordance with a design rule.

[0008] Further, production costs can be reduced not only by simplifying a process but also by eliminating a process in which failure may occur in view of a yield.

[0009] Meanwhile, in a design of a flash memory device, a floating gate requires high capacitance for the purpose of coupling a higher floating gate voltage from a control gate.

[0010] As a method for obtaining high capacitance as described above, there are methods of increasing an overlap between floating and control gates, utilizing a material with an interlayer dielectric constant, reducing the thickness of an interlayer dielectric layer, and the like.

[0011] The method of utilizing a material with an interlayer dielectric constant or reducing the thickness of an interlayer dielectric layer has a disadvantage in that a leakage current is large.

[0012] Therefore, the method of increasing an overlap between floating and control gates is mainly used to obtain high capacitance. However, the method of increasing an overlapping area has a disadvantage in that a cell area is increased.

[0013] As a method for solving these disadvantages, there is a method of increasing an overlapping area of a sidewall rather than that of a plan, which causes many problems in view of planarization.

[0014] One of such area increasing methods is a method of allowing the shape of a floating gate to be uneven.

[0015] That is, there is a method in which a floating gate is primarily formed, and a mask process is then performed such that the interior of the floating gate is removed by a predetermined thickness, thereby allowing the shape of the floating gate to be uneven.

[0016] In this case, the capacitance of a floating gate is increased in accordance with the increase of an area due to unevenness, and thus the coupling ratio of a flash memory is increased.

[0017] However, there is a problem in that a mask process must be performed twice in such a method, i.e., a process is complicated and manufacturing costs are increased.

SUMMARY OF THE INVENTION

[0018] The present invention has been made to solve the above mentioned problem occurring in the prior art, and it is an object of the present invention to provide a floating gate of a flash memory device and a method of forming the same, wherein the area of the floating gate is extended, and a coupling ratio is increased.

[0019] According to one aspect of the present invention, there is provided a floating gate of a flash memory device, wherein a tunneling oxide layer is formed on a semiconductor substrate, and a floating gate is formed in the shape of a lens having a convex top surface.

[0020] According to another aspect of the present invention, there is provided a method of forming a floating gate in a flash memory device, which includes the steps of: forming a tunneling oxide layer on a semiconductor substrate; forming a conductive layer on the tunneling oxide layer; coating a photoresist layer on the conductive layer and then selectively patterning the photoresist layer, thereby defining a floating gate area; selectively removing the conductive layer by a predetermined thickness from a top surface of the conductive layer by using the patterned photoresist layer as a mask; performing a thermal process with respect to the photoresist layer, thereby, reflowing the photoresist layer with the shape of a lens having a convex top surface; and simultaneously etching the photoresist layer subjected to reflowing and the conductive layer, thereby forming a floating gate with the shape of a lens having a convex top surface.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] FIG. 1 is a sectional view showing a floating gate of a flash memory device according to the present invention; and

[0022] FIGS. 2A to 2E are sectional views illustrating a process of forming a floating gate in a flash memory device according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, a floating gate of a flash memory device and a method of forming the same according to the present invention will be described in detail with reference to the accompanying drawings.

[0024] FIG. 1 is a sectional view showing a floating gate of a flash memory device according to the present invention.

[0025] As shown in FIG. 1, a tunneling oxide layer 102 is formed on a semiconductor substrate 101, and a floating gate is formed in the shape of a lens having a convex top surface.

[0026] FIGS. 2A to 2E are sectional views illustrating a process of forming a floating gate in a flash memory device according to the present invention.

[0027] As shown in FIG. 2A, a tunneling oxide layer 102 is formed in a thickness of 80 to 120 .ANG. on a semiconductor substrate 101, and a poly-silicon layer 103 is formed in a thickness of 900 to 1100 .ANG. on the tunneling oxide layer 102.

[0028] Here, the poly-silicon 103 may be formed by allowing the thickness of the poly-silicon layer 103 to be adjusted depending on etching selectivity with a photoresist layer to be coated later.

[0029] As shown in FIG. 2B, a photoresist layer 104 is coated on an entire surface of the semiconductor substrate 101 having the poly-silicon layer 103, and the photoresist layer 104 is selectively patterned through an exposure and development process, thereby defining a floating gate area.

[0030] Here, after the photoresist layer 104 has been coated, an antireflective coating (not shown) may be formed in a thickness of about 600 .ANG..

[0031] Meanwhile, in a method of coating the photoresist layer 104, there are methods of spin coat, spray coat, dip coat and the like. However, the spin coat performed while chucking and rotating a wafer at a high speed under a vacuum atmosphere is advantageous to stability and uniformity.

[0032] Then, a photo mask (not shown) corresponding to a desired pattern is positioned on the photoresist layer 104, and a photoresist pattern is then formed to have a desired size through exposure and development processes.

[0033] Here, the development process is performed through deposition or spraying. In the former, it is difficult to manage a temperature, a density, a change in time and the like, while, in the latter, it is relatively easy to manage. Currently, an apparatus subjected to in-line through a spraying scheme has been widely used.

[0034] As shown in FIG. 2C, the poly-silicon layer 103 is selectively removed by a predetermined thickness from a top surface thereof by using the patterned photoresist layer 104 as a mask.

[0035] Here, the thickness of the poly-silicon layer 103 removed by the predetermined thickness is about 1/2 of the original thickness of the poly-silicon layer 103.

[0036] As shown in FIG. 2D, a thermal process is performed with respect to the photoresist layer 104 such that the photoresist layer 104 is subjected to reflowing, thereby forming a photoresist layer 104a with the shape of a lens having a convex top surface.

[0037] As shown in FIG. 2E, the photoresist layer 104 subjected to reflowing and the residual poly-silicon layer 103 are simultaneously etched at etching selectivity of 1:1, thereby forming a floating gate 105 with the shape of a lens having a convex top surface.

[0038] Subsequently, after the floating gate 105 has been formed, the residual photoresist layer 104 and impurities are removed, and a washing process is performed.

[0039] As described above, a floating gate of a flash memory device and a method of forming the same according to the present invention has advantages as follows.

[0040] That is, a floating gate is formed in the shape of a lens having a convex top surface through a simple process, so that the area of the floating gate can be extended, and a coupling ratio can be increased.

[0041] It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention. Thus, it is intended that the present invention covers the modifications and variations thereof within the scope of the appended claims.

Claims

1. A floating gate of a flash memory device, comprising: a tunneling oxide layer on a semiconductor substrate; a floating gate having a lens shape and a convex top surface; a gate oxide on the floating gate; and a concave control gate on the gate oxide.

2. The nonvolatile memory device of claim 1, wherein the gate oxide and the control gate have a shape complementary to that of the floating gate.

3. The nonvolatile memory device of claim 1, wherein the gate oxide and the control gate also have a shape effective to increase the capacitance or coupling ratio between the floating gate and the control gate, relative to an otherwise identical nonvolatile memory having a planar floating gate.

4. The nonvolatile memory device of claim 1, wherein the floating gate has a width of from 45 nm to 150 nm.

5. The nonvolatile memory device of claim 4, wherein the floating gate width is less than or equal to 100 nm.

6. The nonvolatile memory device of claim 2, wherein the control gate has a width greater than that of the floating gate, and portions of the floating gate extend along sidewalls of the floating gate.

7. A nonvolatile memory device, comprising: a tunnel oxide layer on a semiconductor substrate; a floating gate on the tunnel oxide layer having a convex top surface; a gate oxide on the floating gate; and a control gate on the gate oxide.

8. The nonvolatile memory device of claim 8, wherein the floating gate has a shape effective to increase a capacitance or a coupling ratio between the floating gate and the control gate.

9. The nonvolatile memory device of claim 9, wherein the gate oxide and the control gate have a shape complementary to that of the floating gate.

10. The nonvolatile memory device of claim 8, wherein the gate oxide and the control gate also have a shape effective to increase the capacitance or coupling ratio between the floating gate and the control gate, relative to an otherwise identical nonvolatile memory having a planar floating gate.

11. The nonvolatile memory device of claim 8, wherein the floating gate has a width of from 45 nm to 150 nm.

12. The nonvolatile memory device of claim 12, wherein the floating gate width is less than or equal to 100 nm.

13. The nonvolatile memory device of claim 9, wherein the control gate has a width greater than that of the floating gate, and portions of the floating gate extend along sidewalls of the floating gate.