U.S. patent application number 12/250526 was filed with the patent office on 2009-05-21 for semiconductor device and manufacturing method of the same.
This patent application is currently assigned to RENESAS TECHNOLOGY CORP.. Invention is credited to Toshifumi IWASAKI, Yoshihiko Kusakabe.
Application Number | 20090127627 12/250526 |
Document ID | / |
Family ID | 40640983 |
Filed Date | 2009-05-21 |
United States Patent
Application |
20090127627 |
Kind Code |
A1 |
IWASAKI; Toshifumi ; et
al. |
May 21, 2009 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
Abstract
A semiconductor device capable of improving the driving power
and a manufacturing method therefor are provided. In a
semiconductor device, a gate structure formed by successively
stacking a gate oxide film and a silicon layer is arranged over a
semiconductor substrate. An oxide film is arranged long the lateral
side of the gate structure and another oxide film is arranged along
the lateral side of the oxide film and the upper surface of the
substrate. In the side wall oxide film comprising these oxide
films, the minimum value of the thickness of the first layer along
the lateral side of the gate structure is less than the thickness
of the second layer along the upper surface of the substrate.
Inventors: |
IWASAKI; Toshifumi; (Tokyo,
JP) ; Kusakabe; Yoshihiko; (Tokyo, JP) |
Correspondence
Address: |
MILES & STOCKBRIDGE PC
1751 PINNACLE DRIVE, SUITE 500
MCLEAN
VA
22102-3833
US
|
Assignee: |
RENESAS TECHNOLOGY CORP.
|
Family ID: |
40640983 |
Appl. No.: |
12/250526 |
Filed: |
October 13, 2008 |
Current U.S.
Class: |
257/369 ;
257/E21.294; 257/E27.046; 438/595 |
Current CPC
Class: |
H01L 29/6653 20130101;
H01L 21/28052 20130101; H01L 21/823468 20130101; H01L 29/7843
20130101; H01L 27/088 20130101; H01L 29/665 20130101; H01L
21/823412 20130101; H01L 21/823807 20130101 |
Class at
Publication: |
257/369 ;
438/595; 257/E27.046; 257/E21.294 |
International
Class: |
H01L 27/08 20060101
H01L027/08; H01L 21/3205 20060101 H01L021/3205 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 21, 2007 |
JP |
2007-301208 |
Claims
1. A semiconductor device comprising: a gate structure arranged
over a semiconductor substrate; side walls arranged on both lateral
sides of the gate structure; and a stress liner film arranged so as
to cover the gate structure and the side wall, wherein the side
wall has an oxide film with an L-cross sectional shape having a
first layer along the lateral side of the gate structure and a
second layer along the upper surface of the semiconductor
substrate, and wherein the minimum value of the thickness of the
first layer is less than the thickness of the second layer.
2. A semiconductor device according to claim 1, wherein the side
wall further has a nitride film arranged over the second layer.
3. A semiconductor device according to claim 2, wherein the nitride
film comprises a rectangular parallelepiped body in which each of
the bottoms thereof is less than the height thereof.
4. A semiconductor device according to claim 3, wherein the height
for the nitride film is 10 nm or less.
5. A semiconductor device according to claim 2, wherein the nitride
film is arranged in the region for an SPAM, but not arranged in the
region for a logic.
6. A semiconductor device according to claim 1, further including a
silicide layer arranged over the gate structure and the
semiconductor substrate.
7. A semiconductor device according to claim 6, further including
an oxide film arranged over the semiconductor substrate at outside
of the side wall.
8. A manufacturing method of a semiconductor device comprising the
steps of: forming a gate structure over a semiconductor substrate;
forming side walls on both lateral sides of the gate structure; and
forming a stress liner film so as to cover the gate structure and
the side wall, wherein the side wall forming step includes the
steps of: forming a first oxide film along the lateral side of the
gate structure, a second oxide film in an L-cross sectional shape
along the lateral side of the first oxide film and the upper
surface of the semiconductor substrate, and a nitride film along
the second oxide film respectively; and etching the first oxide
film, the second oxide film, and the nitride film with a hot
phosphoric acid, and wherein the second oxide film is removed more
than the first oxide film in the etching step.
9. A manufacturing method of a semiconductor device according to
claim 8, wherein the first oxide film is formed of TEOS and the
second oxide film is formed of USG in the side wall forming
step.
10. A manufacturing method of a semiconductor device according to
claim 8, wherein the side wall forming step further includes the
steps of: etching the semiconductor substrate at the surface of a
region excepting just below the gate structure; and forming a
silicide layer over the gate structure and the semiconductor
substrate.
11. A semiconductor device according to claim 2, further including
a silicide layer arranged over the gate structure and the
semiconductor substrate.
12. A semiconductor device according to claim 11, further including
an oxide film arranged over the semiconductor substrate at outside
of the side wall.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The disclosure of Japanese Patent Application No.
2007-301208 filed on Nov. 21, 2007 including the specification,
drawings and abstract is incorporated herein by reference in its
entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention concerns a semiconductor device and a
manufacturing method of the same and it particularly relates to a
technique of enhancing the driving performance by a stress liner
film.
[0003] In a semiconductor device having a PMOSFET or an NMOSFET, a
structure of providing a stress liner film so as to cover a gate
electrode has been adopted so far. By providing the stress liner
film so as to exert a compressive stress to a channel region in the
PMOSFET and exert a tensile stress to a channel region in the
NMOSFET, the driving performance in the PMOSFET or the NMOSFET can
be enhanced. The stress liner film is formed so as to cover the
gate electrode and the side walls after forming side walls on both
lateral sides of a gate electrode.
[0004] Such semiconductor devices are disclosed, for example, in
Japanese Unexamined Patent Publications Nos. 2006-148077,
2006-173432, and 2007-49166.
SUMMARY OF THE INVENTION
[0005] In the structure of the semiconductor devices of the patent
publications described above, since the stress by the stress liner
film is not always applied sufficiently to the channel region by
way of the side wall, they involve a problem that the driving
performance cannot always be enhanced sufficiently.
[0006] The present invention has been achieved for solving the
foregoing problem and it intends to provide a semiconductor device
capable of enhancing the driving performance and a method of
manufacturing the same.
[0007] In a semiconductor device according to one aspect of the
present invention, a gate structure having a gate oxide film and a
polysilicon layer stacked successively over a substrate is
arranged. A first oxide film is arranged along the lateral side of
the gate structure and a second oxide film is arranged along the
lateral side of the first oxide film and the upper surface of the
substrate. In the side wall oxide film comprising the first oxide
film and the second oxide film, the minimum value of the thickness
of the first layer along the lateral side of the gate structure is
less than the thickness of the second layer along the upper surface
of the substrate.
[0008] According to the invention, a distance between the liner
nitride film and a channel region can be decreased and the stress
by the liner nitride film can be applied sufficiently to a channel
region. Accordingly, the driving performance can be enhanced.
DESCRIPTION OF THE ACCOMPANYING DRAWINGS
[0009] FIG. 1 is a cross sectional view showing the structure of a
semiconductor device according to a basic technique;
[0010] FIG. 2 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0011] FIG. 3 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0012] FIG. 4 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0013] FIG. 5 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0014] FIG. 6 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0015] FIG. 7 is a cross sectional view showing the manufacturing
method of the semiconductor device according to a basic
technique;
[0016] FIG. 8 is a cross sectional view shown an example of a
structure of the semiconductor device according to a first
embodiment;
[0017] FIG. 9 is a cross sectional view shown another example of a
structure of the semiconductor device according to a first
embodiment;
[0018] FIG. 10 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0019] FIG. 11 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0020] FIG. 12 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0021] FIG. 13 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0022] FIG. 14 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0023] FIG. 15 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0024] FIG. 16 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0025] FIG. 17 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0026] FIG. 18 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0027] FIG. 19 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0028] FIG. 20 is a cross sectional view showing a manufacturing
method of the semiconductor device according to a first
embodiment;
[0029] FIG. 21 is a cross sectional view showing another example of
a structure of the semiconductor device according to a first
embodiment;
[0030] FIG. 22 is a cross sectional view showing another example of
a structure of the semiconductor device according to a first
embodiment;
[0031] FIG. 23 is a cross sectional view showing another example of
a structure of the semiconductor device according to a first
embodiment;
[0032] FIG. 24 is a cross sectional view showing another example of
a structure of the semiconductor device according to the first
embodiment;
[0033] FIG. 25A is a cross sectional view showing another example
of the manufacturing method of the semiconductor device according
to the first embodiment;
[0034] FIG. 25B is a cross sectional view showing another example
of the manufacturing method of the semiconductor device according
to the first embodiment; and
[0035] FIG. 25C is a cross sectional view showing another example
of the manufacturing method of the semiconductor device according
to the first embodiment.
PREFERRED EMBODIMENTS OF THE INVENTION
Basic Technique
[0036] FIG. 1 is a cross sectional view showing a structure of a
semiconductor device 500 according to a basic technique. The
semiconductor device 500 according to the basic technique includes
a plurality of PMOSFETs or NMOSFETs, which are isolated into a
plurality of regions by isolation films 20 arranged in a substrate
10 (semiconductor substrate) comprising Si.
[0037] As shown in FIG. 1, in the semiconductor device 500, a gate
structure formed by successively stacking a gate oxide film 31 and
a polysilicon layer 30 is arranged over the substrate 10. A side
wall having an oxide film 40 comprising TEOS (first oxide film) and
an oxide film 50 comprising USG (second oxide film) is arranged on
both lateral sides of the gate structure. That is, the oxide film
40 is arranged along the lateral side of the gate structure, and
the oxide film 50 is arranged along the lateral side of the oxide
film 40 and the upper surface of the substrate 10. As to be
described later, the semiconductor device 500 has a DSW (disposable
Side Wall) structure in which a distance between a liner nitride
film 80 and a channel region is decreased by etching to remove a
nitride film (90) formed along the oxide film 50 in order to form a
source/drain region 60 in the substrate 10 after forming a
source/drain region 60. The oxide films 40, 50 are to be described
hereinafter collectively also as a side wall oxide film. The side
wall oxide film has an L-shaped cross section and has a first layer
along the lateral side of the gate structure and a second layer
along the upper surface of the substrate 10.
[0038] Further, in the substrate 10, the source/drain region 60 is
arranged with a channel region just below the gate structure being
put therebetween.
[0039] Further, a silicide layer 70 is arranged over the gate
structure and the substrate 10. The silicide layer 70 is not
arranged to all of MOSFETs over one identical substrate 10 but is
arranged only to predetermined MOSFETs in which lowering of
resistance is required (in the present specification, only the
MOSFET provided with the silicide layer 70 is shown).
[0040] Further, a liner nitride film 80 (stress liner film) is
arranged over the entire surface so as to cover the gate structure
and the side wall.
[0041] FIG. 2 to FIG. 7 are cross sectional views showing a method
of manufacturing the semiconductor device 500 in FIG. 1.
[0042] At first, as shown in FIG. 2, an isolation film 20 is formed
in the substrate 10. Then, a gate structure is formed according to
a predetermined gate pattern over a substrate 10 (only the
polysilicon layer 30 is shown while saving the gate oxide film 31
for the convenience of illustration). Then, an oxide film 40 is
formed along the lateral surface of the gate structure. Then, an
oxide film 50 along the lateral side of the oxide film 40 and the
upper surface of the substrate 10, and a nitride film 90 along the
oxide film 50 are formed. Then, a source/drain region 60 is formed
in the substrate 10 by implanting impurities from above and
activating them by annealing (in FIG. 2 to FIG. 7, the source/drain
region 60 is not illustrated for the convenience of
illustration).
[0043] Then, as shown in FIG. 3, an oxide film 100 comprising USG
is formed by deposition over the entire surface. The oxide film 100
functions as a silicide protection film for protecting an MOSFET
which is not to be formed with the silicide layer 70 from
silicidation in the subsequent siliciding step, and it is removed
from the MOSFET which is to be formed with the silicide layer 70,
before the siliciding step.
[0044] Then, as shown in FIG. 4, the oxide film 100 is left only to
the outside of the side wall by applying wet etching.
[0045] Then, as shown in FIG. 5, the oxide film 100 left to the
outside of the side wall is further decreased by applying etching
(petit side wall).
[0046] Then, as shown in FIG. 6, the petit side wall is removed by
applying etching. Then, the nitride film 90 is removed by applying
etching. In this case, the polysilicon layer 30 and the substrate
10 can be protected against etching by previously forming an oxide
film to the Si surface of the polysilicon layer 30 and the
substrate 10 by O.sub.2 ashing or the like before the etching.
[0047] Then, as shown in FIG. 7, a silicide layer 70 comprising
NiSi is formed over the gate structure and the substrate 10.
Specifically, after depositing Ni over the entire surface, it is
silicided by annealing and unreacted Ni is removed. Then, a liner
nitride film 80 is deposited so as to cover the gate structure and
the side wall, whereby the semiconductor device 500 shown in FIG. 1
is manufactured.
[0048] As shown in FIG. 1, in the semiconductor device 500
according to the basic technique, the thickness of the first layer
along the lateral side of the gate structure is greater than the
thickness of the second layer along the upper surface of the
substrate 10 in the side wall oxide film comprising the oxide films
40, 50. Accordingly, this involves a problem that the stress by the
liner nitride film 80 cannot always be applied sufficiently to the
channel region.
First Embodiment
[0049] FIG. 8 is a cross sectional view showing the structure of a
semiconductor device 500a according to a first embodiment. In this
embodiment shown in FIG. 8, the thickness of the first layer along
the lateral side of the gate structure is decreased to less than
the thickness of the second layer along the upper surface of the
substrate 10 in the basic technique shown in FIG. 1. That is, in
the side wall shown in FIG. 8, the thickness of the first layer is
decreased upward and the minimum value thereof is smaller than the
thickness of the second layer. In such a structure, the distance
between the liner nitride film 80 and the channel region can be
decreased and the stress by the liner nitride film 80 can be
applied sufficiently to the channel region.
[0050] FIG. 9 is a cross sectional view showing a structure of a
semiconductor device 500b according to the first embodiment. In
FIG. 9, the nitride film 90 shown in FIG. 8 is not removed entirely
but left partially on the oxide film 50. As shown in FIG. 9, even
when a portion of the nitride film 90 is left, the stress by the
liner nitride film 80 can be applied sufficiently to the channel
region unless the region of the first layer that takes a minimum
value is covered with the nitride film 90. The nitride film 90 has
a rectangular parallelepiped shape in which each of the bottoms is
preferably smaller than the height and the height is preferably 10
nm or less.
[0051] FIG. 10 to FIG. 20 are cross sectional views showing a
method of manufacturing the semiconductor device 500a in FIG.
9.
[0052] At first, as shown in FIG. 10, an isolation film 20 is
formed in a substrate 10. Then, a gate structure is formed over the
substrate 10 according to a predetermined gate pattern (only the
polysilicon layer 30 is shown while saving the gate oxide film 31
for the convenience of illustration).
[0053] Then, as shown in FIG. 11, an oxide film 40 comprising TEOS
is formed over the entire surface by depositing to 6 nm at
620.degree. C. Then, bake-hardening is applied at 900.degree. C.
HTO may be deposited at 750.degree. C. instead of TEOS and
bake-hardening is not necessary in this case.
[0054] Then, as shown in FIG. 12, the oxide film 40 is left only on
the lateral side of the gate structure by applying anisotropic
etching.
[0055] Then, as shown in FIG. 13, an oxide film 50 comprising USG
is formed over the entire surface by deposition to 10 nm at
480.degree. C. Then, a nitride film 90 comprising ALD-SiN is formed
over the entire surface by deposition to 30 nm at 500.degree. C.
Instead of ALD-SiN, HCD-SiN may be deposited at 600.degree. C.
[0056] Then, as shown in FIG. 14, by applying etching back, the
oxide film 50 is fabricated into an L-cross sectional shape and the
nitride film 90 is left only over the second layer of the side wall
oxide film. Then, by implanting impurities from above and
activating by annealing, a source/drain region 60 is formed in the
substrate 10 (source/drain region 60 is not shown in FIG. 14 to
FIG. 20 for the sake of illustration).
[0057] Then, as shown in FIG. 15, an oxide film 100 comprising USG
is formed over the entire surface to 20 nm by deposition at
480.degree. C.
[0058] Then, as shown in FIG. 16, the oxide film 100 is left only
to the outside of the side wall by applying etching. In this case,
not only the oxide film 100 but also the substrate 10 are engraved
downward by etching at the outside of the side wall.
[0059] Generally, when the substrate 10 is engraved downward, while
the possibility of increasing the leak current is increased, this
is minimized in FIG. 16 since the second layer of the oxide film 50
protects the substrate 10 near the gate structure. That is, while
it is preferred that the first layer of the side wall is thin in
order to enhance the driving performance, it is preferred that the
second layer of the side wall is thick (to such an extent not
eliminated by etching) in order to prevent increase of the leak
current.
[0060] Then, as shown in FIG. 17, the oxide film 100 left to the
outside of the side wall is further decreased (petit side wall) by
applying wet etching. In this case, by applying wet etching using
hot phosphoric acid at 160.degree. C. for 5 min, the oxide film 50
comprising USG and the nitride film 90 comprising ALD-SiN can be
removed more compared with the oxide film 40 comprising TEOS. This
enables to decrease the minimum value of the thickness of the first
layer along the lateral side of the gate structure to less than the
thickness of the second layer along the upper surface of the
substrate 10, in the side wall oxide film comprising the oxide
films 40, 50.
[0061] That is, the first layer can be etched greatly without
etching the second layer not so much in the side wall oxide film by
using hot phosphoric acid having selectivity greatly different
between the oxide film 40 (TEOS) and the oxide film 50 (USG) as the
etching solution. The etching rate is defined as: oxide film 40
(TEOS)<oxide film 50 (USG)<< nitride film 90 (ALD-SiN) and
the rate for the nitride film is particularly higher relative to
that for the oxide film.
[0062] The oxide film 40 may be left thinly at the upper end
portion of the side wall oxide film as shown in FIG. 17, or it may
be removed entirely as shown in FIG. 8 to FIG. 9. In this case, the
polysilicon layer 30 and the substrate 10 can be protected against
etching by previous forming an oxide film to the Si surface of the
polysilicon layer 30 and the substrate 10 by O.sub.2 ashing or the
like before the etching.
[0063] Then, as shown in FIG. 18, the petit side wall is removed by
applying etching. In this case, the not bake-hardened petit side
wall can be removed at a high rate by applying wet etching using
APM (aqueous ammonia hydrogen peroxide).
[0064] Then, as shown in FIG. 19, a silicide layer 70 comprising
NiSi is formed over the gate structure and the substrate 10.
Specifically, after depositing Ni over the entire surface, it is
silicided by annealing and unreacted Ni is removed. Pt may also be
used in addition to Ni.
[0065] Then, as shown in FIG. 20, a liner nitride film 80
comprising p-SiN is formed by deposition to 50 nm over the entire
surface by UV curing at 425.degree. C. so as to cover the gate
structure and the side wall, whereby the stress by the liner
nitride film 80 can be increased.
[0066] As described above, according to the semiconductor devices
500a to 500b of this embodiment, the minimum value of the thickness
of the first layer along the lateral side of the gate structure is
less than the thickness of the second layer along the upper surface
of the substrate 10, in the side wall oxide film having an L-cross
sectional shape. Accordingly, the distance between the liner
nitride film 80 and the channel region can be decreased and the
stress by the liner nitride film 80 can be applied sufficiently to
the channel region. Accordingly, the driving performance can be
enhanced.
[0067] While description has been made to the case of removing the
petit side wall (oxide film 100), the petit side wall may be left
without removal as shown in FIG. 21 to FIG. 22 (FIG. 21 to FIG. 22
correspond respectively to the case of leaving the petit side wall
in FIG. 8 to FIG. 9).
[0068] Generally, for applying the stress by the liner nitride film
80 sufficiently to the channel region, it is preferred not to leave
but remove the petit side wall. However, in a case of not removing
but leaving the petit side wall, since the downward engraving of
the substrate 10 is decreased in the step of FIG. 16 as described
above, the leak current can be decreased. Further as shown in FIG.
23, the width of the silicide layer 70 can be adjusted by adjusting
the width of the remaining petit side wall (oxide film 100).
[0069] Further, while descriptions have been made to a case where
the structure has a symmetrical structure on both lateral sides
thereof, the structure may be asymmetrical as shown in FIG. 24. In
FIG. 24, the shape of the oxide film 50 is different between the
right and left of the gate structure, and the nitride film 90 is
left only on the right of the gate structure.
[0070] Further, as shown in FIG. 25, while a plurality of
functional areas such as a logic area (region for logic) or an SRAM
area (region for SRAM) are formed over one identical substrate 10,
the structure may be made different in accordance with the
functional areas. For example, as shown in FIG. 25A, when the
thickness of the oxide film 100 in the logic area is decreased to
less than that of the oxide film 100 in the SRAM area by adding a
step of selectively wet-etching the oxide film 100 only in the
logic area and applying dry etching as shown in FIG. 25B, the
nitride film 90 is left only in the SRAM area as shown in FIG. 25C.
This can make the characteristics for SC (Shared Contact) different
between the logic area and the SRAM area.
* * * * *