U.S. patent application number 12/289297 was filed with the patent office on 2009-05-14 for nonvolatile memory device and method of manufacturing the same.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Jeong-Uk Han, Yong-Tae Kim, Tea-Kwang Yu.
Application Number | 20090121277 12/289297 |
Document ID | / |
Family ID | 40622905 |
Filed Date | 2009-05-14 |
United States Patent
Application |
20090121277 |
Kind Code |
A1 |
Yu; Tea-Kwang ; et
al. |
May 14, 2009 |
Nonvolatile memory device and method of manufacturing the same
Abstract
The nonvolatile memory device includes a semiconductor
substrate, and a device isolation layer defining an active region
in the semiconductor substrate. The device isolation layer includes
a top surface lower than a top surface of the semiconductor
substrate, such that a side-upper surface of the active region is
exposed. A sense line crosses both the active region and the device
isolation layer, and a word line, spaced apart from the sense line,
crosses both the active region and the device isolation layer.
Inventors: |
Yu; Tea-Kwang; (Hwaseong-si,
KR) ; Han; Jeong-Uk; (Suwon-si, KR) ; Kim;
Yong-Tae; (Yongin-si, KR) |
Correspondence
Address: |
HARNESS, DICKEY & PIERCE, P.L.C.
P.O. BOX 8910
RESTON
VA
20195
US
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
|
Family ID: |
40622905 |
Appl. No.: |
12/289297 |
Filed: |
October 24, 2008 |
Current U.S.
Class: |
257/321 ;
257/E27.103 |
Current CPC
Class: |
H01L 27/11521 20130101;
H01L 27/11524 20130101; H01L 27/11519 20130101 |
Class at
Publication: |
257/321 ;
257/E27.103 |
International
Class: |
H01L 27/115 20060101
H01L027/115 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 8, 2007 |
KR |
10-2007-0113790 |
Claims
1. A nonvolatile memory device comprising: a semiconductor
substrate; at least one device isolation layer defining an active
region in the semiconductor substrate, the device isolation layer
including a top surface lower than a top surface of the
semiconductor substrate, such that a side-upper surface of the
active region is exposed; a sense line crossing both the active
region and the device isolation layer; and a word line spaced apart
from the sense line and crossing both the active region and the
device isolation layer.
2. The nonvolatile memory device of claim 1, wherein the word line
comprises: a gate insulation layer on the semiconductor substrate;
and a gate electrode on the gate insulation layer.
3. The nonvolatile memory device of claim 2, wherein the gate
electrode disposed in the active region comprises a bottom surface
higher than a bottom surface of the gate electrode disposed in the
device isolation layer.
4. The nonvolatile memory device of claim 2, wherein a bottom
surface of the gate electrode disposed in the device isolation
layer is lower than a top surface of the active region.
5. The nonvolatile memory device of claim 2, wherein a portion of
the gate electrode faces the exposed side-upper surface of the
active region.
6. The nonvolatile memory device of claim 1, wherein the sense line
comprises: a tunnel insulation layer on the semiconductor
substrate; a floating gate on the tunnel insulation layer; an
inter-gate dielectric on the floating gate; and a control gate on
the inter-gate dielectric.
7. The nonvolatile memory device of claim 6, wherein a bottom
surface of the floating gate disposed in the active region is
higher than a bottom surface of the floating gate disposed in the
device isolation layer.
8. The nonvolatile memory device of claim 6, wherein a portion of
the floating gate faces the exposed side-upper surface of the
active region.
9. The nonvolatile memory device of claim 6, wherein a portion of
the inter-gate dielectric and a portion of the control gate are
lower than a top surface of the active region.
10. The nonvolatile memory device of claim 1, wherein the active
region comprises a top surface, a side surface, and a rounded edge
where the top surface and the side surface cross each other.
11. The nonvolatile memory device of claim 10, wherein the sense
line and the word line cross the rounded edge.
12. The nonvolatile memory device of claim 1, further comprising a
pocket p-well on the semiconductor substrate, and an n-well
surrounding the pocket p-well on the semiconductor substrate.
13. A nonvolatile memory device comprising: an active region in a
semiconductor substrate, the active region having a top surface
higher than a top surface of at least one neighboring device
isolation layer; and first and second transistor structures formed
on the active region.
14. The nonvolatile memory device of claim 13, wherein the top
surface of the active region has a rounded edge.
15. The nonvolatile memory device of claim 14, wherein the first
transistor structure includes a portion of a word line and the
second transistor structure includes a portion of a sense line.
16. The nonvolatile memory device of claim 14, wherein a word line
connects to the first transistor structure and a sense line
connects to the second transistor structure.
17. The nonvolatile memory device of claim 13, wherein the first
transistor structure comprises: a gate insulation layer; a first
gate electrode; a first inter-gate dielectric; and a second gate
electrode.
18. The nonvolatile memory device of claim 13, wherein the second
transistor structure comprises: a tunnel insulation layer; a
floating gate; a second inter-gate dielectric; and a control
gate.
19. A card, comprising: a nonvolatile memory including a
semiconductor substrate, at least one device isolation layer
defining an active region in the semiconductor substrate, the
device isolation layer including a top surface lower than a top
surface of the semiconductor substrate, such that a side-upper
surface of the active region is exposed, a sense line crossing both
the active region and the device isolation layer, and a word line
spaced apart from the sense line and crossing both the active
region and the device isolation layer; and a control unit
configured to control the memory.
20. The card of claim 19, wherein the active region comprises a top
surface, a side surface, and a rounded edge where the top surface
and the side surface cross each other, and the sense line and the
word line cross the rounded edge.
Description
FOREIGN PRIORITY STATEMENT
[0001] This application claims priority under 35 U.S.C. .sctn.119
to Korean Patent Application No. 10-2007-0113790, filed on Nov. 8,
2007, the entire contents of which are incorporated herein by
reference.
BACKGROUND
[0002] 1. Field
[0003] An example embodiments provides a semiconductor memory
device and a method of manufacturing the same, and more
particularly, to a nonvolatile memory device and a method of
manufacturing the same.
[0004] 2. Description of the Related Art
[0005] Nonvolatile memory devices can maintain stored data while
external power is turned off. Such nonvolatile memory devices
include a mask read only memory (mask ROM) device, an erasable
programmable read-only memory (EPROM) device, an electrically
erasable programmable read-only memory (EEPROM) device, and a flash
memory device. The flash memory device is classified into a
NOR-type flash memory device and a NAND-type flash memory
device.
[0006] FIG. 1 is a plan view of a conventional EEPROM device. FIGS.
2 and 3 are cross-sectional views taken along lines II-II' and
III-III' of FIG. 1, respectively. Referring to FIGS. 1 through 3,
the EEPROM device includes an active region 12 defined by a device
isolation layer 13 of a semiconductor substrate 11. The active
region 12 includes a source region 12s, a drain region 12d, and a
floating diffusion region 12f. A sense line structure SL crosses
the active region 12. A word line structure WL spaced apart from
and parallel to the sense line structure SL crosses the active
region 12.
[0007] An interlayer dielectric 30, covering the word line
structure WL and the sense line structure SL, is disposed on the
semiconductor substrate 11. A bit line contact plug 31 connected to
the drain region 12d is disposed in the interlayer dielectric 30. A
bit line 35 connected to the bit line contact plug 31 is disposed
on the interlayer dielectric 30. The word line structure WL
includes a gate insulation layer 14, a first gate electrode 22, an
inter-gate dielectric 24, and a second gate electrode 26. The sense
line structure SL includes a tunnel insulation layer 15, a floating
gate electrode 21, an inter-gate dielectric 23, and a control gate
electrode 25. The sense line structure SL is disposed on the active
region 12 between the drain region 12d and the floating diffusion
region 12f. The word line structure WL is disposed on the active
region 12 between the source region 12s and the floating diffusion
region 12f.
[0008] Since semiconductor devices are highly integrated, the
channel width of a transistor including a word line structure WL
may be reduced. As a result, a cell current may also be reduced,
and a sense amplifier sensing an ON/OFF-state of a memory cell may
be overloaded. Additionally, a low power voltage caused by the
decreased cell current may reduce an operating speed of the
semiconductor device.
SUMMARY
[0009] An example embodiment provides a nonvolatile memory device
and a method of manufacturing the same that can increase a cell
current.
[0010] In an example embodiment, a nonvolatile memory device
includes a semiconductor substrate a device isolation layer
defining an active region in the semiconductor substrate, the
device isolation layer including a top surface lower than a top
surface of the semiconductor substrate, such that a side-upper
surface of the active region is exposed, a sense line crossing both
the active region and the device isolation layer, and a word line
spaced apart from the sense line and crossing both the active
region and the device isolation layer.
[0011] In an example embodiment, the word line includes a gate
insulation layer on the semiconductor substrate, and a gate
electrode on the gate insulation layer.
[0012] In an example embodiment, the gate electrode disposed in the
active region includes a bottom surface higher than a bottom
surface of the gate electrode disposed in the device isolation
layer.
[0013] In an example embodiment, a bottom surface of the gate
electrode disposed in the device isolation layer is lower than a
top surface of the active region.
[0014] In an example embodiment, a portion of the gate electrode
faces the exposed side-upper surface of the active region.
[0015] In an example embodiment, the sense line includes a tunnel
insulation layer on the semiconductor substrate, a floating gate on
the tunnel insulation layer, an inter-gate dielectric on the
floating gate, and a control gate on the inter-gate dielectric.
[0016] In an example embodiment, a bottom surface of the floating
gate disposed in the active region is higher than a bottom surface
of the floating gate disposed in the device isolation layer.
[0017] In an example embodiment, a portion of the floating gate
faces the exposed side-upper surface of the active region.
[0018] In an example embodiment, a portion of the inter-gate
dielectric and a portion of the control gate are lower than a top
surface of the active region.
[0019] In an example embodiment, the active region includes a top
surface, a side surface, and a rounded edge where the top surface
and the side surface cross each other.
[0020] In an example embodiment, the sense line and the word line
cross the rounded edge.
[0021] In an example embodiment, the nonvolatile memory device
includes a pocket p-well on the semiconductor substrate, and an
n-well surrounding the pocket p-well on the semiconductor
substrate.
[0022] In an example embodiment, a nonvolatile memory device
comprises an active region in a semiconductor substrate, the active
region having a top surface higher than a top surface of at least
one neighboring device isolation layer, and first and second
transistor structures formed on the active region.
[0023] In an example embodiment, the top surface of the active
region has a rounded edge.
[0024] In an example embodiment, the first transistor structure
includes a portion of a word line and the second transistor
structure includes a portion of a sense line.
[0025] In an example embodiment, a word line connects to the first
transistor structure and a sense line connects to the second
transistor structure.
[0026] In an example embodiment, the first transistor structure
comprises a gate insulation layer, a first gate electrode, a first
inter-gate dielectric, and a second gate electrode.
[0027] In an example embodiment, the second transistor structure
comprises a tunnel insulation layer, a floating gate, a second
inter-gate dielectric, and a control gate.
[0028] In an example embodiment, a card comprises a nonvolatile
memory including a semiconductor substrate, at least one device
isolation layer defining an active region in the semiconductor
substrate, the device isolation layer including a top surface lower
than a top surface of the semiconductor substrate, such that a
side-upper surface of the active region is exposed, a sense line
crossing both the active region and the device isolation layer, and
a word line spaced apart from the sense line and crossing both the
active region and the device isolation layer, and a control unit
configured to control the memory.
[0029] In an example embodiment, the active region comprises a top
surface, a side surface, and a rounded edge where the top surface
and the side surface cross each other, and the sense line and the
word line cross the rounded edge.
[0030] In an example embodiment, a method of manufacturing a
nonvolatile memory device includes forming a device isolation layer
defining an active region in a semiconductor substrate, the device
isolation layer including a top surface lower than that of the
semiconductor substrate, to expose a side-upper surface of the
active region, forming a sense line crossing both the active region
and the device isolation layer, and forming a word line spaced
apart from the sense line and crossing both the active region and
the device isolation layer.
[0031] In an example embodiment, forming the device isolation layer
includes forming a trench in the semiconductor substrate, forming a
preliminary device isolation layer filling the trench, and
recessing a portion of the preliminary device isolation layer to
expose the side-upper surface of the active region.
[0032] In an example embodiment, the portion of the preliminary
device isolation layer is recessed using a wet etching process.
[0033] In an example embodiment, the preliminary device isolation
layer includes a silicon oxide layer, and the wet etching process
is performed with a solution including hydrofluoric acid.
[0034] In an example embodiment, a method of manufacturing a
nonvolatile semiconductor device includes rounding an edge of the
semiconductor substrate in the active region.
[0035] In an example embodiment, rounding the edge of the
semiconductor substrate includes etching the edge with a mixture
solution of NH.sub.4OH, H.sub.2O.sub.2 and H.sub.2O.
[0036] In an example embodiment, rounding the edge of the
semiconductor substrate includes oxidizing the edge of the
semiconductor substrate, and etching the oxidized edge.
[0037] In an example embodiment, forming the word line includes
forming a gate insulation layer on the semiconductor substrate, and
forming a gate electrode on the gate insulation layer, wherein a
bottom surface of the gate electrode disposed in the active region
is higher than a bottom surface of the gate electrode disposed in
the device isolation layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The above and other features and advantages of example
embodiments will become more apparent by describing them in detail
with reference to the attached drawings. The accompanying drawings
are intended to depict example embodiments and should not be
interpreted to limit the intended scope of the claims. The
accompanying drawings are not to be considered as drawn to scale
unless explicitly noted.
[0039] FIGS. 1 through 3 are views of a typical conventional memory
device.
[0040] FIGS. 4 through 8 are views illustrating a method of forming
a nonvolatile memory device according to an example embodiment.
[0041] FIGS. 9 through 13 are views illustrating the implementation
of a nonvolatile memory device according to an example embodiment
in various applications of semiconductor devices.
DESCRIPTION OF EXAMPLE EMBODIMENTS
[0042] Detailed example embodiments are disclosed herein. However,
specific structural and functional details disclosed herein are
merely representative for purposes of describing example
embodiments. Example embodiments may, however, be embodied in many
alternate forms and should not be construed as limited to only the
embodiments set forth herein.
[0043] Accordingly, while example embodiments are capable of
various modifications and alternative forms, embodiments thereof
are shown by way of example in the drawings and will herein be
described in detail. It should be understood, however, that there
is no intent to limit example embodiments to the particular forms
disclosed, but to the contrary, example embodiments are to cover
all modifications, equivalents, and alternatives falling within the
scope of example embodiments. Like numbers refer to like elements
throughout the description of the figures.
[0044] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements, these
elements should not be limited by these terms. These terms are only
used to distinguish one element from another. For example, a first
element could be termed a second element, and, similarly, a second
element could be termed a first element, without departing from the
scope of example embodiments. As used herein, the term "and/or"
includes any and all combinations of one or more of the associated
listed items.
[0045] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it may be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. Other words
used to describe the relationship between elements should be
interpreted in a like fashion (e.g., "between" versus "directly
between", "adjacent" versus "directly adjacent", etc.).
[0046] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
example embodiments. As used herein, the singular forms "a", "an"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises", "comprising,", "includes"
and/or "including", when used herein, specify the presence of
stated features, integers, steps, operations, elements, and/or
components, but do not preclude the presence or addition of one or
more other features, integers, steps, operations, elements,
components, and/or groups thereof.
[0047] It should also be noted that in some alternative
implementations, the functions/acts noted may occur out of the
order noted in the figures. For example, two figures shown in
succession may in fact be executed substantially concurrently or
may sometimes be executed in the reverse order, depending upon the
functionality/acts involved.
[0048] FIG. 4 is a plan view illustrating a method of forming a
nonvolatile memory device according to an example embodiment. FIGS.
5A, 6A and 7A are cross-sectional views taken along a line VA-VA'
of FIG. 4. FIGS. 5B, 6B and 7B are cross-sectional views taken
along a line VB-VB' of FIG. 4. FIG. 8 is a cross-sectional views
taken along a line VIII-VIII' of FIG. 4.
[0049] Referring to FIGS. 5A and 5B, a semiconductor substrate 110
is prepared. A preliminary device isolation layer 113a defining an
active region 112 is formed in the semiconductor substrate 110. The
forming of the preliminary device isolation layer 113a may include
forming a trench in the semiconductor substrate 110 and forming a
dielectric filling the trench. For example, the preliminary device
isolation layer 113a may be formed through a shallow trench
isolation (STI) method, and the preliminary device isolation layer
113a may be formed of a silicon oxide.
[0050] Referring to FIGS. 6A and 6B, a portion of the preliminary
device isolation layer 113a is recessed to form a device isolation
layer 113. The device isolation layer 113 is formed to expose
side-upper surfaces of the active region 112. Accordingly, the
active region 112 in the semiconductor substrate 110 protrudes
above the device isolation layer 113. The recessed portion of the
preliminary device isolation layer 113a may be removed through a
wet etching process. The wet etching process may be performed with
a solution including hydrofluoric acid. The protruding
semiconductor substrate 110 may have a rounded edge E. Since the
semiconductor substrate 110 has a rounded edge E, an electric field
that may concentrate on an angled edge can be reduced or prevented,
thereby decreasing deterioration of a gate insulation layer and a
tunnel insulation layer.
[0051] The rounding of the edge of the semiconductor substrate 110
may include etching an angled edge with a mixture solution of
NH.sub.4OH, H.sub.2O.sub.2 and H.sub.2O. Since the angled edge is
etched more intensively than a flat portion of the semiconductor
substrate 110, the rounded edge E can be formed. The rounding of
the edge E may include oxidizing the angled edge of the
semiconductor substrate 110, and etching the oxidized edge. A
pocket p-well 118 and an n-well 117 surrounding the pocket p-well
118 may be formed on the semiconductor substrate 110.
[0052] Referring to FIG. 7A and 7B, a sense line structure SL and a
word line structure WL are formed, crossing the active region 112
and the device isolation layer 113. The sense line structure SL and
the word line structure WL may be simultaneously patterned. As
shown in FIG. 7B, the sense line structure SL includes a tunnel
insulation layer 115, a floating gate 121, a first inter-gate
dielectric 123, and a control gate 125 that are sequentially
stacked. As shown in FIG. 7A, the word line structure WL includes a
gate insulation layer 114, a first gate electrode 122, a second
inter-gate dielectric 124, and a second gate electrode 126 that are
sequentially stacked. The first and the second gate electrode 122
and 126 may be connected through a butting contact. Alternatively,
the first gate electrode 122 may be connected to a metal contact
(not shown) for applying voltage.
[0053] A bottom surface of the first gate electrode 122 disposed in
the active region 112 is higher than a bottom surface of the first
gate electrode 122 in the device isolation layer 113. A portion of
the first gate electrode 122 may face the exposed side-upper
surfaces of the active region 112. That is, the active region 112
that the first gate electrode 122 crosses has a three-dimensional
structure with a substantially improved effective channel width, to
increase a cell current.
[0054] Referring to FIGS. 4 and 8, an ion-implantation process is
performed to form a source region 112s, a drain region 112d, and a
floating diffusion region 112f after the word line structure WL and
the sense line structure SL are formed. An interlayer dielectric
130 is formed to cover the word line structure WL and the sense
line structure SL. Then, a bit line contact plug 131 is formed to
penetrate through the interlayer dielectric 130 and contact the
drain region 112d. A bit line 135 contacting the bit line contact
plug 131 is disposed on the interlayer dielectric 130.
[0055] Referring to FIGS. 7A and 7B, aspects of the nonvolatile
memory device according to an example embodiment will be
described.
[0056] The device isolation layer 113 is provided to define the
active region 112 in the semiconductor substrate 110 and have a top
surface lower than a top surface of the semiconductor substrate
110. The device isolation layer 113 exposes the side-upper surfaces
of the active region 112. The device isolation layer 113 may
include a silicon oxide layer. The sense line structure SL and the
word line structure WL are provided, and cross the active region
112 and the device isolation layer 113.
[0057] The word line structure WL may include the gate insulation
layer 114, the first gate electrode 122, the first inter-gate
dielectric 124, and the second gate electrode 126 on the
semiconductor substrate 110. A bottom surface of the first gate
electrode 122 in the active region 112 is higher than a bottom
surface of the first gate electrode 122 in the device isolation
layer 113. A portion of the first gate electrode 122 may face the
exposed side-upper surfaces of the active region 112. That is, the
active region 112 that the word line structure WL crosses has a
three-dimensional structure, and a substantially effective channel
width is extended without increasing the size of a cell.
[0058] The sense line structure SL may include the tunnel
insulation layer 115, the floating gate 121, the second inter-gate
dielectric 123, and the control gate 125 on the semiconductor
substrate 110. The gate insulation layer 114 and the tunnel
insulation layer 115 may be formed of a silicon oxide. The first
and the second gate electrodes 122 and 126, the floating gate 121,
and the control gate 125 may include a poly-silicon. The first and
the second inter-gate dielectrics 124 and 123 may be formed of an
oxide-nitride-oxide (ONO).
[0059] The sense line structure SL and the word line structure WL
may cross the rounded edge of the semiconductor substrate 110 in
the active region 112. The rounded edge may reduce or prevent the
concentration of the electric field and accordingly may reduce or
prevent the deterioration of the gate insulation layer 114 and the
tunnel insulation layer 115.
[0060] According to an example embodiment, a top surface of the
device isolation layer is lower than a top surface of the
semiconductor substrate. Therefore, a channel region of the word
line has a three-dimensional structure, and the width of the
channel increases to cause the increase of the cell current.
[0061] FIG. 9 illustrates an example embodiment of an application
of the semiconductor device. As shown, this embodiment includes a
memory 2210 connected to a memory controller 2220. The memory 2210
may be any of the semiconductor device embodiments described above.
The memory controller 2220 supplies the input signals for
controlling operation of the memory 2210. For example, the memory
controller 2220 supplies a command CMD and address signals.
[0062] FIG. 10 illustrates yet another example embodiment. This
embodiment is the same as the embodiment of FIG. 9, except that the
memory 2210 and memory controller 2220 have been embodied as a card
2330. For example, the card 2330 may be a memory card such as a
flash memory card. Namely, the card 2330 may be a card meeting any
industry standard for use with a consumer electronics device such
as a digital camera, personal computer, etc. It will be appreciated
that the memory controller 2220 may control the memory 2210 based
on controls signals received by the card 2330 from another (e.g.,
external) device.
[0063] FIG. 11 illustrates a still further example embodiment. As
shown, the memory 2210 may be connected with a host system 2410.
The host system 2410 may be a processing system such as a personal
computer, digital camera, etc. The host system 2410 may use the
memory 2210 as a removable storage medium. As will be appreciated,
the host system 2410 supplies the input signals for controlling
operation of the memory 2210. For example, the host system 2410
supplies the command CMD and address signals.
[0064] FIG. 12 illustrates an example embodiment in which the host
system 2410 is connected to the card 2330 of FIG. 10. In this
embodiment, the host system 2410 applies control signals to the
card 2330 such that the memory controller 2220 controls operation
of the memory 2210.
[0065] FIG. 13 illustrates a further example embodiment. As shown,
the memory 2210 may be connected to a central processing unit (CPU)
2620 within a computer system 2610. For example, the computer
system 2610 may be a personal computer, personal data assistant,
etc. The memory 2210 may be directly connected with the CPU 2620,
connected via bus, etc. It will be appreciated, that FIG. 13 does
not illustrate the full complement of components that may be
included within a computer system 2610 for the sake of clarity.
[0066] Example embodiments having thus been described, it will be
obvious that the same may be varied in many ways. Such variations
are not to be regarded as a departure from the intended spirit and
scope of example embodiments, and all such modifications as would
be obvious to one skilled in the art are intended to be included
within the scope of the following claims.
* * * * *