U.S. patent application number 11/968869 was filed with the patent office on 2009-05-14 for semiconductor device with improved short channel effect of a pmos and stabilized current of an nmos and method for manufacturing the same.
Invention is credited to Min Jung SHIN.
Application Number | 20090121256 11/968869 |
Document ID | / |
Family ID | 40622891 |
Filed Date | 2009-05-14 |
United States Patent
Application |
20090121256 |
Kind Code |
A1 |
SHIN; Min Jung |
May 14, 2009 |
SEMICONDUCTOR DEVICE WITH IMPROVED SHORT CHANNEL EFFECT OF A PMOS
AND STABILIZED CURRENT OF AN NMOS AND METHOD FOR MANUFACTURING THE
SAME
Abstract
The present invention relates to a semiconductor device which is
capable of simultaneously improving a short channel effect of a
PMOS and the current of an NMOS and a method for manufacturing the
same. The semiconductor device includes first and second gates
formed over first and second areas of a semiconductor substrate,
respectively; and first and second junction areas formed in a
portion of the semiconductor substrate corresponding to both sides
of the first gate and a portion of the semiconductor substrate
corresponding to both sides of the second gate, and including a
projection, respectively, wherein the projection of the first
junction area has a height higher than the height of the projection
of the second junction area, and the second junction area is formed
such that it has a depth from the surface of the semiconductor
substrate deeper than the depth of the first junction area.
Inventors: |
SHIN; Min Jung;
(Gyeonggi-do, KR) |
Correspondence
Address: |
LADAS & PARRY LLP
224 SOUTH MICHIGAN AVENUE, SUITE 1600
CHICAGO
IL
60604
US
|
Family ID: |
40622891 |
Appl. No.: |
11/968869 |
Filed: |
January 3, 2008 |
Current U.S.
Class: |
257/190 ;
257/E21.632; 257/E27.062; 438/229 |
Current CPC
Class: |
H01L 29/41783 20130101;
H01L 21/823814 20130101 |
Class at
Publication: |
257/190 ;
438/229; 257/E27.062; 257/E21.632 |
International
Class: |
H01L 27/092 20060101
H01L027/092; H01L 21/8238 20060101 H01L021/8238 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 14, 2007 |
KR |
10-2007-0116055 |
Claims
1. A semiconductor device, comprising: first and second gates
formed over first and second areas of a semiconductor substrate,
respectively; and first and second junction areas formed in a
portion of the semiconductor substrate corresponding to both sides
of the first gate and a portion of the semiconductor substrate
corresponding to both sides of the second gate, and including a
projection, respectively, wherein the projection of the first
junction area has a height higher than the height of the projection
of the second junction area, and the second junction area is formed
to a depth from the surface of the semiconductor substrate deeper
than the depth of the first junction area.
2. The semiconductor device according to claim 1, wherein the first
area is a PMOS area and the second area is an NMOS area.
3. The semiconductor device according to claim 1, wherein the first
and second gates are made in a structure including an N.sup.+
polysilicon layer.
4. The semiconductor device according to claim 1, wherein the
projections of the first and second junction areas are made of an
epitaxial layer.
5. The semiconductor device according to claim 1, wherein the
epitaxial layer includes a SiGe layer.
6. A method for manufacturing a semiconductor device, comprising
the steps of: forming first and second gates over first and second
areas of a semiconductor substrate, respectively; selectively ion
implanting impurities into the surface of the semiconductor
substrate corresponding to both sides of the first gate; growing
first and second epitaxial layers over the portion of the
semiconductor substrate corresponding to both sides of the first
gate into which the impurities are ion implanted and a portion of
the semiconductor substrate corresponding to both sides of the
second gate, respectively, so as to have a higher height over the
portion of the semiconductor substrate corresponding to both sides
of the first gate into which the impurities are ion implanted; and
forming a first junction area in a portion of semiconductor
substrate corresponding to both sides of the first gate including
the first epitaxial layer and forming a second junction area,
having a depth from a surface of the semiconductor substrate deeper
than a depth of the first junction area, in a portion of
semiconductor substrate corresponding to both sides of the second
gate including the second epitaxial layer.
7. The method according to claim 6, wherein the first area is a
PMOS area and the second area is an NMOS area.
8. The method according to claim 6, wherein the first and second
gates are formed in a structure including an N.sup.+ polysilicon
layer.
9. The method according to claim 6, wherein the step of ion
implanting selectively the impurities into the surface of the
semiconductor substrate corresponding to both sides of the first
gate is performed using P-type impurities.
10. The method according to claim 9, wherein the P-type impurities
include boron (B).
11. The method according to claim 6, wherein the step of growing
the epitaxial layer is performed through a selective epitaxial
growth (SEG) process.
12. The method according to claim 6, wherein the epitaxial layer is
grown to a SiGe layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to Korean patent
application number 10-2007-0116055 filed on Nov. 14, 2007, which is
incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor device and
a method for manufacturing the same, and more particularly to a
semiconductor device which is capable of simultaneously improving
the short channel effect of a PMOS and stabilizing the current of
an NMOS and a method for manufacturing the same.
[0003] The gate material of a MOSFET device is mainly made of a
polysilicon layer, because the polysilicon layer displays the
physical properties required in a manufacturing process for a
semiconductor device, such as a high melting point, ease of forming
a thin film, ease of patterning a line, stability in an oxidation
atmosphere and formation of a planarized surface. In an actual
MOSFET device, a polysilicon gate contains a dopant such as
phosphorous (P), arsenic (As) or boron (B), thereby ensuring low
resistance.
[0004] Also, in a CMOS device, an NMOS and PMOS are all formed with
an N.sup.+ polysilicon gate. In this case, the NMOS has a surface
channel and the PMOS has a buried channel by a count doping.
[0005] Meanwhile, as the level of integration of semiconductor
devices increases the width of the gate electrode has decreased.
Unlike the NMOS having a surface channel, the PMOS is disadvantaged
by an increase in short channel effect, such as the punch-through
phenomenon, due to the buried channel.
[0006] Accordingly, there has been suggested a method in which an
elevated source/drain area is formed on both sides of the
polysilicon gate. The elevated source/drain area increases the
effective channel length thereby improving the short channel effect
of the PMOS.
[0007] However, in the prior art described above, it is difficult
to increase the current since the elevated source/drain area is
formed with a shallow depth within the semiconductor substrate.
Therefore, the prior art is limited in its ability to ensure the
stability of the current of the NMOS.
[0008] Also, because the NMOS has a larger variation in current as
compared to the PMOS, it is important to ensure the stability of
the current of the NMOS device in order to enhance the operational
characteristics of the semiconductor device. No method, however,
has been developed which is capable of simultaneously improving the
short channel effect of the PMOS and ensuring the stability of the
current of the NMOS. Therefore, it is necessary to find the
solution.
SUMMARY OF THE INVENTION
[0009] Embodiments of the present invention are directed to a
semiconductor device which is capable of simultaneously improving
the short channel effect of a PMOS and the current of an NMOS and a
method for manufacturing the same.
[0010] In one embodiment, a semiconductor device comprises first
and second gates formed over first and second areas of a
semiconductor substrate, respectively; and first and second
junction areas formed in a portion of the semiconductor substrate
corresponding to both sides of the first gate and a portion of the
semiconductor substrate corresponding to both sides of the second
gate, and including a projection, respectively, wherein the
projection of the first junction area has a height higher than the
height of the projection of the second junction area, and the depth
of the second junction area is deeper than the depth of the first
junction area.
[0011] The first area is a PMOS area and the second area is an NMOS
area.
[0012] The first and second gates are made of a structure which
includes an N.sup.+ polysilicon layer.
[0013] The projections of the first and second junction areas are
made of an epitaxial layer.
[0014] The epitaxial layer includes a SiGe layer.
[0015] In another embodiment, a method for manufacturing a
semiconductor device comprises the steps of forming first and
second gates over the first and second areas of a semiconductor
substrate, respectively; selectively ion implanting impurities into
a surface of the semiconductor substrate corresponding to both
sides of the first gate; growing first and second epitaxial layers
over the portion of the semiconductor substrate corresponding to
both sides of the first gate into which the impurities are ion
implanted and a portion of the semiconductor substrate
corresponding to both sides of the second gate, respectively, such
that the epitaxial layer has a higher height over the portion of
the semiconductor substrate corresponding to both sides of the
first gate into which the impurities are ion implanted; and forming
a first junction area in a portion of the semiconductor substrate
corresponding to both sides of the first gate including the first
epitaxial layer and forming a second junction area having a depth
from the surface of the semiconductor substrate deeper than that of
the first junction area in a portion of the semiconductor substrate
corresponding to both sides of the second gate including the second
epitaxial layer.
[0016] The first area is a PMOS area and the second area is an NMOS
area.
[0017] The first and second gates are formed in a structure which
includes an N.sup.+ polysilicon layer.
[0018] The step of selectively ion implanting the impurities into
the surface of the semiconductor substrate corresponding to both
sides of the first gate is performed using P-type impurities.
[0019] The P-type impurities include boron (B).
[0020] The step of growing the epitaxial layer is performed through
a selective epitaxial growth (SEG) process.
[0021] The epitaxial layer is grown to a SiGe layer.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] FIG. 1 is a cross-sectional view showing a semiconductor
device in accordance with an embodiment of the present
invention.
[0023] FIGS. 2A through 2D are cross-sectional views for
illustrating the process steps of a method for manufacturing a
semiconductor device in accordance with an embodiment of the
present invention.
[0024] FIG. 3 is a graph showing the relationship between the
concentration of boron and the growth rate of an epitaxial
layer.
DESCRIPTION OF SPECIFIC EMBODIMENTS
[0025] In the present invention, P-type impurities are selectively
ion implanted into an area of the surface of a semiconductor
substrate corresponding to both sides of a first gate of the
semiconductor substrate having a PMOS area formed with the first
gate and an NMOS area formed with a second gate. After that, an
epitaxial layer is grown over the semiconductor substrate
corresponding to both sides of the first and second gates such that
it has a higher height over the semiconductor substrate
corresponding to both sides of the first gate into which the P-type
impurities are ion implanted. Impurities are then ion implanted
into the epitaxial layer and the surface of the semiconductor
substrate below the epitaxial layer to form an elevated
source/drain area.
[0026] By doing this, it is possible to form a source/drain area
with a shallow depth within the surface of the semiconductor
substrate at both sides of the first gate of the PMOS area into
which the P-type impurities are ion implanted, and a source/drain
area having a relatively deeper depth within the surface of the
semiconductor substrate at both sides of the second gate of the
NMOS area into which the P-type impurities are not ion
implanted.
[0027] Therefore, in the present invention, it is possible to
enhance the operational characteristics of the device by both
improving the short channel effect and increasing the current of
the PMOS through an increase in the effective channel length.
[0028] Hereafter, a preferred embodiment of the present invention
will be described in detail with reference to the accompanying
drawings.
[0029] FIG. 1 is a cross-sectional view illustrating a
semiconductor device in accordance with an embodiment of the
present invention.
[0030] As shown, in a semiconductor substrate 100 having a PMOS
area and an NMOS area, an isolation layer 102 isolates the PMOS
area from the NMOS area. The PMOS area of the semiconductor
substrate 100 is formed with a first gate 110a and the NMOS area is
formed with a second gate 110b. The first and second gates 110a and
110b include a stacked structure of a gate insulation layer 104, a
gate conductive layer 106 and a gate hard mask layer 108. The gate
conductive layer 106 includes an N.sup.+ polysilicon layer.
[0031] A portion of the semiconductor substrate 100 corresponding
to both sides of the first gate 110a is formed with a first
junction area 122a made of a P-type ion implantation layer and a
portion of the semiconductor substrate 100 corresponding to both
sides of the second gate 110b is formed with a second junction area
122b. The first and second junction areas 122a and 122b have an
elevated structure including, respectively, first and second
projections 120a and 120b formed over the semiconductor substrate
100. The first and second projections 120a and 120b are made of an
epitaxial layer, e.g. an ion implanted epitaxial SiGe layer.
[0032] Herein, the first junction area 122a formed in the PMOS area
includes the first projection 120a having, on the semiconductor
substrate 100, a height a higher than the height b of the second
projection 120b in the second junction area 122b (a>b), and
formed so as to have, within the surface of the semiconductor
substrate 100, a depth c shallower than the depth d of the second
junction area 122b (c<d).
[0033] Also, the second junction area 122b formed in the NMOS area
includes the second projection 120b having, on the semiconductor
substrate 100, a height b lower than the height a of the first
projection 120a in the first junction area 122a (b<a), and
formed so as to have, within the surface of the semiconductor
substrate 100, a depth d deeper than the depth c of the first
junction area 122a (d>c).
[0034] Therefore, in the semiconductor device of the present
invention described above, since the first junction area 122a
formed in the PMOS area is formed so as to have the shallow depth c
within the surface of the semiconductor substrate 100, the effect
channel length is increased thereby improving the short channel
effect. Also, in the semiconductor device of the present invention
described above, since the second junction area 122b formed in the
NMOS area is formed so as to have the deep depth d within the
surface of the semiconductor substrate 100, the current of the NMOS
area is increased to improve operational characteristics of the
device. Therefore, in the present invention, the short channel
effect of the PMOS and the current of the NMOS are simultaneously
improved.
[0035] FIGS. 2A through 2D are cross-sectional views illustrating
the process steps of a method for manufacturing a semiconductor
device in accordance with an embodiment of the present
invention.
[0036] Referring to FIG. 2A, in a semiconductor substrate 100
having a PMOS area and an NMOS area, an isolation layer 102
isolates the PMOS area from the NMOS area. Impurities different
from each other are ion implanted into each area of the
semiconductor substrate 100 formed with the isolation layer 102
respectively to form wells (not shown)
[0037] A gate insulation layer 104, a gate conductive layer 106 and
a gate hard mask layer 108 are sequentially formed over the PMOS
area and the NMOS area of the semiconductor substrate 100. The gate
conductive layer 106 formed in each area is formed so as to include
an N.sup.+ polysilicon layer. The gate hard mask layer 108, the
gate conductive layer 106 and the gate insulation layer 104 are
etched to form a first gate 110a in the PMOS area and a second gate
110b in the NMOS area. Spacers 112 are formed at both walls of the
first and second gates 110a and 110b.
[0038] Referring to FIG. 2B, a mask pattern 114 which covers the
NMOS area of the semiconductor substrate 100 but exposes the PMOS
area is formed over the semiconductor substrate 100 formed with the
first and second gates 110a and 110b and the spacer 112. P-type
impurities, e.g. boron (B), are ion implanted into the exposed PMOS
area to form a boron ion implantation layer 116 within a surface of
the semiconductor substrate 100 corresponding to both sides of the
first gate 110a formed in the PMOS area.
[0039] Referring to FIG. 2C, after removal of the mask pattern 114,
a first epitaxial layer 118a is grown over the semiconductor
substrate 100 corresponding to both sides of the first gate 110a in
the PMOS area and a second epitaxial layer 118b is grown over the
semiconductor substrate 100 corresponding to both sides of the
second gate 110b in the NMOS area. The first and second epitaxial
layers 118a and 118b are grown to a SiGe layer through a selective
epitaxial growth (SEG) process.
[0040] Herein, since the first and second epitaxial layers 118a and
118b will grow at a faster speed over the portion of the
semiconductor substrate 100 having a high doping concentration of
boron, it is possible to form the first epitaxial layer 118a with a
height a higher than that of the second epitaxial layer 118b,
height b, over the semiconductor substrate 100 corresponding to
both sides of the first gate 110a in the PMOS area (a>b).
[0041] Referring to FIG. 2D, impurities are ion implanted into the
first and second epitaxial layers 118a and 118b and the surface of
the semiconductor substrate 100 below the epitaxial layers to form
a first junction area 122a in a portion of the semiconductor
substrate 100 corresponding to both sides of the first gate 110a in
the PMOS area and a second junction area 122b in a portion of the
semiconductor substrate 100 corresponding to both sides of the
second gate 110b in the NMOS area. The first junction area 122a is
formed by the ion implantation of P-type impurities and the second
junction area 122b is formed by the ion implantation of N-type
impurities.
[0042] Herein, the height a of the first epitaxial layer 118a
formed at both sides of the first gate 110a in the PMOS area
prevents the P-type impurities from implanting deeply into the
surface of the semiconductor substrate 100 below the first
epitaxial layer 118a. As the result, the first junction area 122a
in the PMOS area includes the first projection 120a having, on the
semiconductor substrate 100, the height a which is higher than the
height b of the second projection 120b in the second junction area
122b (a>b), and formed so as to have, within the surface of the
semiconductor substrate 100, a depth c shallower than the depth d
of the second junction area 122b (c<d).
[0043] Also, since the second epitaxial layer 118b having a
relatively low height b is formed at both sides of the second gate
110b in the NMOS area, the N-type impurities are ion implanted
deeper into the surface of the semiconductor substrate 100 below
the second epitaxial layer 118b. As a result, the second junction
area 122b formed in the NMOS area includes the second projection
120b having, on the semiconductor substrate 100, the height b lower
than the height a of the first projection 120a in the first
junction area 122a (b<a), and formed so as to have, within the
surface of the semiconductor substrate 100, the depth d deeper than
the depth c of the first junction area 122a (d>c).
[0044] After that, though not shown, a series of known follow-up
processes is sequentially performed, thereby completing the
semiconductor device in accordance with an embodiment of the
present invention.
[0045] FIG. 3 is a graph showing the relationship between the
concentration of boron and the growth rate of an epitaxial
layer.
[0046] As shown, as the pressure increases, the concentration of
boron and the growth rate of an epitaxial layer both increase. In
other words, since the pressure and the concentration of boron are
proportional to each other and the pressure and the growth rate of
an epitaxial layer are proportional to each other, the
concentration of boron and the growth rate of an epitaxial layer
are also proportional to each other. Therefore, the higher the
concentration of boron within the semiconductor substrate is, the
faster an epitaxial layer will grow.
[0047] As is apparent from the above description, in the present
invention, the boron is selectively ion implanted only into the
PMOS area of the semiconductor substrate, and the epitaxial layer
over the ion implanted portion of the semiconductor substrate
therefore has a height higher than that of the epitaxial layer in
the NMOS area. Therefore, it is possible to form a junction area in
the surface of the semiconductor substrate below the epitaxial
layer in the PMOS area with a depth shallower than that of the
junction area in the NMOS area. Accordingly, in the present
invention, the effect channel length is increased and the short
channel effect is therefore improved.
[0048] Also, in the present invention, the NMOS area, which has not
been ion implanted with boron, is formed with an epitaxial layer
having a height lower than that of the epitaxial layer of the PMOS
area. Therefore, it is possible to form a junction area having a
depth deeper than that of the junction area in the PMOS area in the
surface of the semiconductor substrate below the epitaxial
layer.
[0049] Further, in the present invention, since it is possible to
perform the ion implantation using less energy than the prior art,
it is possible to reduce current leakage caused by the surface
damage created during the ion implantation. Accordingly, in the
present invention, the current of the NMOS device is increased and
thus the operational characteristics of the device are
improved.
[0050] Therefore, in the present invention, it is possible to
simultaneously improve the short channel effect of the PMOS and the
current and operational characteristics of the NMOS, thereby
efficiently enhancing the characteristics and reliability of the
device.
[0051] Although specific embodiments of the present invention have
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
the spirit of the invention as disclosed in the accompanying
claims.
* * * * *