U.S. patent application number 12/261167 was filed with the patent office on 2009-04-30 for analog switch.
This patent application is currently assigned to ROHM CO., LTD.. Invention is credited to Sachito Horiuchi, Hironori Nakahara.
Application Number | 20090108911 12/261167 |
Document ID | / |
Family ID | 40582058 |
Filed Date | 2009-04-30 |
United States Patent
Application |
20090108911 |
Kind Code |
A1 |
Nakahara; Hironori ; et
al. |
April 30, 2009 |
ANALOG SWITCH
Abstract
An analog signal is input to an input terminal. An analog signal
is output via an output terminal. A first transistor is an
N-channel MOSFET, and is provided between the input terminal and
the output terminal. A first resistor is provided between the gate
of the first transistor and a first fixed voltage terminal (power
supply terminal), which sets the gate of the first transistor to a
high-impedance state.
Inventors: |
Nakahara; Hironori; (Kyoto,
JP) ; Horiuchi; Sachito; (Kyoto, JP) |
Correspondence
Address: |
CANTOR COLBURN, LLP
20 Church Street, 22nd Floor
Hartford
CT
06103
US
|
Assignee: |
ROHM CO., LTD.
Kyoto
JP
|
Family ID: |
40582058 |
Appl. No.: |
12/261167 |
Filed: |
October 30, 2008 |
Current U.S.
Class: |
327/434 |
Current CPC
Class: |
H03K 17/063
20130101 |
Class at
Publication: |
327/434 |
International
Class: |
H03K 17/687 20060101
H03K017/687 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 30, 2007 |
JP |
2007-282218 |
Oct 30, 2007 |
JP |
2007-282223 |
Claims
1. An analog switch comprising: an input terminal via which an
analog signal is input; an output terminal via which the analog
signal is output; a first N-channel MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) provided between the input
terminal and the output terminal; and a first resistor provided
between the gate of the first MOSFET and a first fixed voltage
terminal.
2. An analog switch according to claim 1, wherein the analog signal
is a signal that swings between a negative voltage and a positive
voltage with the ground voltage as the midpoint, and wherein, in
the ON state of the analog switch, the power supply voltage is
applied to the first fixed voltage terminal.
3. An analog switch according to claim 1, further including a
second N-channel MOSFET which is connected in series with the first
MOSFET between the input terminal and the output terminal, such
that the gate thereof is connected to the gate of the first MOSFET
so as to form a common gate.
4. An analog switch according to claim 1, wherein the analog signal
is an audio signal, and wherein a bypass filter configured of the
first resistor and the gate-source capacitance of the first MOSFET
allows a signal in the audio frequency band to pass through.
5. An analog switch according to claim 1, further including a first
capacitor in the form of a MIM (Metal Insulator Metal) capacitance
between the input terminal and the gate of the first MOSFET.
6. An analog switch according to claim 1, further including a
second capacitor in the form of a MIM capacitance between the
output terminal and the gate of the first MOSFET.
7. An analog switch according to claim 3, further including a third
MOSFET provided between the first fixed voltage terminal and the
first resistor, such that the gate voltage is controlled according
to the ON/OFF operation of the analog switch.
8. An analog switch according to claim 3, further including a
fourth MOSFET provided between the node that connects the first
MOSFET and the second MOSFET and the first resistor, such that the
gate voltage thereof is controlled according to the ON/OFF
operation of the analog switch.
9. An analog switch according to claim 3, further including a fifth
MOSFET provided between the node that connects the first MOSFET and
the second MOSFET and the ground terminal, such that the gate
voltage thereof is controlled according to the ON/OFF operation of
the analog switch.
10. An analog switch according to claim 1, further including a
first diode in series with the first resistor between the gate of
the first MOSFET and the first fixed voltage terminal, such that
the cathode thereof is arranged on the gate side of the first
MOSFET.
11. An analog switch according to claim 1, further including: a
sixth MOSFET which is a P-channel MOSFET provided between the input
terminal and the output terminal; and a second resistor provided
between the gate of the sixth MOSFET and the second fixed voltage
terminal.
12. An analog switch comprising: an input terminal via which an
analog signal is input; an output terminal via which the analog
signal is output; a sixth P-channel MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) provided between the input
terminal and the output terminal; and a second resistor provided
between the gate of the sixth MOSFET and a second fixed voltage
terminal.
13. An analog switch according to claim 12, wherein the analog
signal is a signal that swings between a negative voltage and a
positive voltage with the ground voltage as the midpoint, and
wherein, in the ON state of the analog switch, the ground voltage
is applied to the second fixed voltage terminal.
14. An analog switch according to claim 12, further including a
seventh P-channel MOSFET which is connected in series with the
sixth MOSFET between the input terminal and the output terminal,
such that the gate thereof is connected to the gate of the sixth
MOSFET so as to form a common gate.
15. An analog switch according to claim 1, wherein the analog
signal is an audio signal, and wherein an electroacoustic
transducing device is connected to the output terminal as a
load.
16. A selector circuit including a plurality of analog switches
according to claim 1, wherein the output terminals of the plurality
of analog switches are connected so as to form a common output
terminal.
17. A selector circuit including a plurality of analog switches
according to claim 1, wherein the input terminals of the plurality
of analog switches are connected so as to form a common input
terminal.
18. An analog switch comprising: an input terminal via which an
analog switch is input; an output terminal via which the analog
signal is output; a first N-channel MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) provided between the input
terminal and the output terminal; and a first diode provided
between the gate of the first MOSFET and a first fixed voltage
terminal, such that the cathode thereof is arranged on the gate
side of the first MOSFET.
19. An analog switch according to claim 18, wherein the analog
signal is a signal that swings between a negative voltage and a
positive voltage with the ground voltage as the midpoint, and
wherein, in the ON state of the analog switch, the power supply
voltage is applied to the first fixed voltage terminal.
20. An analog switch according to claim 18, further including a
second N-channel MOSFET which is connected in series with the first
MOSFET between the input terminal and the output terminal, such
that the gate thereof is connected to the gate of the first MOSFET
so as to form a common gate.
21. An analog switch according to claim 18, further including a
first capacitor in the form of a MIM (Metal Insulator Metal)
capacitance between the input terminal and the gate of the first
MOSFET.
22. An analog switch according to claim 18, further including a
second capacitor in the form of a MIM capacitance between the
output terminal and the gate of the first MOSFET.
23. An analog switch according to claim 20, further including a
third MOSFET provided between the first fixed voltage terminal and
the anode of the first diode, such that the gate voltage is
controlled according to the ON/OFF operation of the analog
switch.
24. An analog switch according to claim 20, further including a
fourth MOSFET provided between the node that connects the first
MOSFET and the second MOSFET and the cathode of the first diode,
such that the gate voltage thereof is controlled according to the
ON/OFF operation of the analog switch.
25. An analog switch according to claim 20, further including a
fifth MOSFET provided between the node that connects the first
MOSFET and the second MOSFET and the ground terminal, such that the
gate voltage thereof is controlled according to the ON/OFF
operation of the analog switch.
26. An analog switch according to claim 18, further including a
first resistor provided in series with the first diode between the
gate of the first MOSFET and the first fixed voltage terminal.
27. An analog switch according to claim 18, further including: a
sixth MOSFET which is a P-channel MOSFET provided between the input
terminal and the output terminal; and a second diode provided
between the gate of the sixth MOSFET and a second fixed voltage
terminal, such that the anode thereof is arranged on the gate side
of the sixth MOSFET.
28. An analog switch comprising: an input terminal via which an
analog signal is input; an output terminal via which the analog
signal is output; a sixth MOSFET (Metal Oxide Semiconductor Field
Effect Transistor) which is a P-channel MOSFET provided between the
input terminal and the output terminal; and a second diode provided
between the gate of the sixth MOSFET and a second fixed voltage
terminal, in the direction in which the anode thereof is arranged
on the gate side of the sixth MOSFET.
29. An analog switch according to claim 28, wherein the analog
signal is a signal that swings between a negative voltage and a
positive voltage with the ground voltage as the midpoint, and
wherein, in the ON state of the analog switch, the ground voltage
is applied to the second fixed voltage terminal.
30. An analog switch according to claim 28, further including a
seventh P-channel MOSFET which is connected in series with the
sixth MOSFET between the input terminal and the output terminal,
such that the gate thereof is connected to the gate of the sixth
MOSFET so as to form a common gate.
31. An analog switch comprising: an input terminal via which an
analog signal is input; an output terminal via which the analog
signal is output; a first MOSFET (Metal Oxide Semiconductor Field
Effect Transistor) provided between the input terminal and the
output terminal; and an impedance element which is provided between
the gate of the first MOSFET and a first fixed voltage terminal,
and which charges/discharges the gate of the first MOSFET according
to the voltage of the analog signal.
32. An analog switch according to claim 18, wherein the analog
signal is an audio signal, and wherein an electroacoustic
transducing device is connected to the output terminal as a
load.
33. A selector circuit including a plurality of analog switches
according to claim 18, wherein the output terminals of the
plurality of analog switches are connected so as to form a common
output terminal.
34. A selector circuit including a plurality of analog switches
according to claim 18, wherein the input terminals of the plurality
of analog switches are connected so as to form a common input
terminal.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to an analog switch.
[0003] 2. Description of the Related Art
[0004] In order to disconnect a transmission path of an analog
signal or in order to switch the transmission path, an analog
switch is employed. In general, a transfer gate is often employed.
The transfer gate includes an N-channel MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) and a P-channel MOSFET
provided in parallel, such that both terminals thereof are
connected to each other to form a common I/O terminal. [0005]
[Patent Document 1]
[0006] Japanese Patent Application Laid Open No. S58-13027 [0007]
[Patent Document 2]
[0008] Japanese Patent Application Laid Open No. S58-13028 [0009]
[Patent Document 3]
[0010] Japanese Patent Application Laid Open No. H9-8625 [0011]
[Patent Document 4]
[0012] Japanese Patent Application Laid Open No. 2006-157132
[0013] Let us consider an arrangement in which an analog signal is
transmitted via a transfer gate. In a state in which the transfer
gate is in the ON state, the high-level voltage (power supply
voltage) is applied to the gate of the N-channel MOSFET, and the
low-level voltage (ground voltage or a negative power supply
voltage) is applied to the gate of the P-channel MOSFET, thereby
providing a fixed voltage state. In this state, when an analog
input signal that changes according to the passage of time is input
via the input terminal of the analog switch, the gate-source
voltages of the MOSFETs change according to the change in the input
signal.
[0014] The change in the gate-source voltages leads to a change in
the ON resistances of the MOSFETs, leading to distortion in the
waveform of the analog signal at the output terminal. In a case in
which a signal which must be transmitted with low distortion, such
as an analog audio signal, analog video signal, etc., is
transmitted via such an analog switch, such an arrangement leads to
a problem of poor sound quality or poor image quality.
SUMMARY OF THE INVENTION
[0015] The present invention has been made in view of the
aforementioned problems. Accordingly, it is a general purpose of
the present invention to provide an analog switch which is capable
of signal transmission with reduced signal distortion.
[0016] 1. An analog switch according to an embodiment of the
present invention comprises: an input terminal via which an analog
signal is input; an output terminal via which the analog signal is
output; a first N-channel MOSFET (Metal Oxide Semiconductor Field
Effect Transistor) provided between the input terminal and the
output terminal; and a first resistor provided between the gate of
the first MOSFET and a first fixed voltage terminal.
[0017] With such an embodiment, the first fixed voltage terminal
and the gate of the first MOSFET are connected in a high-impedance
state by means of the first resistor. In this state, when an analog
signal is input via the input terminal, the input terminal and the
gate are coupled by the gate-source capacitance (or the gate-drain
capacitance), and accordingly, the gate voltage changes in phase
with the input signal. As a result, such an arrangement suppresses
fluctuation in the gate-source voltage of the first MOSFET. This
suppresses fluctuation in the ON-resistance, thereby reducing
distortion in the analog signal.
[0018] Also, the analog signal may be a signal that swings between
a negative voltage and a positive voltage with the ground voltage
as the midpoint. Also, in the ON state of the analog switch, the
power supply voltage may be applied to the first fixed voltage
terminal. That is to say, the first fixed voltage terminal may be a
power supply terminal. This analog switch requires only the power
supply voltage without involving a negative bias voltage, thereby
providing a simple circuit configuration.
[0019] The analog switch according an embodiment may further
include a second N-channel MOSFET which is connected in series with
the first MOSFET between the input terminal and the output
terminal, such that the gate thereof is connected to the gate of
the first MOSFET so as to form a common gate.
[0020] The analog signal may be an audio signal. Furthermore, a
bypass filter configured of the first resistor and the gate-source
capacitance of the first MOSFET may allow a signal in the audio
frequency band to pass through.
[0021] An analog switch according to an embodiment may further
include a first capacitor provided between the input terminal and
the gate of the first MOSFET.
[0022] With such an arrangement, the gate and the input terminal
are coupled by the first capacitor, in addition to being coupled by
the gate-source capacitance (gate-drain capacitance) of the MOSFET.
This improves the response of the gate voltage to the input
voltage, thereby further reducing distortion in the analog
signal.
[0023] An analog switch according to an embodiment may further
include a second capacitor provided between the output terminal and
the gate of the first MOSFET.
[0024] With such an arrangement, the gate and the input terminal
are coupled by the second capacitor, in addition to being coupled
by the gate-source capacitance (gate-drain capacitance) of the
MOSFET. This improves the response of the gate voltage to the input
signal, thereby further reducing signal distortion.
[0025] Also, the analog switch according an embodiment may further
include a third MOSFET provided between the first fixed voltage
terminal and the first resistor, such that the gate voltage is
controlled according to the ON/OFF operation of the analog
switch.
[0026] Also, the analog switch according to an embodiment may
further include a fourth MOSFET provided between the node that
connects the first MOSFET and the second MOSFET and the first
resistor, such that the gate voltage thereof is controlled
according to the ON/OFF operation of the analog switch.
[0027] Also, the analog switch according to an embodiment may
further include a fifth MOSFET provided between the node that
connects the first MOSFET and the second MOSFET and the ground
terminal, such that the gate voltage thereof is controlled
according to the ON/OFF operation of the analog switch.
[0028] Also, the analog switch according to an embodiment may
further include a first diode in series with the first resistor
between the gate of the first MOSFET and the first fixed voltage
terminal, such that the cathode thereof is arranged on the gate
side of the first MOSFET.
[0029] Also, the analog switch according to an embodiment may
further include: a sixth MOSFET which is a P-channel MOSFET
provided between the input terminal and the output terminal; and a
second resistor provided between the gate of the sixth MOSFET and
the second fixed voltage terminal.
[0030] Also, the analog signal may be a signal that swings between
a negative voltage and a positive voltage with the ground voltage
as the midpoint. In the ON state of the analog switch, the ground
voltage may be applied to the second fixed voltage terminal. That
is to say, the second fixed voltage terminal may be the ground
terminal. Alternatively, a negative voltage may be applied to the
second fixed voltage terminal.
[0031] Also, the analog switch according to an embodiment may
further include a seventh P-channel MOSFET which is connected in
series with the sixth MOSFET between the input terminal and the
output terminal, such that the gate thereof is connected to the
gate of the sixth MOSFET so as to form a common gate.
[0032] Another embodiment of the present invention also relates to
an analog switch. The analog switch comprises: an input terminal
via which an analog signal is input; an output terminal via which
the analog signal is output; a first MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) provided between the input
terminal and the output terminal; and an impedance element which is
provided between the gate of the first MOSFET and a first fixed
voltage terminal, and which charges/discharges the gate of the
first MOSFET according to the voltage of the analog signal.
[0033] Also, the analog signal may be an audio signal. Furthermore,
an electroacoustic transducing device may be connected to the
output terminal as a load. The "electroacoustic transducing device"
represents a device which converts an electronic analog signal into
an acoustic wave (sound), examples of which include speakers,
headphones, earphones, etc. Such an electroacoustic transducing
device has a small impedance of from several .OMEGA. to tens of
.OMEGA.. Thus, the above-described analog switch, which is capable
of suppressing fluctuation in the ON-resistance of the MOSFET, is
suitably employed.
[0034] Yet another embodiment of the present invention relates to a
selector circuit. The selector circuit includes the above-described
multiple analog switches. The output terminals of the multiple
analog switches are connected so as to form a common output
terminal.
[0035] Such an embodiment offers a multiplexer which provides
signal transmission with low distortion.
[0036] Yet another embodiment of the present invention also relates
to a selector circuit. The selector circuit includes the
above-described multiple analog switches. The input terminals of
the multiple analog switches are connected so as to form a common
input terminal.
[0037] Such an embodiment offers a demultiplexer which provides
signal transmission with low distortion.
[0038] 2. Yet another embodiment of the present invention also
relates to an analog switch. The analog switch comprises: an input
terminal via which an analog switch is input; an output terminal
via which the analog signal is output; a first N-channel MOSFET
(Metal Oxide Semiconductor Field Effect Transistor) provided
between the input terminal and the output terminal; and a first
diode provided between the gate of the first MOSFET and a first
fixed voltage terminal, such that the cathode thereof is arranged
on the gate side of the first MOSFET.
[0039] With such an embodiment, the first fixed voltage terminal
and the gate of the first MOSFET are connected in a high-impedance
state by means of the first diode. In this state, when an analog
signal is supplied via the input terminal, the input terminal and
the gate are coupled by the gate-source capacitance (or the
gate-drain capacitance), thereby changing the gate voltage in phase
with the input signal. As a result, such an arrangement suppresses
fluctuation in the gate-source voltage of the first MOSFET. This
suppresses fluctuation in the ON-resistance, thereby reducing
distortion in the analog signal.
[0040] In the ON state of the analog switch, the power supply
voltage may be applied to the first fixed voltage terminal. That is
to say, the first fixed voltage terminal may be the power supply
terminal. Such an analog switch requires only the power supply
voltage without involving a negative bias voltage, thereby
providing a simple circuit configuration.
[0041] An analog switch according to an embodiment may further
include a second MOSFET which is an N-channel MOSFET connected in
series with the first MOSFET between the input terminal and the
output terminal, such that the gate thereof is connected to the
gate of the first MOSFET so as to form a common gate.
[0042] An analog switch according to an embodiment may further
include a first capacitor provided between the input terminal and
the gate of the first MOSFET.
[0043] With such an arrangement, the gate and the input terminal
are coupled by the first capacitor, in addition to being coupled by
the gate-source capacitance (gate-drain capacitance) of the MOSFET.
This improves the response of the gate voltage to the input
voltage, thereby further reducing signal distortion.
[0044] Also, the analog switch according to an embodiment may
further include a second capacitor between the output terminal and
the gate of the first MOSFET.
[0045] With such an arrangement, the gate and the input terminal
are coupled by the second capacitor, in addition to being coupled
by the gate-source capacitance (gate-drain capacitance) of the
MOSFET. This improves the response of the gate voltage to the input
voltage, thereby further reducing signal distortion.
[0046] Also, the analog switch according to an embodiment may
further include a third MOSFET provided between the first fixed
voltage terminal and the anode of the first diode, such that the
gate voltage is controlled according to the ON/OFF operation of the
analog switch.
[0047] Also, the analog switch according to an embodiment may
further include a fourth MOSFET provided between the node that
connects the first MOSFET and the second MOSFET and the cathode of
the first diode, such that the gate voltage thereof is controlled
according to the ON/OFF operation of the analog switch.
[0048] Also, the analog switch according to an embodiment may
further include a fifth MOSFET provided between the node that
connects the first MOSFET and the second MOSFET and the ground
terminal, such that the gate voltage thereof is controlled
according to the ON/OFF operation of the analog switch.
[0049] Also, the analog switch according to an embodiment may
further include a first resistor provided in series with the first
diode between the gate of the first MOSFET and the first fixed
voltage terminal.
[0050] Such an arrangement further includes the resistor, thereby
allowing the impedance between the gate and the first fixed voltage
terminal to be adjusted. Thus, the gain properties and the phase
properties of the analog switch can be adjusted.
[0051] Also, the analog switch according to an embodiment may
further include: a sixth MOSFET which is a P-channel MOSFET
provided between the input terminal and the output terminal; and a
second diode provided between the gate of the sixth MOSFET and a
second fixed voltage terminal, such that the anode thereof is
arranged on the gate side of the sixth MOSFET.
[0052] Yet another embodiment of the present invention also relates
to an analog switch. The analog switch comprises: an input terminal
via which an analog signal is input; an output terminal via which
the analog signal is output; a sixth MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) which is a P-channel MOSFET
provided between the input terminal and the output terminal; and a
second diode provided between the gate of the sixth MOSFET and a
second fixed voltage terminal, in the direction in which the anode
thereof is arranged on the gate side of the sixth MOSFET.
[0053] With such an embodiment, the second fixed voltage terminal
and the gate of the second MOSFET are connected in a high-impedance
state by means of the first diode. In this state, when an analog
signal is supplied via the input terminal, the input terminal and
the gate are coupled by the gate-source capacitance (or the
gate-drain capacitance), thereby changing the gate voltage in phase
with the input signal. As a result, such an arrangement suppresses
fluctuation in the gate-source voltage of the first MOSFET. This
suppresses fluctuation in the ON-resistance thereof, thereby
reducing distortion in the analog signal.
[0054] In the ON state of the analog switch, the ground voltage may
be applied to the second fixed voltage terminal. That is to say,
the second fixed voltage terminal may be the ground terminal.
Alternatively, the second fixed voltage terminal may be a negative
voltage terminal.
[0055] Also, the analog switch according to an embodiment may
further include a seventh P-channel MOSFET which is connected in
series with the sixth MOSFET between the input terminal and the
output terminal, such that the gate thereof is connected to the
gate of the sixth MOSFET so as to form a common gate.
[0056] Yet another embodiment of the present invention also relates
to an analog switch. The analog switch comprises: an input terminal
via which an analog signal is input; an output terminal via which
the analog signal is output; a first MOSFET (Metal Oxide
Semiconductor Field Effect Transistor) provided between the input
terminal and the output terminal; and an impedance element which is
provided between the gate of the first MOSFET and a first fixed
voltage terminal, and which charges/discharges the gate of the
first MOSFET according to the voltage of the analog signal.
[0057] Also, the analog signal may be an audio signal. Furthermore,
an electroacoustic transducing device may be connected to the
output terminal as a load. The "electroacoustic transducing device"
represents a device which converts an electronic analog signal into
an acoustic wave (sound), examples of which include speakers,
headphones, earphones, etc. Such an electroacoustic transducing
device has a small impedance of from several .OMEGA. to tens of
.OMEGA.. Thus, the above-described analog switch, which is capable
of suppressing fluctuation in the ON-resistance of the MOSFET, is
suitably employed.
[0058] Yet another embodiment of the present invention relates to a
selector circuit. The selector circuit includes the above-described
multiple analog switches. The output terminals of the multiple
analog switches are connected so as to form a common output
terminal.
[0059] Such an embodiment offers a multiplexer which provides
signal transmission with low distortion.
[0060] Yet another embodiment of the present invention also relates
to a selector circuit. The selector circuit includes the
above-described multiple analog switches. The input terminals of
the multiple analog switches are connected so as to form a common
input terminal.
[0061] Such an embodiment offers a demultiplexer which provides
signal transmission with low distortion.
[0062] It is to be noted that any arbitrary combination or
rearrangement of the above-described structural components and so
forth is effective as and encompassed by the present
embodiments.
[0063] Moreover, this summary of the invention does not necessarily
describe all necessary features so that the invention may also be a
sub-combination of these described features.
BRIEF DESCRIPTION OF THE DRAWINGS
[0064] Embodiments will now be described, by way of example only,
with reference to the accompanying drawings which are meant to be
exemplary, not limiting, and wherein like elements are numbered
alike in several Figures, in which:
[0065] FIG. 1 is a circuit diagram which shows a principal part of
the configuration of an analog switch according to a first
embodiment;
[0066] FIG. 2 is a time chart which shows the operation states of
the analog switch shown in FIG. 1;
[0067] FIG. 3 is a circuit diagram which shows a configuration of
an analog switch according to a first modification of the first
embodiment;
[0068] FIG. 4 is a circuit diagram which shows a configuration of
an analog switch according to a second modification of the first
embodiment;
[0069] FIG. 5 is a circuit diagram which shows a configuration of
an analog switch according to a third modification of the first
embodiment;
[0070] FIGS. 6A and 6B are circuit diagrams which show the
configurations of analog switches according to a fourth
modification of the first embodiment;
[0071] FIG. 7 is a circuit diagram which shows a configuration of
an analog switch according to a fifth modification of the first
embodiment;
[0072] FIGS. 8A and 8B are block diagrams which show the
configurations of selector circuits using the analog switches;
[0073] FIG. 9 is a circuit diagram which shows the principal part
of the configuration of the analog switch according to a second
embodiment;
[0074] FIG. 10 is a time chart which shows the operation states of
the analog switch shown in FIG. 9;
[0075] FIG. 11 is a circuit diagram which shows a configuration of
an analog switch according to a first modification;
[0076] FIG. 12 is a circuit diagram which shows a configuration of
an analog switch according to a second modification;
[0077] FIG. 13 is a circuit diagram which shows a configuration of
an analog switch according to a third modification;
[0078] FIGS. 14A and 14B are circuit diagrams which show the
configurations of analog switches according to a fourth
modification;
[0079] FIG. 15 is a circuit diagram which shows a configuration of
an analog switch according to a fifth modification; and
[0080] FIGS. 16A and 16B are block diagrams which show the
configurations of selector circuits using the analog switches.
DETAILED DESCRIPTION OF THE INVENTION
[0081] The invention will now be described based on preferred
embodiments which do not intend to limit the scope of the present
invention but exemplify the invention. All of the features and the
combinations thereof described in the embodiment are not
necessarily essential to the invention.
[0082] In the present specification, the state represented by the
phrase "the member A is connected to the member B" includes: a
state in which the member A and the member B are physically and
directly connected to each other; and a state in which the member A
and the member B are indirectly connected to each other via another
member that does not affect the electric connection therebetween.
In the same way, the state represented by the phrase "the member C
is provided between the member A and the member B" includes a state
in which these members are indirectly connected to each other via
another member that does not affect the electric connection
therebetween, in addition to the state in which the member A and
the member C, or the member B and the member C are directly
connected.
First Embodiment
[0083] FIG. 1 is a circuit diagram which shows a principal part of
the configuration of an analog switch 10a according to a first
embodiment. The analog switch 10a includes an input terminal P1, an
output terminal P2, a first resistor R1, and a capacitor C1.
[0084] In the ON state, via the output terminal P2, the analog
switch 10a outputs the input signal IN input via the input terminal
P1. In the OFF state, the analog switch 10a sets the output
terminal P2 to a state in which it is unrelated to the input signal
IN, e.g., a high-impedance state or a state in which the output
terminal P2 is fixed at a predetermined voltage.
[0085] The input signal IN is an analog signal which must be
transmitted with low distortion, examples of which include an audio
signal, a video signal, etc. Also, the input signal IN may be any
one of other desired signals. Description will be made below
regarding an arrangement in which the input signal IN has a
waveform that swings between a positive voltage and a negative
voltage with the ground voltage (0 V) as the midpoint.
[0086] A first transistor M1 is an N-channel MOSFET, and is
provided between the input terminal P1 and the output terminal P2.
For convenience of explanation, the terminal of the first
transistor M1 on the input terminal P1 side will be referred to as
the "source", and the terminal thereof on the output terminal P2
side will be referred to as the "drain".
[0087] The first resistor R1 is provided between the gate of the
first transistor M1 and a first fixed voltage terminal P3.
[0088] When the analog switch 10a is in the ON state, the power
supply voltage Vdd is applied to the first fixed voltage terminal
P3. When the analog switch 10a is to be switched to the OFF state,
the first transistor M1 should be switched to the OFF state. The
switching method is not restricted in particular. For example, the
ground voltage or a negative voltage may be applied to the first
fixed voltage terminal P3. Alternatively, an arrangement may be
made in which a switching element may be provided in series with
the first resistor R1, and the bias voltage applied to the gate of
the first transistor M1 is disconnected by turning off the
switching element. FIG. 1 shows only a most basic configuration of
the analog switch 10a, and does not show the configuration which
allows the analog switch 10a to be switched between the ON state
and the OFF state. In other words, FIG. 1 shows a circuit
equivalent to the analog switch 10a in the ON state.
[0089] A first capacitor C1 is provided between the gate of the
first transistor M1 and the input terminal P1. The first capacitor
C1 may be provided in the form of a MIM (Metal Insulator Metal)
capacitance. Also, the gate-source capacitance of the first
transistor M1 may be used as the first capacitor C1. An arrangement
in which the first capacitor C1 is formed in the form of a MIM
capacitance has the advantage that the capacitance can be designed
independent of the size of the first transistor M1. In a case in
which the gate-source capacitance is used as the first capacitor
C1, the transistor size is designed so as to provide a desired
capacitance. The capacitance formed between the input terminal P1
and the gate of the first transistor M1 will be referred to as the
"first capacitor C1" hereafter, regardless of whether it is
provided in the form of a MIM capacitance or a parasitic
capacitance.
[0090] In the same way, a second capacitor may be provided between
the gate of the first transistor M1 and the output terminal P2. It
should be noted that the second capacitor is provided in the form
of the gate-drain capacitance of the first transistor M1, which is
not shown in FIG. 1. Furthermore, a MIM capacitance may be
provided, in addition to the gate-drain capacitance.
[0091] With regard to the analog switch 10a shown in FIG. 1, the
first capacitor C1 and the first resistor R1 form a bypass filter
between the input terminal P1 and the gate of the first transistor
M1. The frequency band of the bypass filter should be designed such
that it matches the frequency band of the analog signal IN. For
example, in a case in which the analog signal IN is an audio
signal, the bandpass filter is designed so as to allow an analog
signal in the audio frequency band to pass through. As an example,
the bypass filter is preferably designed with an R1 of around 100
M.OMEGA., and a C1 of around 100 pF.
[0092] The above is a basic configuration of the analog switch 10a
according to the embodiment. Next, description will be made
regarding the operation of the analog switch 10a shown in FIG. 1.
FIG. 2 is a time chart which shows the operation state of the
analog switch 10a shown in FIG. 1. The vertical axis and the
horizontal axis in FIG. 2 are expanded or reduced as appropriate in
order to facilitate understanding. Furthermore, simple waveforms
are shown in the drawing in order to facilitate understanding.
[0093] In order to clarify the effects of the circuit shown in FIG.
1, let us consider the operation of a circuit which does not
include the first resistor R1. For example, in a case in which the
first resistor R1 is not provided to the gate of the transistor, as
in conventional transfer gates, the gate voltage Vg of the first
transistor M1 is fixed to the power supply voltage Vdd, as
indicated by the broken line shown in FIG. 2. Furthermore, the
gate-source voltage Vgs of the first transistor M1 changes over
time corresponding to the voltage value of the input signal IN, as
indicated by the broken line shown in FIG. 2. As a result, the ON
resistance of the first transistor M1 fluctuates, leading to
fluctuation of the drain-source voltage of the first transistor M1.
This leads to distortion in the output signal OUT with respect to
the input signal IN.
[0094] On the other hand, the analog switch 10a shown in FIG. 1
operates as follows. The connection between the first fixed voltage
terminal P3 and the gate of the first transistor M1 is made in a
high-impedance manner by means of the first resistor R1. That is to
say, the gate voltage Vg of the first transistor M1 is not fixed to
the power supply voltage Vdd. The first resistor R1 provides a
function as a device for charging the first transistor M1.
[0095] In this state, when the input signal IN is supplied to the
input terminal P1 using the ground voltage (0 V) as the bias point
as shown in FIG. 2, the gate voltage Vg changes in phase with the
input signal IN, since the input terminal P1 and the gate are
coupled by means of the first capacitor C1.
[0096] The voltage of the input signal IN corresponds to the source
voltage of the first transistor M1. The source-gate voltage Vgs of
the first transistor M1 is the potential difference between the
gate voltage Vg of the first transistor M1 and the voltage of the
input signal IN. As shown in FIG. 2, after the input signal IN is
input, fluctuation of the gate-source voltage Vgs is reduced
according to the passage of time, following which the gate-source
voltage Vgs is stabilized to approximately a constant value. By
stabilizing the gate-source voltage Vgs of the first transistor M1,
fluctuation of the ON resistance Ron is suppressed. Thus, such an
arrangement reduces distortion in the output signal OUT with
respect to the input signal IN.
[0097] In particular, in a case in which a load with an impedance
of from several .OMEGA. to tens of .OMEGA., such as a speaker,
headphones, or the like, is connected to the output terminal P2,
noticeable distortion occurs in the output signal OUT due to the
fluctuation of the ON resistance of the first transistor M1.
Accordingly, the analog switch 10 shown in FIG. 1 and modifications
described later can be suitably employed in an audio system.
[0098] In general, with conventional transfer gates, in order to
transmit the input signal IN that swings between a negative voltage
and a positive voltage using the voltage of 0 V as the bias point,
the gate voltage for the P-channel MOSFET is biased to the negative
power supply voltage (-Vdd). On the other hand, the circuit shown
in FIG. 1 uses only the power supply voltage Vdd without involving
the negative power supply, thereby providing a simple circuit
configuration.
[0099] Description will be made regarding several modifications
configured based upon the configuration shown in FIG. 1.
[0100] FIG. 3 is a circuit diagram which shows an analog switch 10b
according to a first modification. The analog switch 10b shown in
FIG. 3 further includes a second transistor M2 and a second
capacitor C2, in addition to the configuration of the analog switch
10a shown in FIG. 1.
[0101] The second transistor M2 is an N-channel MOSFET, which is
the same type as the first transistor M1. The second transistor M2
and the first transistor M1 are connected in series between the
input terminal P1 and the output terminal P2. Furthermore, the gate
of the second transistor M2 and the gate of the first transistor M1
are connected to each other so as to form a common gate. For
convenience of explanation, the terminal of the second transistor
M2 on the output terminal P2 side will be referred to as the
"source", and the terminal thereof on the first transistor M1 side
will be referred to as the "drain".
[0102] The back gate of the first transistor M1 is preferably
connected to a point on the node N1 side between the first
transistor M1 and the second transistor M2, i.e., a point on the
drain side of the first transistor M1. The back gate of the second
transistor M2 is preferably connected to a point on the node N1
side, i.e., a point on the drain side of the second transistor
M2.
[0103] The second capacitor C2 is provided between the gate of the
second transistor M2 and the output terminal 22. The second
capacitor C2 may be provided in the form of a MIM (Metal Insulator
Metal) capacitance. Also, the gate-source capacitance of the second
transistor M2 may be used as the second capacitor C2. The
capacitance formed between the output terminal 22 and the gate of
the second transistor M2 will be referred to as the "second
capacitor C2" hereafter, regardless of whether it is provided in
the form of a MIM capacitance or a parasitic capacitance.
[0104] With the modification shown in FIG. 3, the body diode (not
shown) of the first transistor M1 and the body diode (not shown) of
the second transistor M2 are connected in opposing directions
between the input terminal P1 and the output terminal P2. As a
result, in the OFF state of the analog switch 10b, such an
arrangement provides improved isolation between the input terminal
P1 and the output terminal P2.
[0105] FIG. 4 is a circuit diagram which shows the configuration of
an analog switch 10c according to a second modification. The analog
switch 10c shown in FIG. 4 includes a third transistor M3, a fourth
transistor M4, a fifth transistor MS, an eighth transistor M8, and
a ninth transistor M9, in addition to the configuration shown in
FIG. 3. The transistors M3, M4, M5, M8, and M9 are provided in
order to allow the analog switch 10c to be switched between the ON
state and the OFF state. It should be noted that, in FIG. 4, the
first capacitor C1 and the second capacitor C2 are not shown.
[0106] The third transistor M3 is provided between the first fixed
voltage terminal P3 and the first resistor R1. The gate voltage
thereof is controlled according to the ON/OFF operation of the
analog switch 10c. That is to say, a control signal #CNT (in this
specification, the symbol "#" indicates "logical inversion"), which
is switched to the low-level state when the analog switch 10c is
switched to the ON state, is input to the gate of the third
transistor M3.
[0107] The fourth transistor M4 is provided between the node N1
that connects the first transistor M1 and the second transistor M2
and the first resistor R1. The gate voltage of the fourth
transistor M4 is controlled according to the ON/OFF operation of
the analog switch 10c. A resistor R3 is provided between the gate
of the fourth transistor M4 and the node N1. Furthermore, the
eighth transistor M8 is provided between the power supply terminal
and the gate of the fourth transistor M4. With such an arrangement,
a control signal CNT is supplied to the gate of the eighth
transistor M8. When the control signal CNT is switched to the
high-level state, the eighth transistor M8 is switched to the OFF
state. In this state, the gate of the fourth transistor M4 is
pulled down by the resistor R3, and accordingly, the fourth
transistor M4 is switched to the OFF state. When the control signal
CNT is switched to the low-level state, the eighth transistor M8 is
switched to the ON state. In this state, the gate of the fourth
transistor M4 is switched to the high-level state, and accordingly,
the fourth transistor M4 is switched to the ON state.
[0108] The fifth transistor M5 and the ninth transistor M9 are
provided in series between the node N1 that connects the first
transistor M1 and the second transistor M2 and the ground terminal.
The gate voltages of the fifth transistor M5 and the ninth
transistor M9 are controlled according to the control signal CNT.
The gate of the fifth transistor M5 and the gate of the fourth
transistor M4 are connected to each other so as to form a common
gate. When the control signal CNT is switched to the high-level
state, and the eighth transistor M8 is accordingly switched to the
OFF state, the gate of the fifth transistor M5 is pulled up by
means of the resistor R3, thereby switching the fifth transistor M5
to the OFF state. Furthermore, the control signal #CNT is input to
the gate of the ninth transistor M9.
[0109] With the analog switch 10c shown in FIG. 4, when the control
signal CNT is in the high-level state, the fourth transistor M4,
the fifth transistor MS, and the ninth transistor M9 are in the OFF
state, and the third transistor M3 is in the ON state, thereby
providing a state equivalent to the state of the analog switch 10b
shown in FIG. 3. In this state, the input signal IN input via the
input terminal P1 is output via the output terminal P2.
[0110] When the control signal CNT is switched to the low-level
state, the fifth transistor M5 and the ninth transistor M9 are
switched to the ON state, and the node N1 is grounded. Furthermore,
the fourth transistor M4 is switched to the ON state, and
accordingly, the gates of the first transistor M1 and the second
transistor M2 are grounded. As a result, at least one of the first
transistor M1 and the second transistor M2 is switched to the OFF
state, thereby disconnecting the connection between the input
terminal P1 and the output terminal P2. Furthermore, the third
transistor M3 is switched to the OFF state, thereby preventing
unnecessary current flow from the first fixed voltage terminal P3
to the ground.
[0111] Such an arrangement including the fifth transistor M5, the
ninth transistor M9, the fourth transistor M4, the third transistor
M3, and the eighth transistor M8 has the above-described advantage.
Also, several transistors may be selectively employed.
[0112] FIG. 5 is a circuit diagram which shows a configuration of
an analog switch 10d according to a third modification. The analog
switch 10d shown in FIG. 5 further includes a sixth transistor M6,
a second resistor R2, a third capacitor C3, and a fourth capacitor
C4, in addition to the configuration of the analog switch 10a shown
in FIG. 1.
[0113] The sixth transistor M6 is a P-channel MOSFET, and is
provided between the input terminal P1 and the output terminal P2.
The second resistor R2 is provided between the gate of the sixth
transistor M6 and the second fixed voltage terminal P4. In the ON
state of the analog switch 10d, the ground voltage is preferably
applied to the second fixed voltage terminal P4.
[0114] The third capacitor C3 is provided between the gate of the
second transistor M2 and the input terminal P1. The fourth
capacitor C4 is provided between the gate of the second transistor
M2 and the output terminal P2. The third capacitor C3 and the
fourth capacitor C4 may be provided in the form of a MIM
capacitance or a parasitic capacitance of the sixth transistor M6
(gate-source capacitance or gate-drain capacitance).
[0115] With the circuit shown in FIG. 5, the gate of the sixth
transistor M6 is grounded via the second resistor R2, thereby
providing a high-impedance state. The first terminal P1 and the
gate of the sixth transistor M6 are coupled by means of the third
capacitor C3. Accordingly, the gate voltage of the sixth transistor
M6 swings in phase with the input signal IN. As a result, the
gate-source voltage of the sixth transistor M6 is maintained at a
constant voltage. This suppresses fluctuation in the ON-resistance
of the sixth transistor M6, thereby reducing distortion in the
signal.
[0116] With the analog switch 10d shown in FIG. 5, the synthetic
impedance formed between the input terminal P1 and the output
terminal P2 is smaller than that shown in FIG. 1, thereby reducing
signal decay (or loss).
[0117] FIG. 6A and FIG. 6B are circuit diagrams which show the
configurations of analog switches 10e and 10f according to a fourth
modification. FIG. 6A shows a modification of the circuit shown in
FIG. 5, in which the fifth transistor M5, the first resistor R1,
the first capacitor C1, and the second capacitor C2 are omitted.
Viewed from a different perspective, the analog switch 10e shown in
FIG. 6A has a circuit configuration in which the first transistor
M1 of the analog switch 10a shown in FIG. 1 is replaced by a
P-channel MOSFET.
[0118] The analog switch 10f shown in FIG. 6B includes a seventh
transistor M7, in addition to the configuration shown in FIG. 6A.
The seventh transistor M7 is a P-channel MOSFET, and is connected
in series with the sixth transistor M6 between the input terminal
P1 and the output terminal P2. The gate of the seventh transistor
M7 and the gate of the sixth transistor M6 are connected to each
other so as to form a common gate. That is to say, it can be
understood that the analog switches 10e and 10f shown in FIG. 6A
and FIG. 6B have the same circuit configurations as those of the
analog switches 10a and 10b shown in FIG. 1 and FIG. 3,
respectively, except that the N-channel MOSFETs are replaced by the
P-channel MOSFETs, and the diodes are provided in opposing
directions. Accordingly, the modification described with reference
to FIG. 4 can also be applied to the circuits shown in FIGS. 6A and
6B.
[0119] FIG. 7 is a circuit diagram which shows a configuration of
an analog switch 10g according to a fifth modification. The analog
switch 10g shown in FIG. 7 further includes a first diode D1
provided in series with the first resistor R1 between the gate of
the first transistor M1 and the first fixed voltage terminal P3.
The first diode D1 is arranged such that the cathode is arranged on
the gate side of the first transistor M1. The positions of the
resistor R1 and the first diode D1 may be exchanged. Also, a second
diode may be provided in series with the second resistor R2 shown
in FIG. 5 and FIGS. 6A and 6B. The second diode is arranged such
that the anode thereof is arranged on the gate side of the
P-channel MOSFET.
[0120] Viewed from a different perspective, the above-described
analog switches can be understood as follows. That is to say, an
analog switch according to an embodiment includes: an input
terminal P1 via which an analog signal IN is input; an output
terminal P2 via which an analog signal OUT is output; a MOSFET
which is provided between the input terminal P1 and the output
terminal P2; and an impedance element which is provided between the
gate of the MOSFET and the fixed voltage terminal, and which
charges the gate of the MOSFET. The term "impedance element"
represents a circuit device element having impedance which allows
the gate voltage of the MOSFET to change without being fixed to the
voltage at the fixed voltage terminal. With the embodiment, the
impedance element is provided in the form of a diode or a
combination of a diode and a resistor.
[0121] FIGS. 8A and 8B are block diagrams which show the
configurations of selector circuits employing any one of the
above-described analog switches 10 through 10g (which will be
simply referred to as the "analog switch 10"). FIG. 8A shows a
multiplexer 20, and FIG. 8B shows a demultiplexer 30. The
multiplexer shown in FIG. 8A includes multiple analog switches 10.
Each analog switch may be any one of the above-described circuits.
The output terminals of the multiple analog switches 10 are
connected to each other so as to form a common output terminal. The
input terminals receive respective signals that differ from one
another. The demultiplexer 30 shown in FIG. 8B includes multiple
analog switches 10. Each analog switch may be any one of the
above-described circuits. The input terminals of the multiple
analog switches 10 are connected to each other so as to form a
common input terminal. The output terminals are connected to
respective circuit blocks that differ from one another. Each of the
multiplexer 20 and the demultiplexer 30 has the advantage of
reducing distortion in the transmitted signal.
[0122] Description has been made in the embodiment regarding an
arrangement in which an analog signal is transmitted via the analog
switch 10. Also, a digital signal may be transmitted via the analog
switch 10. Also, a differential signal may be transmitted using two
paired analog switches.
Second Embodiment
[0123] FIG. 9 is a circuit diagram which shows a principal part of
the configuration of an analog switch 10a according to a second
embodiment. The analog switch 10a includes an input terminal P1, an
output terminal P2, a first diode D1, and a capacitor C1.
[0124] In the ON state, via the output terminal P2, the analog
switch 10a outputs the input signal IN input via the input terminal
P1. In the OFF state, the analog switch 10a sets the output
terminal P2 to a state in which it is unrelated to the input signal
IN, e.g., a high-impedance state or a state in which the output
terminal P2 is fixed at a predetermined voltage.
[0125] The input signal IN is an analog signal which must be
transmitted with low distortion, examples of which include an audio
signal, a video signal, etc. Also, the input signal IN may be any
one of other desired signals. Description will be made below
regarding an arrangement in which the input signal IN has a
waveform that swings between a positive voltage and a negative
voltage with the ground voltage (0 V) as the midpoint.
[0126] A first transistor M1 is an N-channel MOSFET, and is
provided between the input terminal P1 and the output terminal P2.
For convenience of explanation, the terminal of the first
transistor M1 on the input terminal P1 side will be referred to as
the "source", and the terminal thereof on the output terminal P2
side will be referred to as the "drain".
[0127] The first diode D1 is provided between the gate of the first
transistor M1 and a first fixed voltage terminal P3. The first
diode D1 is arranged such that the cathode thereof is arranged on
the gate side of the first transistor M1, and the anode thereof is
arranged on the first fixed voltage terminal P3 side.
[0128] When the analog switch 10a is in the ON state, the power
supply voltage Vdd is applied to the first fixed voltage terminal
P3. When the analog switch 10a is to be switched to the OFF state,
the first transistor M1 should be switched to the OFF state. The
switching method is not restricted in particular. For example, the
ground voltage or a negative voltage may be applied to the first
fixed voltage terminal P3. Alternatively, an arrangement may be
made in which a switching element may be provided in series with
the first diode D1, and the bias voltage applied to the gate of the
first transistor M1 is disconnected by turning off the switching
element. FIG. 9 shows only a most basic configuration of the analog
switch 10a, and does not show the configuration which allows the
analog switch 10a to be switched between the ON state and the OFF
state. In other words, FIG. 9 shows a circuit equivalent to the
analog switch 10a in the ON state.
[0129] A first capacitor C1 is provided between the gate of the
first transistor M1 and the input terminal P1. The first capacitor
C1 may be provided in the form of a MIM (Metal Insulator Metal)
capacitance. Also, the gate-source capacitance of the first
transistor M1 may be used as the first capacitor C1. An arrangement
in which the first capacitor C1 is formed in the form of a MIM
capacitance has the advantage that the capacitance can be designed
independent of the size of the first transistor M1. In a case in
which the gate-source capacitance is used as the first capacitor
C1, the transistor size is designed so as to provide a desired
capacitance. The capacitance formed between the input terminal P1
and the gate of the first transistor M1 will be referred to as the
"first capacitor C1" hereafter, regardless of whether it is
provided in the form of a MIM capacitance or a parasitic
capacitance.
[0130] In the same way, a second capacitor may be provided between
the gate of the first transistor M1 and the output terminal P2. It
should be noted that the second capacitor is provided in the form
of the gate-drain capacitance of the first transistor M1, which is
not shown in FIG. 9. Furthermore, a MIM capacitance may be
provided, in addition to the gate-drain capacitance.
[0131] The above is a basic configuration of the analog switch 10a
according to the embodiment. Next, description will be made
regarding the operation of the analog switch 10a shown in FIG. 9.
FIG. 10 is a time chart which shows the operation state of the
analog switch 10a shown in FIG. 9. The vertical axis and the
horizontal axis in FIG. 10 are expanded or reduced as appropriate
in order to facilitate understanding. Furthermore, simple waveforms
are shown in the drawing in order to facilitate understanding.
[0132] In order to clarify the effects of the circuit shown in FIG.
9, let us consider the operation of a circuit which does not
include the first diode D1. For example, in a case in which the
first diode D1 is not provided to the gate of the transistor, as in
conventional transfer gates, the gate voltage Vg of the first
transistor M1 is fixed to the power supply voltage Vdd, as
indicated by the broken line shown in FIG. 10. Furthermore, the
gate-source voltage Vgs of the first transistor M1 changes over
time corresponding to the voltage value of the input signal IN, as
indicated by the broken line shown in FIG. 10. As a result, the ON
resistance of the first transistor M1 fluctuates, leading to
fluctuation of the drain-source voltage of the first transistor M1.
This leads to distortion in the output signal OUT with respect to
the input signal IN.
[0133] On the other hand, the analog switch 10a shown in FIG. 9
operates as follows. The connection between the first fixed voltage
terminal P3 and the gate of the first transistor M1 is made in a
high-impedance manner by means of the first diode D1. That is to
say, the gate voltage Vg of the first transistor M1 is not fixed to
the power supply voltage Vdd. The first diode D1 provides a
function as a device for charging the first transistor M1.
[0134] In this state, when the input signal IN is supplied to the
input terminal P1 using the ground voltage (0 V) as the bias point
as shown in FIG. 10, the gate voltage Vg changes in phase with the
input signal IN, since the input terminal P1 and the gate are
coupled by means of the first capacitor C1. As shown in FIG. 10,
the gate voltage Vg is clamped at (Vdd-Vf) or more by means of the
first diode D1.
[0135] The voltage of the input signal IN corresponds to the source
voltage of the first transistor M1. The source-gate voltage Vgs of
the first transistor M1 is the potential difference between the
gate voltage Vg of the first transistor M1 and the voltage of the
input signal IN. As shown in FIG. 10, after the input signal IN is
input, fluctuation of the gate-source voltage Vgs is reduced
according to the passage of time, following which the gate-source
voltage Vgs is stabilized to approximately a constant value. By
stabilizing the gate-source voltage Vgs of the first transistor M1,
fluctuation of the ON resistance Ron is suppressed. Thus, such an
arrangement reduces distortion in the output signal OUT with
respect to the input signal IN.
[0136] In particular, in a case in which a load with an impedance
of from several .OMEGA. to tens of .OMEGA., such as a speaker,
headphones, or the like, is connected to the output terminal P2,
noticeable distortion occurs in the output signal OUT due to the
fluctuation of the ON resistance of the first transistor M1.
Accordingly, the analog switch 10 shown in FIG. 9 and modifications
described later can be suitably employed in an audio system.
[0137] In general, with conventional transfer gates, in order to
transmit the input signal IN that swings between a negative voltage
and a positive voltage using the voltage of 0 V as the bias point,
the gate voltage for the P-channel MOSFET is biased to the negative
power supply voltage (-Vdd). On the other hand, the circuit shown
in FIG. 9 uses only the power supply voltage Vdd without involving
the negative power supply, thereby providing a simple circuit
configuration.
[0138] With such an arrangement, the gate of the first transistor
M1 is set to the high-impedance state by means of the first diode
D. This reduces a phase delay as compared with an arrangement in
which the high-impedance state is provided by means of a
resistor.
[0139] Description will be made regarding several modifications
configured based upon the configuration shown in FIG. 9.
[0140] FIG. 11 is a circuit diagram which shows an analog switch
10b according to a first modification. The analog switch 10b shown
in FIG. 11 further includes a second transistor M2 and a second
capacitor C2, in addition to the configuration of the analog switch
10a shown in FIG. 9.
[0141] The second transistor M2 is an N-channel MOSFET, which is
the same type as the first transistor M1. The second transistor M2
and the first transistor M1 are connected in series between the
input terminal P1 and the output terminal P2. Furthermore, the gate
of the second transistor M2 and the gate of the first transistor M1
are connected to each other so as to form a common gate. For
convenience of explanation, the terminal of the second transistor
M2 on the output terminal P2 side will be referred to as the
"source", and the terminal thereof on the first transistor M1 side
will be referred to as the "drain".
[0142] The back gate of the first transistor M1 is preferably
connected to a point on the node N1 side between the first
transistor M1 and the second transistor M2, i.e., a point on the
drain side of the first transistor M1. The back gate of the second
transistor M2 is preferably connected to a point on the node N1
side, i.e., a point on the drain side of the second transistor
M2.
[0143] The second capacitor C2 is provided between the gate of the
second transistor M2 and the output terminal P2. The second
capacitor C2 may be provided in the form of a MIM (Metal Insulator
Metal) capacitance. Also, the gate-source capacitance of the second
transistor M2 may be used as the second capacitor C2. The
capacitance formed between the output terminal P2 and the gate of
the second transistor M2 will be referred to as the "second
capacitor C2" hereafter, regardless of whether it is provided in
the form of a MIM capacitance or a parasitic capacitance.
[0144] With the modification shown in FIG. 11, the body diode (not
shown) of the first transistor M1 and the body diode (not shown) of
the second transistor M2 are connected in opposing directions
between the input terminal P1 and the output terminal P2. As a
result, in the OFF state of the analog switch 10b, such an
arrangement provides improved isolation between the input terminal
P1 and the output terminal P2.
[0145] FIG. 12 is a circuit diagram which shows the configuration
of an analog switch 10c according to a second modification. The
analog switch 10c shown in FIG. 12 includes a third transistor M3,
a fourth transistor M4, a fifth transistor M5, an eighth transistor
M8, and a ninth transistor M9, in addition to the configuration
shown in FIG. 11. The transistors M3, M4, M5, M8, and M9 are
provided in order to allow the analog switch 10c to be switched
between the ON state and the OFF state. It should be noted that, in
FIG. 12, the first capacitor C1 and the second capacitor C2 are not
shown.
[0146] The third transistor M3 is provided between the first fixed
voltage terminal P3 and the anode of the first diode D1. The gate
voltage thereof is controlled according to the ON/OFF operation of
the analog switch 10c. That is to say, a control signal #CNT (in
this specification, the symbol "#" indicates "logical inversion"),
which is switched to the low-level state when the analog switch 10c
is switched to the ON state, is input to the gate of the third
transistor M3.
[0147] The fourth transistor M4 is provided between the node N1
that connects the first transistor M1 and the second transistor M2
and the cathode of the first diode D1. The gate voltage of the
fourth transistor M4 is controlled according to the ON/OFF
operation of the analog switch 10c. A resistor R3 is provided
between the gate of the fourth transistor M4 and the node N1.
Furthermore, the eighth transistor M8 is provided between the power
supply terminal and the gate of the fourth transistor M4. With such
an arrangement, a control signal CNT is supplied to the gate of the
eighth transistor M8. When the control signal CNT is switched to
the high-level state, the eighth transistor M8 is switched to the
OFF state. In this state, the gate of the fourth transistor M4 is
pulled down by the resistor R3, and accordingly, the fourth
transistor M4 is switched to the OFF state. When the control signal
CNT is switched to the low-level state, the eighth transistor M8 is
switched to the ON state. In this state, the gate of the fourth
transistor M4 is switched to the high-level state, and accordingly,
the fourth transistor M4 is switched to the ON state.
[0148] The fifth transistor M5 and the ninth transistor M9 are
provided in series between the node N1 that connects the first
transistor M1 and the second transistor M2 and the ground terminal.
The gate voltages of the fifth transistor M5 and the ninth
transistor M9 are controlled according to the control signal CNT.
The gate of the fifth transistor M5 and the gate of the fourth
transistor M4 are connected to each other so as to form a common
gate. When the control signal CNT is switched to the high-level
state, and the eighth transistor M8 is accordingly switched to the
OFF state, the gate of the fifth transistor MS is pulled up by
means of the resistor R3, thereby switching the fifth transistor MS
to the OFF state. Furthermore, the control signal #CNT is input to
the gate of the ninth transistor M9.
[0149] With the analog switch 10c shown in FIG. 12, when the
control signal CNT is in the high-level state, the fourth
transistor M4, the fifth transistor MS, and the ninth transistor M9
are in the OFF state, and the third transistor M3 is in the ON
state, thereby providing a state equivalent to the state of the
analog switch 10b shown in FIG. 11. In this state, the input signal
IN input via the input terminal P1 is output via the output
terminal P2.
[0150] When the control signal CNT is switched to the low-level
state, the fifth transistor MS and the ninth transistor M9 are
switched to the ON state, and the node N1 is grounded. Furthermore,
the fourth transistor M4 is switched to the ON state, and
accordingly, the gates of the first transistor M1 and the second
transistor M2 are grounded. As a result, at least one of the first
transistor M1 and the second transistor M2 is switched to the OFF
state, thereby disconnecting the connection between the input
terminal P1 and the output terminal P2. Furthermore, the third
transistor M3 is switched to the OFF state, thereby preventing
unnecessary current flow from the first fixed voltage terminal P3
to the ground.
[0151] Such an arrangement including the fifth transistor M5, the
ninth transistor M9, the fourth transistor M4, the third transistor
M3, and the eighth transistor M8 has the above-described advantage.
Also, several transistors may be selectively employed.
[0152] FIG. 13 is a circuit diagram which shows a configuration of
an analog switch 10d according to a third modification. The analog
switch 10d shown in FIG. 13 further includes a sixth transistor M6,
a second diode D2, a third capacitor C3, and a fourth capacitor C4,
in addition to the configuration of the analog switch 10a shown in
FIG. 9.
[0153] The sixth transistor M6 is a P-channel MOSFET, and is
provided between the input terminal P1 and the output terminal P2.
The second diode D2 is provided between the gate of the sixth
transistor M6 and the second fixed voltage terminal P4 such that
the anode thereof is on the gate side of the sixth transistor M6.
In the ON state of the analog switch 10d, the ground voltage is
preferably applied to the second fixed voltage terminal P4.
[0154] The third capacitor C3 is provided between the gate of the
second transistor M2 and the input terminal P1. The fourth
capacitor C4 is provided between the gate of the second transistor
M2 and the output terminal P2. The third capacitor C3 and the
fourth capacitor C4 may be provided in the form of a MIM
capacitance or a parasitic capacitance of the sixth transistor M6
(gate-source capacitance or gate-drain capacitance).
[0155] With the circuit shown in FIG. 13, the gate of the sixth
transistor M6 is grounded via the second diode D2, thereby
providing a high-impedance state. The first terminal P1 and the
gate of the sixth transistor M6 are coupled by means of the third
capacitor C3. Accordingly, the gate voltage of the sixth transistor
M6 swings in phase with the input signal IN. As a result, the
gate-source voltage of the sixth transistor M6 is maintained at a
constant voltage. This suppresses fluctuation in the ON-resistance
of the sixth transistor M6, thereby reducing distortion in the
signal.
[0156] With the analog switch 10d shown in FIG. 13, the synthetic
impedance formed between the input terminal P1 and the output
terminal P2 is smaller than that shown in FIG. 9, thereby reducing
signal decay.
[0157] FIG. 14A and FIG. 14B are circuit diagrams which show the
configurations of analog switches 10e and 10f according to a fourth
modification. FIG. 14A shows a modification of the circuit shown in
FIG. 13, in which the fifth transistor M5, the first diode D1, the
first capacitor C1, and the second capacitor C2 are omitted.
[0158] The analog switch 10f shown in FIG. 14B includes a seventh
transistor M7, in addition to the configuration shown in FIG. 14A.
The seventh transistor M7 is a P-channel MOSFET, and is connected
in series with the sixth transistor M6 between the input terminal
P1 and the output terminal P2. The gate of the seventh transistor
M7 and the gate of the sixth transistor M6 are connected to each
other so as to form a common gate. That is to say, it can be
understood that the analog switches 10e and 10f shown in FIG. 14A
and FIG. 14B have the same circuit configurations as those of the
analog switches 10a and 10b shown in FIG. 9 and FIG. 11,
respectively, except that the N-channel MOSFETs are replaced by the
P-channel MOSFETs, and the diodes are provided in opposing
directions. Accordingly, the modification described with reference
to FIG. 12 can also be applied to the circuits shown in FIGS. 14A
and 14B.
[0159] FIG. 15 is a circuit diagram which shows a configuration of
an analog switch 10g according to a fifth modification. The analog
switch 10g shown in FIG. 15 further includes a first resistor
provided in series with the first diode D1 between the gate of the
first transistor M1 and the first fixed voltage terminal P3. By
providing the resistor R1, such an arrangement allows the impedance
between the gate of the first transistor M1 and the first fixed
voltage terminal P3 to be adjusted. The positions of the resistor
R1 and the first diode D1 may be exchanged. Also, a resistor may be
provided in series with the second diode D2 shown in FIG. 13 and
FIGS. 14A and 14B.
[0160] Viewed from a different perspective, the above-described
analog switches can be understood as follows. That is to say, an
analog switch according to an embodiment includes: an input
terminal P1 via which an analog signal IN is input; an output
terminal P2 via which an analog signal OUT is output; a MOSFET
which is provided between the input terminal P1 and the output
terminal P2; and an impedance element which is provided between the
gate of the MOSFET and the fixed voltage terminal, and which
charges the gate of the MOSFET. The term "impedance element"
represents a circuit device element having impedance which allows
the gate voltage of the MOSFET to change without being fixed to the
voltage at the fixed voltage terminal. With the embodiment, the
impedance element is provided in the form of a diode or a
combination of a diode and a resistor.
[0161] FIGS. 16A and 16B are block diagrams which show the
configurations of selector circuits employing any one of the
above-described analog switches 10 through 10g (which will be
simply referred to as the "analog switch 10"). FIG. 16A shows a
multiplexer 20, and FIG. 16B shows a demultiplexer 30. The
multiplexer shown in FIG. 16A includes multiple analog switches 10.
Each analog switch may be any one of the above-described circuits.
The output terminals of the multiple analog switches 10 are
connected to each other so as to form a common output terminal. The
input terminals receive respective signals that differ from one
another. The demultiplexer 30 shown in FIG. 16B includes multiple
analog switches 10. Each analog switch may be any one of the
above-described circuits. The input terminals of the multiple
analog switches 10 are connected to each other so as to form a
common input terminal. The output terminals are connected to
respective circuit blocks that differ from one another. Each of the
multiplexer 20 and the demultiplexer 30 has the advantage of
reducing distortion in the transmitted signal.
[0162] Description has been made in the embodiment regarding an
arrangement in which an analog signal is transmitted via the analog
switch 10. Also, a digital signal may be transmitted via the analog
switch 10. Also, a differential signal may be transmitted using two
paired analog switches.
[0163] While the preferred embodiments of the present invention
have been described using specific terms, such description is for
illustrative purposes only, and it is to be understood that changes
and variations may be made without departing from the spirit or
scope of the appended claims.
* * * * *