U.S. patent application number 12/343220 was filed with the patent office on 2009-04-23 for apparatus, module, and method for implementing communications functions.
This patent application is currently assigned to QST Holdings, LLC. Invention is credited to Kuor-Hsin Chang, Ghobad Heidari, Eugene B. Hogenauer, Paul L. Master, Walter James Scheuermann.
Application Number | 20090104930 12/343220 |
Document ID | / |
Family ID | 27732231 |
Filed Date | 2009-04-23 |
United States Patent
Application |
20090104930 |
Kind Code |
A1 |
Heidari; Ghobad ; et
al. |
April 23, 2009 |
Apparatus, module, and method for implementing communications
functions
Abstract
A system acquisition module and corresponding method for
facilitating PN code searching which has a PN sequence generator
configurable to generate a plurality of PN sequences. The module
and method also includes computational units configurable to
correlate each received signal sample of a plurality of received
signal samples with a corresponding PN sequence of the plurality of
PN sequences, and further configurable to provide other hardware
resources. A number of computational units from the plurality of
computational units are selectively configured to correlate the
received signal samples with the PN sequences--the number depending
upon availability of the plurality of computational units from
providing the other hardware resources. In another embodiment, a
communication device having a system acquisition function is
provided which includes the system acquisition module and a
receiver configured to receive signals, where a plurality of
configurable computational units are selectively configurable to
implement the PN sequence generator.
Inventors: |
Heidari; Ghobad; (San Diego,
CA) ; Chang; Kuor-Hsin; (Sunnyvale, CA) ;
Master; Paul L.; (Sunnyvale, CA) ; Hogenauer; Eugene
B.; (San Carlos, CA) ; Scheuermann; Walter James;
(Saratoga, CA) |
Correspondence
Address: |
NIXON PEABODY LLP
401 9TH STREET, N.W.
WASHINGTON
DC
20004
US
|
Assignee: |
QST Holdings, LLC
Palo Alto
CA
|
Family ID: |
27732231 |
Appl. No.: |
12/343220 |
Filed: |
December 23, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12141822 |
Jun 18, 2008 |
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12343220 |
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10067496 |
Feb 4, 2002 |
7400668 |
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12141822 |
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09815122 |
Mar 22, 2001 |
6836839 |
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10067496 |
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Current U.S.
Class: |
455/552.1 |
Current CPC
Class: |
H04B 2201/70711
20130101; G06F 15/7867 20130101; H04B 1/708 20130101 |
Class at
Publication: |
455/552.1 |
International
Class: |
H04M 1/00 20060101
H04M001/00 |
Claims
1. A communications device comprising: a plurality of
reconfigurable hardware resources configurable to provide a first
communications function, the plurality of reconfigurable hardware
resources further configurable or reconfigurable to provide at
least a second communications function; and control logic adapted
to selectively configure a first number of reconfigurable hardware
resources from the plurality of reconfigurable hardware resources
to provide the first communications function at one point in time,
the control logic further adapted to selectively configure a second
number of reconfigurable hardware resources from the plurality of
reconfigurable hardware resources to provide at least the second
communications function at another point in time by reconfiguring
at least some of the first number of reconfigurable hardware
resources.
2. The communications device of claim 1, wherein the communications
device comprises a mobile phone for use in a Code Division Multiple
Access (CDMA) communication system.
3. The communications device of claim 1, wherein the communications
device is a base station.
4. The communications device of claim 1, wherein at least some of
the reconfigurable hardware resources comprise a plurality of
configurable and reconfigurable digital signal processing (DSP)
computational units, the control logic further adapted to
selectively configure and reconfigure a third number of digital
signal processing computational units depending on for which
communications standard the digital signal processing computational
units are to be selectively configured or reconfigured.
5. The communications device of claim 1, wherein the first
communications function is one of a Code Division Multiple Access
(CDMA), a Wideband Code Division Multiple Access (W-CDMA), or a
Global System for Mobile Communications (GSM) communications
function, and the second communications function is one of a Code
Division Multiple Access (CDMA), a Wideband Code Division Multiple
Access (W-CDMA), or a Global System for Mobile Communications (GSM)
communications function.
6. The communications device of claim 1, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on
availability of the plurality of reconfigurable hardware resources
from providing other functions.
7. The communications device of claim 1, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
available clock rate driving the plurality of reconfigurable
hardware resources.
8. The communications device of claim 1, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
incoming signal rate of signals for the first and second
communications functions.
9. The communications device of claim 1, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
incoming signal period of signals operated on by the first and
second communications functions.
10. The communications device of claim 1, wherein the plurality of
reconfigurable hardware resources are further configurable or
reconfigurable to provide at least one other function.
11. The communications device of claim 10, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on how many
of the plurality of reconfigurable hardware resources are needed to
provide the at least one other function.
12. The communications device of claim 10, wherein the at least one
other function is a non-communications function.
13. The communications device of claim 7, wherein the number of
reconfigurable hardware resources selectively configured by the
control logic to provide the first communications function at one
point in time is capable of being reduced when the available clock
rate driving the plurality of reconfigurable hardware resources is
increased.
14. The communications device of claim 1, wherein the plurality of
reconfigurable hardware resources comprise a plurality of
reconfigurable computational units.
15. The communications device of claim 14, wherein the plurality of
configurable computational units comprise a plurality of
configurable heterogeneous computational units.
16. The communications device of claim 1, wherein the first
communications function comprises at least a portion of a system
acquisition function.
17. The communications device of claim 16, further comprising
dedicated hardware to provide another portion of the system
acquisition function.
18. The communications device of claim 1, wherein the first
communications function comprises at least a portion of a system
acquisition function, wherein the system acquisition function
includes: a receiver function portion to receive a plurality of
signals; a PN sequence generator function portion to generate a
plurality of PN sequences; and a correlator function portion to
correlate the plurality of signals with the plurality of PN
sequences.
19. The communications device of claim 18, further comprising: a PN
sequence generator to provide the PN sequence generator function
portion of the system acquisition function; and dedicated hardware
to provide the PN sequence generator.
20. The communications device of claim 18, further comprising:
dedicated hardware to provide another portion of the system
acquisition function; and wherein the other portion comprises one
of the receiver function portion, the PN sequence generator
function portion, or the correlator function portion.
21. The communications device of claim 20, wherein the other
portion of the system acquisition function is the receiver function
portion.
22. The communications device of claim 18, wherein the control
logic selectively configures the first number of reconfigurable
hardware resources to provide the at least a portion of the system
acquisition function; and wherein the at least a portion of the
system acquisition function comprises at least one of the receiver
function portion, the PN sequence generator function portion, or
the correlator function portion.
23. The communications device of claim 18, wherein the at least a
portion of the system acquisition function comprises the receiver
function portion, the PN sequence generator function portion, and
the correlator function portion; and wherein the control logic
selectively configures the first number of reconfigurable hardware
resources to provide the receiver function portion, the PN sequence
generator function portion, and the correlator function
portion.
24. The communications device of claim 23, wherein the control
logic selectively configures or reconfigures one or more of the
first number of configurable hardware resources to provide at least
one other function when not needed to provide the receiver function
portion, the PN sequence generator function portion, and the
correlator function portion.
25. The communications device of claim 1, further comprising a
receiver and a correlator.
26. A communications module in a communications device, the
communications module comprising: a plurality of reconfigurable
hardware resources configurable to provide a first communications
function, the plurality of reconfigurable hardware resources
further configurable or reconfigurable to provide at least a second
communications function; and control logic adapted to selectively
configure a first number of reconfigurable hardware resources from
the plurality of reconfigurable hardware resources to provide the
first communications function at one point in time, the control
logic further adapted to selectively configure a second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources to provide at least the second
communications function at another point in time by reconfiguring
at least some of the first number of reconfigurable hardware
resources.
27. The communications module of claim 26, wherein the
communications device is a mobile phone for use in a Code Division
Multiple Access (CDMA) communication system.
28. The communications module of claim 26, wherein the
communications device is a base station.
29. The communications module of claim 26, wherein at least some of
the reconfigurable hardware resources comprise a plurality of
configurable and reconfigurable digital signal processing (DSP)
computational units, the control logic further adapted to
selectively configure and reconfigure a third number of digital
signal processing computational units depending on for which
communications standard the digital signal processing computational
units are to be selectively configured or reconfigured.
30. The communications module of claim 26, wherein the first
communications function is one of a Code Division Multiple Access
(CDMA), a Wideband Code Division Multiple Access (W-CDMA), or a
Global System for Mobile Communications (GSM) communications
function, and the second communications function is one of a Code
Division Multiple Access (CDMA), a Wideband Code Division Multiple
Access (W-CDMA), or a Global System for Mobile Communications (GSM)
communications function.
31. The communication module of claim 26, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on
availability of the plurality of reconfigurable hardware resources
from providing other functions.
32. The communication module of claim 26, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
available clock rate driving the plurality of reconfigurable
hardware resources.
33. The communication module of claim 26, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
incoming signal rate of signals for the first and second
communications functions.
34. The communication module of claim 26, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on the
incoming signal period of signals operated on by the first and
second communications functions.
35. The communication module of claim 26, wherein the plurality of
reconfigurable hardware resources are further configurable or
reconfigurable to provide at least one other function.
36. The communication module of claim 35, wherein the first and
second number of reconfigurable hardware resources from the
plurality of reconfigurable hardware resources depend on how many
of the plurality of reconfigurable hardware resources are needed to
provide the at least one other function.
37. The communication module of claim 35, wherein the at least one
other function is a non-communications function.
38. The communication module of claim 32, wherein the number of
reconfigurable hardware resources selectively configured by the
control logic to provide the first communications function at one
point in time is capable of being reduced when the available clock
rate driving the plurality of reconfigurable hardware resources is
increased.
39. The communication module of claim 26, wherein the plurality of
reconfigurable hardware resources comprise a plurality of
reconfigurable computational units.
40. The communication module of claim 39, wherein the plurality of
configurable computational units comprise a plurality of
configurable heterogeneous computational units.
41. The communication module of claim 26, wherein the first
communications function comprises at least a portion of a system
acquisition function.
42. The communication module of claim 41, further comprising
dedicated hardware to provide another portion of the system
acquisition function.
43. The communication module of claim 26, wherein the first
communications function comprises at least a portion of a system
acquisition function, wherein the system acquisition function
includes: a receiver function portion to receive a plurality of
signals; a PN sequence generator function portion to generate a
plurality of PN sequences; and a correlator function portion to
correlate the plurality of signals with the plurality of PN
sequences.
44. The communications module of claim 43, further comprising: a PN
sequence generator to provide the PN sequence generator function
portion of the system acquisition function; and dedicated hardware
to provide the PN sequence generator.
45. The communication module of claim 43, further comprising:
dedicated hardware to provide another portion of the system
acquisition function; and wherein the other portion comprises one
of the receiver function portion, the PN sequence generator
function portion, or the correlator function portion.
46. The communication module of claim 45, wherein the other portion
of the system acquisition function is the receiver function
portion.
47. The communication module of claim 43, wherein the control logic
selectively configures the first number of reconfigurable hardware
resources to provide the at least a portion of the system
acquisition function; and wherein the at least a portion of the
system acquisition function comprises at least one of the receiver
function portion, the PN sequence generator function portion, or
the correlator function portion.
48. The communication module of claim 43, wherein the at least a
portion of the system acquisition function comprises the receiver
function portion, the PN sequence generator function portion, and
the correlator function portion; and wherein the control logic
selectively configures the first number of reconfigurable hardware
resources to provide the receiver function portion, the PN sequence
generator function portion, and the correlator function
portion.
49. The communication module of claim 48, wherein the control logic
selectively configures or reconfigures one or more of the first
number of configurable hardware resources to provide at least one
other function when not needed to provide the receiver function
portion, the PN sequence generator function portion, and the
correlator function portion.
50. The communication module of claim 26, further comprising a
receiver and a correlator.
51. A method for implementing communications functions in a
communications device comprising: providing a plurality of
reconfigurable hardware resources configurable to provide a first
communications function, the plurality of reconfigurable hardware
resources further configurable or reconfigurable to provide at
least a second communications function; providing control logic for
selectively configuring a first number of reconfigurable hardware
resources from the plurality of reconfigurable hardware resources
to provide the first communications function at one point in time,
the control logic further for selectively configuring a second
number of reconfigurable hardware resources from the plurality of
reconfigurable hardware resources to provide at least the second
communications function at another point in time, the selectively
configuring a second number of reconfigurable hardware resources
including reconfiguring at least some of the first number of
reconfigurable hardware resources.
52. The method of claim 51, wherein the communications device
comprises a mobile phone for use in a Code Division Multiple Access
(CDMA) communication system.
53. The method of claim 51, wherein the communications device is a
base station.
54. The method of claim 51, wherein at least some of the
reconfigurable hardware resources comprise a plurality of
configurable and reconfigurable digital signal processing (DSP)
computational units, the control logic further for selectively
configuring and reconfiguring a third number of digital signal
processing computational units depending on for which
communications standard the digital signal processing computational
units are to be selectively configured or reconfigured.
55. The method of claim 51, wherein the first communications
function is one of a Code Division Multiple Access (CDMA), a
Wideband Code Division Multiple Access (W-CDMA), or a Global System
for Mobile Communications (GSM) communications function, and the
second communications function is one of a Code Division Multiple
Access (CDMA), a Wideband Code Division Multiple Access (W-CDMA),
or a Global System for Mobile Communications (GSM) communications
function.
56. The method of claim 51, wherein the first and second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources depend on availability of the
plurality of reconfigurable hardware resources from providing other
functions.
57. The method of claim 51, wherein the first and second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources depend on the available clock
rate driving the plurality of reconfigurable hardware
resources.
58. The method of claim 51, wherein the first and second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources depend on the incoming signal
rate of signals for the first and second communications
functions.
59. The method of claim 51, wherein the first and second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources depend on the incoming signal
period of signals operated on by the first and second
communications functions.
60. The method of claim 51, wherein the plurality of reconfigurable
hardware resources are further configurable or reconfigurable to
provide at least one other function, the method further comprising
configuring or reconfiguring the plurality of reconfigurable
hardware resources to provide the at least one other function.
61. The method of claim 60, wherein the first and second number of
reconfigurable hardware resources from the plurality of
reconfigurable hardware resources depend on how many of the
plurality of reconfigurable hardware resources are needed to
provide the at least one other function.
62. The method of claim 60, wherein the at least one other function
is a non-communications function.
63. The method of claim 57, wherein the number of reconfigurable
hardware resources selectively configured by the control logic to
provide the first communications function at one point in time is
capable of being reduced when the available clock rate driving the
plurality of reconfigurable hardware resources is increased.
64. The method of claim 51, wherein the plurality of reconfigurable
hardware resources comprise a plurality of reconfigurable
computational units.
65. The method of claim 64, wherein the plurality of configurable
computational units comprise a plurality of configurable
heterogeneous computational units.
66. The method of claim 51, wherein the first communications
function comprises at least a portion of a system acquisition
function.
67. The method of claim 66, further comprising providing dedicated
hardware to provide another portion of the system acquisition
function.
68. The method of claim 51, wherein the first communications
function comprises at least a portion of a system acquisition
function, wherein the system acquisition function includes: a
receiver function portion to receive a plurality of signals; a PN
sequence generator function portion to generate a plurality of PN
sequences; and a correlator function portion to correlate the
plurality of signals with the plurality of PN sequences.
69. The method of claim 68, further comprising: providing a PN
sequence generator to provide the PN sequence generator function
portion of the system acquisition function; and providing dedicated
hardware to provide the PN sequence generator.
70. The method of claim 68, further comprising: providing dedicated
hardware to provide another portion of the system acquisition
function; and wherein the other portion comprises one of the
receiver function portion, the PN sequence generator function
portion, or the correlator function portion.
71. The method of claim 70, wherein the other portion of the system
acquisition function is the receiver function portion.
72. The method of claim 68, wherein the control logic is further
for selectively configuring the first number of reconfigurable
hardware resources to provide the at least a portion of the system
acquisition function; and wherein the at least a portion of the
system acquisition function comprises at least one of the receiver
function portion, the PN sequence generator function portion, or
the correlator function portion.
73. The method of claim 68, wherein the at least a portion of the
system acquisition function comprises the receiver function
portion, the PN sequence generator function portion, and the
correlator function portion; and wherein the control logic is
further for selectively configuring the first number of
reconfigurable hardware resources to provide the receiver function
portion, the PN sequence generator function portion, and the
correlator function portion.
74. The method of claim 73, wherein the control logic is further
for selectively configuring or reconfiguring one or more of the
first number of configurable hardware resources to provide at least
one other function when not needed to provide the receiver function
portion, the PN sequence generator function portion, and the
correlator function portion.
75. The method of claim 51, further comprising providing a receiver
and a correlator.
Description
CROSS-REFERENCES TO RELATED APPLICATION(S)
[0001] This application is a continuation of U.S. patent
application Ser. No. 12/141,822, filed Jun. 18, 2008, which is a
continuation of U.S. patent application Ser. No. 10/067,496, filed
Feb. 4, 2002, now issued as U.S. Pat. No. 7,400,668 on Jul. 15,
2008, which is a continuation-in-part application of U.S. patent
application Ser. No. 09/815,122, filed Mar. 22, 2001, now issued as
U.S. Pat. No. 6,836,839 on Dec. 28, 2004, the disclosures of each
of the aforementioned applications are hereby incorporated by
reference in their entirety as if set forth in full herein for all
purposes.
BACKGROUND OF THE INVENTION
[0002] The present invention generally relates to a system
acquisition function. More specifically, the present invention
relates to a method and system for implementing a system
acquisition function for use with a communication device.
[0003] In CDMA communication systems, each base station
differentiates amongst one another by using a unique PN code. A
communication device, such as a mobile phone, is equipped with a
system acquisition function, typically embodied in a searcher, to
search for and locate the PN codes of the base stations within the
vicinity of the mobile phone. Upon power-on, one of the initial
tasks of the mobile phone is to find the strongest pilot signal
from the nearby base stations as soon as possible. The task of
finding the strongest pilot signal is commonly known as system or
pilot acquisition and is usually performed by a searcher within the
mobile phone.
[0004] Under one conventional approach, the system acquisition
function within the mobile phone is implemented in the form of the
searcher using a serial search technique that only utilizes a set
of complex correlators to search for the correlation peak from one
PN code offset to another. This approach consumes less power and
requires less hardware; however, the search for the correlation
peak may take longer.
[0005] Under another conventional approach, the searcher within the
mobile phone is implemented using a traditional parallel search
technique that utilizes several sets of fixed, dedicated
correlators to compute the correlation peak in a concurrent manner.
This other approach may shorten the search time but it does so at
cost of incurring more hardware and power consumption. Furthermore,
since the acquisition mode is typically less active than other
modes, the exclusive use of fixed, dedicated correlators often
results in a waste of hardware resources within the mobile
phone.
[0006] More specifically, system or pilot acquisition in a CDMA
communication system is typically performed as follows. Each base
station continually broadcasts its own unique PN code in a periodic
manner. One PN code from one base station differs from another PN
code from another base station by an offset. Before a PN code can
be identified by the mobile phone, the mobile phone first searches
for signals at a particular frequency. As a result, only signals
from base stations transmitting at that particular frequency are
received by the mobile phone.
[0007] Next, the PN code of the base station which transmits the
strongest pilot signal is identified and synchronized. The mobile
phone receives signals from different base stations and these
received signals are added up. Typically, the received signals are
stored by the mobile phone before the correlation process begins.
The mobile phone has a local PN sequence generator which is capable
of generating sequences of PN codes. Initially, before the PN code
of the base station which transmits the strongest pilot signal is
identified, the PN sequence generator generates an initial PN code.
This initial PN code is correlated with the received signals by a
correlator residing in the mobile phone. Correlation is done to
determine the power level of the received signals. The correlation
results are examined to determine if the received signals
representing the PN code of the transmitting base station fall
within an acceptable time delay from the initial PN code to qualify
as the strongest pilot signal. If the correlation results are below
a predetermined threshold, i.e., the initial PN code generated by
the local PN sequence generator does not qualify as the strongest
pilot signal, then the local PN sequence generator shifts by one
chip to generate another PN code and this other PN code is
correlated with the received signals. The generation of PN codes
and the correlation of these codes with the received signals
continue until the strongest pilot signal is identified.
[0008] When the strongest pilot signal is identified, the PN code
generated by the PN sequence generator and used to identify the
strongest pilot signal is synchronized with the PN code of the base
station which transmits the strongest pilot signal. Once the
synchronization of the PN code is achieved, the mobile phone is
able to communicate with the base station.
[0009] Furthermore, after pilot acquisition is completed, the
mobile phone continues searching for nearby strong pilot signals
and maintains a list to keep track of such signals. This process is
commonly called set maintenance. That is, in addition to the
strongest pilot signal, the mobile phone also searches for and
keeps track of a number of additional pilot signals (and their
associated PN codes) with different levels of signal strength. For
example, the mobile phone may maintain an active set which keeps
track of additional multipaths associated with the pilot signal of
the base station that the mobile phone is currently communicating
with, a candidate set with pilot signals whose strengths exceed
certain threshold, and a neighbor set that includes pilot signals
from cells that are in the vicinity of the cells that the mobile
phone is communicating with. Maintaining a number of additional
pilot signals (and their associated PN codes) facilitates the
handoff process. A handoff typically occurs when a mobile phone is
roaming from one area to another. This happens when a pilot signal
transmitted from another base station is stronger than the one that
the mobile phone is currently communicating with. The candidate set
may be used to more efficiently identify the new base station
transmitting the strongest pilot signal. This is because the
strongest pilot signal is more likely to be one of the signals
included in the candidate set. Hence, the associated PN code can be
retrieved more quickly and communication with the new base station
likewise can be established in a shorter period of time.
[0010] As can be seen above, the received signals need to be stored
by the mobile phone so they can be subsequently used for
correlation purposes. Furthermore, generation of the PN codes by
the PN sequence generator is done in a sequential manner by
shifting the current PN code.
[0011] Hence, it would be desirable to provide a method and system
to implement a searcher for use with a mobile phone to more
efficiently identify the PN code of the base station which
transmits the strongest pilot signal.
SUMMARY OF THE INVENTION
[0012] A method and system for implementing a system acquisition
function for use with a communication device is provided. According
to one exemplary embodiment of the system, the system acquisition
function is embodied in a searcher. The searcher is embedded in the
communication device, such as, a mobile phone. The searcher
includes one or more computational units which are used to perform
a PN sequence generation function to generate PN sequences. Each PN
sequence is comprised of a number of PN chips. The searcher further
includes a number of computational units which are used to
correlate received signal samples with the PN chips generated by
the PN sequence generation function. As each signal sample is
received by the communication device, the received signal sample is
correlated (complex multiplied) with a PN sequence in a parallel
manner using the computational units. The sample correlation
results are then respectively accumulated within each computational
unit that conducts the corresponding sample correlation. As the
next signal sample is received, this newly received signal sample
is similarly correlated with the next PN sequence in a parallel
manner. Likewise, the sample correlation results are also
accumulated. The foregoing process is repeated until all the signal
samples needed to complete a signal correlation are received and
correlated with the PN sequences. The number of PN chips within a
PN sequence used to correlate with each received signal sample is
equivalent to a correlation length chosen such that the correlation
results between each received signal sample and the locally
generated PN sequence are sufficiently reliable to determine
whether the strongest pilot is found.
[0013] According to another aspect of the system, the computational
units are implemented using adaptive hardware resources. The number
of computational units which are used to implement the PN sequence
generation function and the correlation function are adjustable
depending on, for example, the amount of available adaptive
hardware resources.
[0014] Reference to the remaining portions of the specification,
including the drawings and claims, will realize other features and
advantages of the present invention. Further features and
advantages of the present invention, as well as the structure and
operation of various embodiments of the present invention, are
described in detail below with respect to accompanying drawings,
like reference numbers indicate identical or functionally similar
elements.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] FIG. 1 is a simplified diagram illustrating an exemplary
embodiment of an M-node having four (4) computational units in
accordance with the present invention;
[0016] FIG. 2 is a simplified diagram illustrating an exemplary
method for performing correlations in accordance with the present
invention;
[0017] FIG. 3 is a simplified diagram illustrating the exemplary
method as shown in FIG. 2 for performing an additional round of
correlations in accordance with the present invention;
[0018] FIG. 4 is a simplified diagram illustrating a second
exemplary method for performing correlations in accordance with the
present invention;
[0019] FIG. 5 is a simplified diagram illustrating a third
exemplary method for performing correlations in accordance with the
present invention;
[0020] FIG. 6 is a block diagram illustrating an exemplary system
embodiment in accordance with the present invention;
[0021] FIG. 7 is a flow diagram illustrating a first exemplary
method embodiment in accordance with the present invention; and
[0022] FIG. 8 is a flow diagram illustrating a second exemplary
method embodiment in accordance with the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0023] The present invention in the form of one or more exemplary
embodiments will now be described. FIG. 1 is a simplified diagram
illustrating an exemplary embodiment of the present invention.
Referring to FIG. 1, there is shown a searcher 10 having a number
of computational units 12a-m. The searcher 10 can be located in any
type of communication device, such as a mobile phone. As will be
further demonstrated below, each computational unit 12a-m
correlates the received signal samples with a corresponding PN
chip. In an exemplary embodiment, these computational units 12a-m
are implemented using reconfigurable hardware resources within an
adaptive computing architecture. Details relating to the adaptive
computing architecture and how reconfigurable hardware resources
are used to implement functions on an on-demand basis are disclosed
in U.S. patent application Ser. No. 09/815,122, filed on Mar. 22,
2001 (now U.S. Pat. No. 6,836,839, issued Dec. 28, 2004), entitled
"ADAPTIVE INTEGRATED CIRCUITRY WITH HETEROGENEOUS AND
RECONFIGURABLE MATRICES OF DIVERSE AND ADAPTIVE COMPUTATIONAL UNITS
HAVING FIXED, APPLICATION SPECIFIC COMPUTATIONAL ELEMENTS", the
disclosure of which is hereby incorporated by reference in their
entirety as if set forth in full herein for all purposes. That
prior application is also referred to herein as "the 09/815,122
application".
[0024] The adaptive computing architecture described in the
09/815,122 application is also referred to therein and herein as an
adaptive computing engine (ACE) architecture. Certain embodiments
of the ACE architecture described the 09/815,122 application
include configurable hardware resources in the form of
computational elements for different functions such as, but not
limited to, memory, addition, multiplication, complex
multiplication, subtraction, configuration, reconfiguration,
control, input, output, and field programmability. Certain
embodiments are further described in the 09/815,122 application
wherein, in response to configuration information, an
interconnection network is operative in real-time to configure and
reconfigure the plurality of heterogeneous computational elements
for a plurality of different functional modes, including linear
algorithmic operations, non-linear algorithmic operations, finite
state machine operations, memory operations, and bit-level
manipulations.
[0025] The ACE architecture according to certain embodiments
described in the 09/815,122 application provides a single IC, which
may be configured and reconfigured in real-time, using specific
computational elements, to perform a wide variety of tasks. For
example, utilizing differing configurations over time of the same
set of heterogeneous computational elements, the ACE architecture
may implement digital signal processing (DSP) functions such as
finite impulse response filtering, fast Fourier transformation,
discrete cosine transformation, and with other types of
computational elements, may implement many other high level
processing functions for advanced communications and computing.
Computational elements such as pluralities of multipliers, complex
multipliers, and adders, each of which are designed for optimal
execution of corresponding multiplication, complex multiplication,
and addition functions, are disclosed in the 09/815,122
application.
[0026] The temporal nature of the ACE architecture is also
described in the 09/815,122 application. In the regard, at any
given instant of time, utilizing different levels of interconnect,
a particular configuration may exist within the ACE which has been
optimized to perform a given function or implement a particular
algorithm. At another instant in time, the configuration may be
changed, to interconnect other computational elements or connect
the same computational elements differently, for the performance of
another function or algorithm. Two important features arise from
this temporal reconfigurability. First, as algorithms may change
over time to, for example, implement a new technology standard, the
ACE may co-evolve and be reconfigured to implement the new
algorithm. Second, because computational elements are
interconnected at one instant in time, as an instantiation of a
given algorithm, and then reconfigured at another instant in time
for performance of another, different algorithm, gate (or
transistor) utilization is maximized, providing significantly
better performance than the most efficient ASICs relative to their
activity factors.
[0027] This temporal reconfigurability of computational elements
for the performance of various different algorithms illustrates a
conceptual distinction utilized herein between configuration and
reconfiguration, on the one hand, and programming or
reprogrammability, on the other hand. Typical programmability
utilizes a pre-existing group or set of functions, which may be
called in various orders, over time, to implement a particular
algorithm. In contrast, configurability and reconfigurability, as
used therein and herein, includes the additional capability of
adding or creating new functions which were previously unavailable
or non-existent.
[0028] The 09/815,122 application describes certain embodiments of
the ACE architecture that may have various and different operating
modes as a cellular or other mobile telephone, a music player, a
pager, a personal digital assistant, and other new or existing
functionalities. In addition, these operating modes may change
based upon the physical location of the device, for example. As
described in the 09/815,122 application, the ACE may, for example,
be configured as a CDMA mobile telephone for use in the United
States, and the ACE may be reconfigured as a GSM mobile telephone
for use in Europe.
[0029] The ACE architecture is further contrasted with other
architectures in the 09/815,122 application, wherein an ASIC, for
example, once etched, is not readily changeable, with any
modification being time-consuming and expensive, effectively
requiring new masks and new fabrication. As a further result, ASIC
design virtually always has a degree of obsolescence, with a design
cycle lagging behind the evolving standards for product
implementations. For example, as described in the 09/815,122
application, an ASIC designed to implement GSM or CDMA standards
for mobile communication becomes relatively obsolete with the
advent of a new standard, such as 3G.
[0030] Regarding the present invention, it should be understood
that while the present invention is described as being in the
searcher 10, it will be appreciated by a person of ordinary skill
in the art that the present invention can be implemented in other
manners within a communication device. For example, some or all of
the functionality of the present invention as described herein may
be implemented outside of the searcher 10 in other parts of the
communication device.
[0031] In an exemplary embodiment, the computational units 12a-m
are arranged in a sequential order and configured to calculate the
correlations between the received signal samples and a number of PN
sequences. The start of any two adjacent PN sequences is offset by
one chip. More specifically, the computational units 12a-m
correlate each received signal sample with their corresponding
components of a PN sequence in a parallel manner.
[0032] The PN sequences used by the computational units 12a-m are
generated in a successive, offset order. The starting position of
each successive PN sequence is only one chip off from the preceding
PN sequence. The PN chips of each PN sequence can be provided to
the computational units 12a-m in a number of ways. For example, the
PN chips can be generated by either a PN sequence generator
implemented in the form of another computational unit (not shown)
or a RISC processor. As will be described further below, each PN
chip is shifted into a corresponding computational unit 12a-m. Each
computational unit 12a-m includes a local memory for storing its
corresponding PN chip.
[0033] FIG. 2 illustrates an exemplary method for performing
correlations in accordance with the present invention. Assume the
time duration of a received signal sample is T.sub.d, that is, one
signal sample is received every T.sub.d. Then, conversely, the
frequency of the received signal sample is 1/T.sub.d=f.sub.d.
[0034] Referring to FIG. 2, there are m computational units 20a-m
within the searcher 10. At time t.sub.0, signal sample R.sub.0 is
received by a receiver (not shown) located within the communication
device. Signal sample R.sub.0 is then correlated with the PN
sequence, P.sub.0P.sub.1 . . . P.sub.M-1. The PN sequence,
P.sub.0P.sub.1 . . . P.sub.M-1, is generated by a PN sequence
generator (as shown in FIG. 6) located within the communication
device. Since there are M PN chips within the PN sequence, M
computational units 20a-m are used to do the correlations in
parallel. Hence, each computational unit 20a-m correlates the
signal sample R.sub.0 with one PN chip. For example, computational
unit 20a correlates R.sub.0 with P.sub.0 to generate correlation
result R.sub.0P.sub.0. The collective correlation results generated
by the computational units 20a-m are as follows: R.sub.0P.sub.0,
R.sub.0P.sub.1, . . . , R.sub.0P.sub.M-1. The correlations are
performed and the correlation results are respectively accumulated
into the computational units 20a-m before the next signal sample
R.sub.1 is received at time t.sub.1. The signal sample R.sub.0 may
then be discarded after the correlations are performed.
[0035] At time t.sub.1, signal sample R.sub.1 is received. Signal
sample R.sub.1 is then correlated with a second PN sequence,
P.sub.1P.sub.2 . . . P.sub.M. The PN sequence, P.sub.1P.sub.2 . . .
P.sub.M, is only a shift of the PN sequence used at time to plus a
newly generated PN chip P.sub.M. That is, the start of the new PN
sequence is offset by one chip from the preceding PN sequence.
Consequently, the new PN sequence can be supplied to or propagated
through the computational units 20a-m as follows. Except for the
last computational unit 20m, each computational unit 20a-1 receives
its corresponding PN chip for the next correlation from its
neighbor. The last computational unit 20m receives its
corresponding PN chip P.sub.M from the PN sequence generator. In
other words, except for the first computational unit 20a, each
remaining computational unit 20b-m passes its current PN chip to
its neighbor in the same direction. As to the first computational
unit 20a, its current PN chip is discarded; and as to the last
computational unit 20m, as mentioned above, the PN sequence
generator provides the next PN chip. For example, after the
correlations are completed for the received signal sample R.sub.0
(which is some time before time t.sub.1), computational unit 20a
discards its current PN chip P.sub.0 and receives its next PN chip
(which will be P.sub.1) from computational unit 20b; computational
unit 20m passes its current PN chip P.sub.M-1 to its neighboring
computational unit 201 (not shown) and receives its next PN chip
P.sub.M from the PN sequence generator; and the remaining
computational units 20b-1 pass their current PN chips respectively
to their neighbors in one direction and receive their next PN chips
respectively from their neighbors in the other direction.
[0036] Again, since there are M PN chips within a PN sequence, M
computational units 20a-m are used to do the correlations in
parallel. This time around, the collective correlation results
generated by the computational units 20a-m are as follows:
R.sub.1P.sub.1, R.sub.1P.sub.2, . . . , R.sub.1P.sub.M. The
correlations are performed and the results are accumulated with the
correlation results that were done at time to before the next
signal sample R.sub.2 is received at time t.sub.2. Hence, for
example, before time t.sub.2, computational unit 20a contains
correlation results R.sub.0P.sub.0 and R.sub.1P.sub.1. The
foregoing process is repeated until the last signal sample
R.sub.n-1 is received at time t.sub.n-1 and then correlated with
the PN sequence, P.sub.n-1P.sub.n . . . P.sub.M+n-2 generating the
following collective correlation results: R.sub.n-1P.sub.n-1,
R.sub.n-1P.sub.n, . . . , R.sub.n-1P.sub.M+n-2.
[0037] At the end of the time period, t.sub.n-1+T.sub.d, the
correlation results for the received signal samples, R.sub.0R . . .
R.sub.n-1, with n different PN sequences that are offset by one
chip between the start of any two adjacent PN sequences, are then
obtained. For example, R.sub.0P.sub.0+R.sub.1P.sub.1+ . . .
+R.sub.n-1P.sub.n-1 represent the correlation results accumulated
at computational unit 20a. Also, at the end of the time period,
t.sub.n-1+T.sub.d, M different PN code offsets have been searched.
If the number of PN chips, within a PN sequence, that need to be
searched is M or fewer, then the entire search process is completed
at the end of the time period t.sub.n-1+T.sub.d.
[0038] If the number of PN chips, within a PN sequence, that need
to be searched is more than M, then a second round of search or
correlations (or additional rounds if necessary) may be performed.
The length (time-wise) of a round of correlations is the time
period t.sub.n-1+T.sub.d. For example, FIG. 3 illustrates this
second round of correlations. Before the second round of
correlations begins, the accumulated correlation results in each of
the computational unit 20a-m are transferred and stored in other
memory locations and then cleared. Referring to FIG. 3, in the
second round of correlations, the received signal sample R.sub.n is
correlated by the computational units 20a-m with the PN sequence,
P.sub.n+MP.sub.n+M+1 . . . P.sub.n+2M-1 at time t.sub.n. The
correlation results are then accumulated at each of the
computational unit 20-a-m.
[0039] At time t.sub.n+1, the signal sample R.sub.n+1 is correlated
with the next PN sequence, P.sub.n+M+1P.sub.n+M+2 . . . P.sub.n+2M.
Similarly, the start of this next PN sequence is offset from the
preceding PN sequence by one chip and a new PN chip is added at the
end. This process will continue until the second round of
correlations is completed. For the second round of real-time
correlations, another M PN offsets (P.sub.M, P.sub.M+1, . . . ,
P.sub.2M+1) are searched. The correlation results are then stored
and cleared from each computational unit 20a-m before the next
round of correlations starts.
[0040] According to the exemplary method shown in FIG. 2, all the
received signal samples R.sub.x are not stored first and then later
used for correlation purposes. Instead, as each signal sample
R.sub.x is received, the signal sample R.sub.x is correlated with M
PN chips and then accumulated. The collective correlation results
for all the received signal samples R.sub.x are then examined to
identify the PN sequence which corresponds to the strongest pilot
signal. Hence, the collective correlation results for the received
signal samples R.sub.x can be derived much faster. In addition,
since all the received signal samples R.sub.x need not be stored
before the correlation function is performed, the memory overhead
and hardware requirements and costs correspondingly become
less.
[0041] As can be seen from FIG. 2, for each time period T.sub.d, M
computational units 20a-m are used to correlate a received signal
sample R.sub.x with a PN sequence which has M PN chips. For each
time period T.sub.d, each computational unit 20a-m performs one
correlation. As a result, with M computational units 20a-m, M
correlations are collectively performed. As will be further
described below, the number of computational units 20a-m which are
used to perform the correlations is scalable. That is, the number
of computational units 20a-m may vary depending on the amount of
hardware resources available and the clock rate that is used to
drive each computational unit.
[0042] Referring back to FIG. 2, for each time period T.sub.d and a
PN sequence with M PN chips, each computational unit performs one
correlation thereby resulting in M correlations being performed.
However, each computational unit is not necessarily restricted to
performing one correlation during each time period T.sub.d.
[0043] Each computational unit may perform two or more correlations
per time period T.sub.d. While M correlations are to be performed
per time period T.sub.d, these M correlations may be collectively
performed by a fewer number of computational units. For example,
referring to FIG. 4, there are M/2 computational units. In this
case, each of the M/2 computational units is driven to perform two
(2) correlations within the time period T.sub.d; for instance,
computational unit 30a performs two (2) correlations and generates
correlation results R.sub.0P.sub.0 and R.sub.0P.sub.1. In order to
perform two (2) correlations with the time period T.sub.d, each
computational unit is driven at a higher clock rate to increase the
speed of execution.
[0044] In another example, as shown in FIG. 5, there are M/4
computational units. In this case, each of the M/4 computational
units is driven to perform four (4) correlations within the time
period T.sub.d; for instance, computational unit 40a performs four
(4) correlations and generates correlation results R.sub.0P.sub.0,
R.sub.0P.sub.1, R.sub.0P.sub.2 and R.sub.0P.sub.3. In order to
perform four (4) correlations with the time period T.sub.d, each
computational unit is driven at an even higher clock rate to
increase the speed of execution.
[0045] FIG. 6 is a block diagram illustrating an exemplary system
100 embodiment in accordance with the present invention. As
illustrated, an exemplary system 100, for implementing a system
acquisition function to facilitate PN code searching, comprises: a
PN sequence generator 110 configured to generate a plurality of PN
sequences; and a searcher 10 having a plurality of computational
units 20a-20m forming a correlator 130 and configurable to
correlate a received signal sample (from receiver 120) with a PN
sequence generated by the PN sequence generator, the correlations
being executed in a parallel manner. As discussed above, the
plurality of PN sequences are generated in a sequential manner; the
plurality of PN sequences includes a first PN sequence and a second
PN sequence, the second PN sequence immediately following the first
PN sequence; and the start of the second PN sequence is determined
by shifting the first PN sequence. In addition, a number of
computational units from the plurality of computational units are
selectively configured to correlate the received signal sample with
the PN sequence, with the number of computational units which are
selectively configured to correlate the received signal with the PN
sequence depending on availability of the plurality of
computational units.
[0046] FIG. 7 is a flow diagram illustrating a first exemplary
method embodiment for implementing a system acquisition function to
facilitate the PN code searching in accordance with the present
invention. The first exemplary method begins with generating a
first PN sequence, the first PN sequence being made up of a
plurality of PN chips, step 205, and receiving a first signal
sample, step 210. The first signal sample is correlated with the
first PN sequence upon receiving the first signal sample, step 215,
and a correlation result from the correlation between the first
signal sample and the first PN sequence is stored, step 220. A
second PN sequence is generated by shifting the first PN sequence
and adding an additional PN chip, step 225, and a second signal
sample is received, step 230. The second signal sample is
correlated with the second PN sequence, step 235, and the
methodology accumulates a correlation result from the correlation
between the second signal sample and the second PN sequence with
the correlation result from the correlation between the first
signal sample and the first PN sequence, step 240. The method then
repeats the above generating, receiving, correlating and
accumulating steps with each received signal and each newly
generated PN sequence, step 245.
[0047] FIG. 8 is a flow diagram illustrating a second exemplary
method embodiment for implementing a system acquisition function to
facilitate PN code searching in accordance with the present
invention. The second exemplary method begins with maintaining a
plurality of configurable computational units, step 305, and
receiving a plurality of signal samples, step 310. One or more of
the plurality of configurable computational units are configured to
implement a PN sequence generator to generate a plurality of PN
sequences, step 315. One or more of the plurality of configurable
computational units are configured to implement a correlator to
correlate the plurality of signal samples with the plurality of PN
sequences, step 320. Each one of the plurality of signal samples is
correlated with a corresponding one of the plurality of PN
sequences at the time when each one of the plurality of signal
samples is received, step 325. As discussed above, the number of
configurable computational units used to implement the correlator
depends on availability of the plurality of configurable
computational units. In addition, the method may also provide for
generating the plurality of PN sequences in a sequential manner,
wherein the plurality of PN sequences includes a first PN sequence
and second PN sequence, the second PN sequence immediately
following the first PN sequence, and wherein the start of the
second PN sequence is determined by shifting the first PN
sequence.
[0048] Based on the disclosure provided herein, a person of
ordinary skill in the art should be able to determine the
appropriate number of computational units to be used to implement
the PN sequence generation function and the correlation function in
accordance with the present invention. The number of computational
units which can be used depends on a number of factors, such as the
availability of the configurable hardware resources, the incoming
signal rate or, conversely, the signal period, and the available
clock rates, etc. For instance, if only a limited number of
computational units can be used, then the clock rate may need to be
driven higher in order to perform the requisite number of
correlations. Conversely, if additional hardware resources are
available, additional computational units driven at a lower clock
rate may be implemented to perform the same number of correlations.
For another instance, if the signal period is shortened, then
additional computational units may be needed to perform the
requisite number of correlations within the signal period.
[0049] The present invention as described above can also be used to
provide more efficient set maintenance. Signals from the base
station which previously transmitted the strongest pilot signal can
be searched and correlated more quickly to confirm that this base
station continues to be the one transmitting the strongest pilot
signal. Likewise, signals from the base stations which correspond
to the candidate set and the neighbor set respectively can also be
searched and correlated more quickly to update the status of the
neighbor set and the neighbor set. A candidate set may be searched
more frequently than a neighbor set. As a result, the set
maintenance update cycle is reduced.
[0050] Moreover, while the above disclosure provided above is
described in connection with a searcher 10, it should be understood
that the present invention is not restricted to use with a searcher
and that the present invention is applicable to and can be used
with any communication devices which are capable of performing a
system acquisition function.
[0051] It is understood that the present invention as described
above is applicable to a Code Division Multiple Access (CDMA)
communication system but that a person of ordinary skill in the art
should know of other ways and/or methods to apply the present
invention to other types of communication systems.
[0052] Furthermore, it is to be understood that the present
invention as described above can be implemented in the form of
control logic using software, hardware or a combination of both.
Based on the disclosure provided herein, a person of ordinary skill
in the art will know of other ways and/or methods to implement the
present invention.
[0053] It is further understood that the examples and embodiments
described herein are for illustrative purposes only and that
various modifications or changes in light thereof will be suggested
to persons skilled in the art and are to be included within the
spirit and purview of this application and scope of the appended
claims. All publications, patents, and patent applications cited
herein are hereby incorporated by reference for all purposes in
their entirety.
* * * * *