U.S. patent application number 12/324289 was filed with the patent office on 2009-04-23 for self-aligned wafer level integration system.
This patent application is currently assigned to Purdue Research Foundation. Invention is credited to Linda P.B. Katehi, Saeed Mohammadi, Hasan Sharifi.
Application Number | 20090102061 12/324289 |
Document ID | / |
Family ID | 38789149 |
Filed Date | 2009-04-23 |
United States Patent
Application |
20090102061 |
Kind Code |
A1 |
Sharifi; Hasan ; et
al. |
April 23, 2009 |
Self-Aligned Wafer Level Integration System
Abstract
A polymer-based, self-aligned wafer-level heterogeneous
integration system, SAWLIT, for integrating semiconductor
integrated circuit (IC) chips to a substrate is presented. The
system includes a method including preparing a substrate, flipping
the substrate onto a polymer-based flat surface and securing the
substrate to the flat surface, mounting semiconductor chips into
the prepared substrate, integrating the chips to the substrate with
another polymer-based material, and removing the resulting
multi-chip module from the flat surface. The chips may then be
connected with each other and regions off the multi-chip module
with metal interconnect processing technology. A multi-chip module
prepared by the polymer-based, self-aligned heterogeneous
integration system including semiconductor chips mounted in a
prepared substrate. The chips may be connected to the substrate by
a polymer-based integrating material.
Inventors: |
Sharifi; Hasan; (West
Lafayette, IN) ; Mohammadi; Saeed; (Zionsville,
IN) ; Katehi; Linda P.B.; (Zionsville, IN) |
Correspondence
Address: |
BRINKS HOFER GILSON & LIONE
P.O. BOX 10395
CHICAGO
IL
60610
US
|
Assignee: |
Purdue Research Foundation
|
Family ID: |
38789149 |
Appl. No.: |
12/324289 |
Filed: |
November 26, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11343256 |
Jan 27, 2006 |
7473579 |
|
|
12324289 |
|
|
|
|
60648873 |
Jan 31, 2005 |
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Current U.S.
Class: |
257/777 ;
257/E25.01 |
Current CPC
Class: |
H01L 2924/01013
20130101; H01L 2924/10329 20130101; H01L 2224/24137 20130101; H01L
2221/68345 20130101; H01L 21/568 20130101; H01L 24/18 20130101;
H01L 24/20 20130101; H01L 24/82 20130101; H01L 2924/01033 20130101;
H01L 2224/04105 20130101; H01L 2924/01079 20130101; H01L 24/19
20130101; H01L 2924/01019 20130101; H01L 2924/14 20130101; H01L
23/5389 20130101; H01L 2924/01047 20130101; H01L 21/6835 20130101;
H01L 2924/01029 20130101; H01L 2924/01027 20130101; H01L 2224/18
20130101; H01L 2924/15787 20130101; H01L 2924/09701 20130101; H01L
25/0655 20130101; H01L 25/50 20130101; H01L 2924/01082 20130101;
H01L 2924/30105 20130101; H01L 2924/15787 20130101; H01L 2924/00
20130101 |
Class at
Publication: |
257/777 ;
257/E25.01 |
International
Class: |
H01L 25/065 20060101
H01L025/065 |
Claims
1-14. (canceled)
15. A semiconductor multi-chip module comprising a plurality of
semiconductor chips, a substrate into which the plurality of
semiconductor chips are mounted, and a polymer-based integrating
material connecting the plurality of semiconductor chips to the
substrate.
16. A semiconductor multi-chip module as in claim 15 further
comprising a plurality of metal interconnect lines connecting the
plurality of semiconductor chips with each other.
17. A semiconductor multi-chip module as in claim 15 further
comprising a plurality of metal interconnect lines connecting the
plurality of semiconductor chips to regions off the multi-chip
module.
18. A semiconductor multi-chip module as in claim 16, where the
plurality of metal interconnect lines are composed of at least one
of a metal or a metal alloy selected from the group comprising: Au,
Cu, and Al.
19. A semiconductor multi-chip module as in claim 15 where the
substrate is composed of any of the following: Si, Quartz, GaAs, a
ceramic substrate, or LCP.
20. The semiconductor multi-chip module as in claim 15 where the
polymer-based integrating material is a polydimethylsiloxane
(PDMS), ultraviolet (UV) cure epoxy resin or adhesive, an
electronic grade encapsulant, a die attach adhesive, an epoxy,
deposited amorphous Si, or deposited or electroplated Au, Cu, or Al
or combination thereof.
21. (canceled)
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is based on and claims all available
benefit to our U.S. Provisional Application 60/648,873 filed Jan.
31, 2005.
FIELD OF THE INVENTION
[0002] This application relates to semiconductor chip-to-package
integration technologies, and particularly to a polymer-based
heterogeneous integration technology that allows high density
interconnects between chips and the package.
BACKGROUND OF THE INVENTION
[0003] Advanced Electronic Packaging is a multidisciplinary
technology defined as the combination of engineering and
manufacturing technologies required to convert an electronic
circuit into a manufactured assembly. One of the most critical
levels of electronic packaging is that of packaging and
interconnecting integrated circuit (IC's) and semiconductor
devices. There are four major chip-to-package interconnection
techniques available today: Wire Bond, Beam Lead, Tape Automated
Bonding (TAB), and Flip Chip.
[0004] Using available technologies, there is typically a minimum
pitch size of approximately 100 .mu.m.times.100 .mu.m for reliable
connection between a metallization pad on the chip and the pad on
the package. This pitch size places limitations on the density of
interconnections coming out of the chip and introduces additional
parasitic capacitance, due to the required large contact area.
Driver circuits are often needed to support I/O pads for speedy
operation. Therefore, there exists a need for a
high-density-interconnect multi-chip module integration
technology.
BRIEF SUMMARY OF THE INVENTION
[0005] The application is based on System in a Package (SIP)
technology. The approach of SIP is to remove bulky passive elements
from expensive active chips, which often use very low feature sizes
(tens to hundreds of nm), and to fabricate the passive elements on
a less expensive carrier substrate, thereby reducing the cost of
the integrated system. At the same time, integrated chips may be
fabricated using different technologies into one integrated
substrate (heterogeneous integration).
[0006] With the technology of this application, the minimum width
of the interconnects may be less than 20 .mu.m.times.20 .mu.m,
which results in fewer parasitic elements and possibly avoids the
need for I/O drivers altogether.
[0007] The application presents a method for packaging integrated
circuit (IC) chips using a heterogeneous, polymer-based integration
technology including the following steps. First, using deep
reactive ion etching, laser ablation or punching, patterned and
recessed positions are created in a substrate. The substrate is
therefore prepared for integration with IC chips. The substrate can
be a Si or quartz wafer, a flexible polymer wafer (such as Liquid
Crystal Polymer), or a ceramic substrate (such as a low temperature
co-fired ceramic (LTCC) substrate). Next, the prepared substrate is
flipped onto a flat and sticky surface (which is composed of a
polymer-based material), and the substrate is secured to the flat
surface using a bonding agent such as a soap film. After the
substrate is secured to the flat surface, the IC chips are inserted
into the patterned and recessed positions of the substrate, in the
proper positions designated for the IC chips, thereby creating
trenches between the lateral walls of the IC chips and the walls of
the recessed positions in the substrate. The IC chips are placed in
a self-aligned fashion as their exact location is pre-determined by
the recessed positions in the substrate.
[0008] Next, the trenches between the IC chips and the walls of the
recessed positions in the substrate are filled with another
polymer-based material, such as a polydimethylsiloxane (PDMS),
ultraviolet (UV) cure epoxy resin or adhesive, an electronic grade
encapsulant, a die attach adhesive, an epoxy, deposited amorphous
Si, or deposited or electroplated Au, Cu, or Al or combination
thereof. This integrates the IC chips with the prepared substrate.
The deposited polymer-based material may be allowed to polymerize
for a period of time. When the polymer has polymerized, the
integrated IC chip and substrate network is now a multi-chip module
(MCM).
[0009] The MCM is then removed from the flat surface. A thin layer
of a high-dielectric material, such as a negative, epoxy-type,
near-UV photoresist, polyimide, low-k benzocyclobutene (BCB),
low-temperature deposited silicon dixide (SiO2), silicon nitride
(Si3N4), or aluminum oxide (Al2O3), or LCP may be deposited on the
surface of the multi-chip module to improve the surface flatness.
The MCM may then be prepared for an interconnect process in which
metal lines are patterned and deposited on the surface of the
multi-chip module, creating connections between the IC chips in the
multi-chip module and to regions off of the multi-chip module.
[0010] The application also presents an MCM including a substrate,
IC chips, and a polymer-based integrating material. The IC chips
are integrated into the substrate to form a multi-chip module by
the integrating material, such as a polydimethylsiloxane (PDMS),
ultraviolet (UV) cure epoxy resin or adhesive, an electronic grade
encapsulant, a die attach adhesive, an epoxy, deposited amorphous
Si, or deposited or electroplated Au, Cu, or Al or combination
thereof deposited into the trenches between the substrate walls and
the lateral walls of the IC chips placed into the substrate. The
IC's MCM may then be connected with a standard metal interconnect
pattern and deposition process.
[0011] Other systems, methods, features and advantages of the
invention will be, or will become, apparent to one with skill in
the art upon examination of the following figures and detailed
description. It is intended that all such additional systems,
methods, features and advantages be included within this
description, be within the scope of the invention, and be protected
by the following claims.
BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS
[0012] The invention can be better understood with reference to the
following drawings and description. The components in the figures
are not necessarily to scale, emphasis instead being placed upon
illustrating the principles of the invention. Moreover, in the
figures, like referenced numerals designate corresponding parts
throughout the different views.
[0013] FIG. 1 is an example flow diagram of a self-aligned
wafer-level integration technology (SAWLIT).
[0014] FIG. 2 is an example diagram of a prepared substrate flipped
onto a flat surface and secured to a flat surface.
[0015] FIG. 3 is an example diagram of a substrate and mounted
semiconductor chips on a flat surface.
[0016] FIG. 4 is a second example diagram of a substrate and
semiconductor chips on a flat surface.
[0017] FIG. 5 is an example diagram of a processed multi-chip
module.
[0018] FIG. 6 is a top-down view of the multi-chip module.
[0019] FIG. 7 is a perspective view of the multi-chip module.
DETAILED DESCRIPTION OF THE INVENTION
[0020] The application presents a method for a polymer-based
multi-chip integration process 100 as presented in FIG. 1. By using
deep reactive ion etching (DRIE), laser ablation or punching, at
block 110, the substrate 220 (see FIG. 2) may be removed to make
desired recessed, patterned positions for semiconductor integrated
circuit (IC) chips 340 (see FIG. 3) that are to be integrated with
the substrate 220. The substrate 220 may be, but is not limited to,
silicon (Si), gallium arsenide (GaAs), liquid crystal polymer
(LCP), quartz or LTCC. The size of patterns created may be a little
larger than the width of the IC chips. The typical difference in
size between the width of the pattern and the IC chip is 10
.mu.m.
[0021] Next, as shown in FIG. 3, the substrate 320 is flipped, at
block 120, (placed upside down) onto a flat surface 310, which may
be composed of a polydimethylsiloxane (PDMS), ultraviolet (UV) cure
epoxy resin or adhesive, an electronic grade encapsulant, a die
attach adhesive, an epoxy, deposited amorphous Si, or deposited or
electroplated Au, Cu, or Al or combination thereof. The substrate
320 is secured to the flat surface 310 by a bonding agent 330, such
as a layer of soap film, between the substrate 320 and the flat
surface 310. The soap film may be a solution of 90% DI water and
10% standard dish soap, although other dissoluble bonding agents
may be used. After the substrate 320 has been flipped 120 and
secured to the flat surface 310, the IC chips 340 to be integrated
may be picked and placed upside down inside their proper places, at
block 130, in the patterned regions of the substrate 320, creating
trench-like regions between the lateral sides of the semiconductor
chips 340 and the lateral walls of the patterned recesses of the
substrate 320. The trenches between the substrate 420 and chips 440
can be filled, at block 140, by a polymer-based material 450, such
as a polydimethylsiloxane (PDMS), ultraviolet (UV) cure epoxy resin
or adhesive, an electronic grade encapsulant, a die attach
adhesive, an epoxy, deposited amorphous Si, or deposited or
electroplated Au, Cu, or Al or combination thereof, as depicted in
FIG. 4. PDMS is a polymer widely used in advanced packaging. PDMS
has very low conductivity, and low loss tangent for high frequency
applications.
[0022] As depicted in FIG. 5, after the polymer deposition and
polymerization, at block 150, at room temperature for a period
(typically 24 hours), the substrate 520, along with the integrated
chips 540, is peeled off from the flat surface, at block 160. The
integrated substrate 520 and IC chips 540 are now an integrated
network, known as a multi-chip module (MCM). A thin layer of high
dielectric material, such as a negative, epoxy-type, near-UV
photoresist, polyimide, low-k benzocyclobutene (BCB),
low-temperature deposited silicon dixide (SiO2), silicon nitride
(Si3N4), or aluminum oxide (Al2O3), or LCP 560 may be deposited, at
block 170, on the top surface of the multi-chip module to improve
the flatness of the top surface. Finally, as shown in FIG. 6,
interconnect metals 660 may be patterned and created, at block 180,
from and between the integrated chips 640 placed into the substrate
620. The metal interconnect lines 660 may be copper (Cu), gold
(Au), or aluminum (Al) alloys typically used in conventional
semiconductor processing.
[0023] The application also presents an MCM 700 (see FIG. 7) that
is created by the polymer-based heterogeneous integration process
100 presented above. The MCM 700 includes a plurality of
semiconductor IC chips 740, mounted into the patterned positions of
the substrate 720. The semiconductor chips 740 may be connected to
the substrate by a polymer-based integrating material 750, such as
a polydimethylsiloxane (PDMS), ultraviolet (UV) cure epoxy resin or
adhesive, an electronic grade encapsulant, a die attach adhesive,
an epoxy, deposited amorphous Si, or deposited or electroplated Au,
Cu, or Al or combination thereof, which fills the trench regions
750 between the lateral sides of the IC chips 740 and the lateral
walls of the patterned recesses created in the substrate 720. The
IC chips 740 in the multi-chip module may be connected to each
other and to regions (not illustrated) off the substrate 720 by
metal interconnect lines 760.
[0024] The substrate 720 may be, but is not limited to, silicon
(Si), quartz, gallium arsenide (GaAs), liquid crystal polymer (LCP)
or other polymer substrate or LTCC. The metal interconnect lines
760 may be copper (Cu), gold (Au), or aluminum (Al) alloys
typically used in conventional semiconductor processing.
[0025] While various embodiments of the invention have been
described, it will be apparent to those of ordinary skill in the
art that many more embodiments and implementations are possible
within the scope of the invention. Accordingly, the invention is
not to be restricted except in light of the attached claims and
their equivalents.
* * * * *