U.S. patent application number 11/874186 was filed with the patent office on 2009-04-23 for method for forming a plug structure and related plug structure thereof.
Invention is credited to Chao-Ching Hsieh.
Application Number | 20090102058 11/874186 |
Document ID | / |
Family ID | 40562658 |
Filed Date | 2009-04-23 |
United States Patent
Application |
20090102058 |
Kind Code |
A1 |
Hsieh; Chao-Ching |
April 23, 2009 |
METHOD FOR FORMING A PLUG STRUCTURE AND RELATED PLUG STRUCTURE
THEREOF
Abstract
A method for forming a plug structure by utilizing a punching
through process and the related plug structure are provided. An
opening is defined in a substrate, and an unwanted oxide residue is
disposed on a bottom of the opening. A glue layer is subsequently
formed over the substrate. Portions of the glue layer are disposed
on the sidewall and bottom of the opening, and cover the oxide.
Thereafter, the portion of the first glue layer disposed at the
bottom of the opening is punched through until the substrate is
exposed so as to remove the oxide. Next, the opening is filled with
a conductive structure.
Inventors: |
Hsieh; Chao-Ching; (Tai-Nan
City, TW) |
Correspondence
Address: |
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION
P.O. BOX 506
MERRIFIELD
VA
22116
US
|
Family ID: |
40562658 |
Appl. No.: |
11/874186 |
Filed: |
October 17, 2007 |
Current U.S.
Class: |
257/774 ;
257/E21.495; 257/E23.01; 438/672 |
Current CPC
Class: |
H01L 21/76814 20130101;
H01L 21/76877 20130101; H01L 21/76844 20130101 |
Class at
Publication: |
257/774 ;
438/672; 257/E21.495; 257/E23.01 |
International
Class: |
H01L 21/4763 20060101
H01L021/4763; H01L 23/48 20060101 H01L023/48 |
Claims
1. A method for forming a plug structure, the method comprising:
providing a substrate, the substrate comprising a dielectric layer,
an opening defined in the dielectric layer forming a first glue
layer over the substrate, the first glue layer being disposed on a
sidewall and the bottom of the opening; punching through a portion
of the first glue layer disposed at the bottom of the opening until
the substrate is exposed; and filling the opening with a conductive
structure.
2. The method of claim 1, further comprising a step of forming a
second glue layer over the substrate after the first glue layer is
punched through.
3. The method of claim 2, further comprising a step of forming a
barrier layer over the substrate after the second glue layer is
formed.
4. The method of claim 1, further comprising a step of forming a
barrier layer over the substrate after the first glue layer is
punched through.
5. The method of claim 4, further comprising a step of punching
through a portion of the barrier layer disposed at the bottom of
the opening after the barrier layer is formed.
6. The method of claim 1, further comprising a step of forming a
barrier layer over the substrate before the first glue layer is
punched through.
7. The method of claim 6, wherein the step of punching through the
portion of the first glue layer also punches through a portion of
the barrier layer disposed at the bottom of the opening.
8. The method of claim 1, further comprising a step of performing a
pre-cleaning process before the first glue layer is formed.
9. The method of claim 8, wherein the pre-cleaning process
comprises an argon (Ar) or F-base pre-cleaning process.
10. The method of claim 1, wherein the step of punching through the
portion of the first glue layer is performed by using an
anisotropic etching process.
11. The method of claim 10, wherein the anisotropic etching process
comprises a radio-frequency (RF) sputtering process.
12. The method of claim 1, wherein the first glue layer comprises
titanium (Ti), tantalum (Ta), or tungsten (W).
13. The method of claim 3, wherein the barrier layer comprises
titanium nitride, tantalum nitride, or tungsten nitride.
14. The method of claim 1, wherein the substrate further comprises
a semiconductor device, and the semiconductor device comprises a
conducting region; wherein the conducting region comprises nickel
silicide (NiSi), and the conductive structure comprises
tungsten.
15. A plug structure, comprising: a substrate; a dielectric layer
disposed on the substrate; an opening defined in the dielectric
layer; a glue layer covering a sidewall of the opening; a barrier
layer covering a surface of the glue layer; and a conductive
structure filling the opening.
16. The plug structure of claim 15, wherein the barrier layer
covers a portion of the substrate at a bottom of the opening.
17. The plug structure of claim 15, wherein the conductive
structure contacts a portion of the substrate at a bottom of the
opening.
18. The plug structure of claim 15, wherein the conductive
structure comprises a seed layer covering a surface of the barrier
layer, and a conductive material filling the opening; wherein the
seed layer and the conductive material comprise copper.
19. The plug structure of claim 16, wherein the substrate comprises
a semiconductor device, and the semiconductor device comprises a
conducting region; wherein the conducting region comprises nickel
silicide, and the conductive structure comprises tungsten.
20. The plug structure of claim 15, wherein the glue layer
comprises titanium, tantalum, or tungsten, and the barrier layer
comprises titanium nitride, tantalum nitride, or tungsten nitride.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a method for forming a plug
structure, and more particularly to a method of cleaning an opening
by using a punching through process.
[0003] 2. Description of the Prior Art
[0004] Currently, semiconductor devices are widely involved in many
products and services in our daily life. These semiconductor
devices are fabricated through many processes, such as
photolithography, deposition, ion implantation, or etching, to form
a plurality of integrated circuit (IC) devices on a wafer. In
semiconductor fabrication on a wafer, an opening with a high aspect
ratio, which is defined as a ratio of the depth to the width, is
needed in some situations. The opening, such as a via hole or a
contact hole, is formed in a dielectric layer and is filled with a
metallic material, such as tungsten, to form a plug.
[0005] Please refer to FIGS. 1-3. FIGS. 1-3 are schematic
cross-sectional diagrams illustrating a method for forming a
contact plug in a wafer 10 according to the prior art. As shown in
FIG. 1, a wafer 10 is provided first. The wafer 10 includes a
substrate 12, a plurality of metal-oxide-semiconductor (MOS)
devices 14 formed on the substrate 12, a dielectric layer 16
covering the substrate 12, and a plurality of plug holes 18 formed
in the dielectric layer 16. There are usually some unwanted oxides
50, such as native oxides, formed on the surface of the MOS devices
14. These oxides 50 will interfere the electrical connection
between the MOS devices 14 and the subsequently formed contact
plug.
[0006] As shown in FIG. 2, in order to remove the oxides 50, an
argon (Ar) cleaning process is subsequently carried out before a
glue layer is formed. As the industry progresses into submicron
processing techniques, a higher aspect ratio is needed for the
contact plug, and it is therefore harder to completely remove all
the oxides 50. As a result, the argon cleaning process should be
enhanced, or the process time of the argon cleaning process should
be extended to clean the bottom oxides 50. However, when the argon
cleaning process is enhanced, or the process time of the argon
cleaning process is extended, a portion of the dielectric layer 16
positioned around the top corner of the plug hole 18 might be
over-rounded. More the argon cleaning process is performed, more
seriously the top corner of the plug hole 18 is over-rounded.
[0007] As shown in FIG. 3, a titanium layer 22 is afterward formed
over the dielectric layer 16 by a physical vapor deposition (PVD)
process, a titanium nitride layer 24 is next formed over the
titanium layer 22 by a chemical vapor deposition (CVD) process, and
a tungsten layer 26 is formed over the wafer 10 to fill the plug
hole 18. Thereafter, a chemical mechanical polishing (CMP) process
is performed to remove excessive parts of the tungsten layer 26,
excessive parts of the titanium nitride layer 24, and excessive
parts of the titanium layer 22, so as to form contact plugs 28 in
the dielectric layer 16. The titanium layer 22 or the titanium
nitride layer 24 functions as a glue layer or a barrier layer
around the contact plugs 28.
[0008] Because the top corner of the plug hole 18 is over-rounded,
a barrier bridge problem 30 is caused between contact plugs 28, as
shown in FIG. 3, especially when the critical dimension (CD)
becomes smaller. The titanium layer 22 or the titanium nitride
layer 24 electrically connects two independent contact plugs 28
with each other, and causes a short circuit in the wafer 10.
Therefore, the fabricated products fail in performance.
[0009] In order to prevent the barrier bridge problem 30 and remove
the oxides 50, a F-base cleaning process is carried out instead of
the argon cleaning process, as shown in FIG. 4. However, the F-base
selectivity with SiO.sub.2 and SiN is poor, so it is easy to cause
the CD of the contact plug 28 to be enlarged, especially at the SiN
spacer or a SiN contact etch stop layer (CESL). It is easy to widen
the contact plug 28 to reach the poly-gate of the MOS device 14,
and causes a short circuit between the contact plug 28 and the
poly-gate.
[0010] The existence of oxides reduces the device performance, and
the short circuit even causes a failure of the device. Accordingly,
it is desired to provide a cleaning method that does not deform the
opening.
SUMMARY OF THE INVENTION
[0011] It is therefore an objective of the present invention to
provide a method for cleaning an opening and the related plug
structure so that the formed product has a great performance.
[0012] It is an objective of the present invention to provide a
method for forming a plug structure. First, a substrate is
provided. The substrate has a dielectric layer, an opening defined
in the dielectric layer. Subsequently, a first glue layer is formed
over the substrate. The first glue layer is disposed at the bottom
and sidewall of the opening. Next, a portion of the first glue
layer disposed at the bottom of the opening is punched through
until the substrate is exposed. Thereafter, the opening is filled
with a conductive structure.
[0013] In accordance with another aspect of the present invention,
a plug structure is provided. The plug structure includes a
substrate, a material layer disposed on the substrate, an opening
formed in the material layer, a glue layer covering a sidewall of
the opening, a barrier layer covering a surface of the glue layer,
and a plug filling the opening.
[0014] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0015] The accompanying drawings are included to provide a further
understanding of the invention, and are incorporated in and
constitute a part of this specification. The drawings illustrate
embodiments of the invention and, together with the description,
serve to explain the principles of the invention. In the
drawings:
[0016] FIGS. 1-3 are schematic cross-sectional diagrams
illustrating a method for forming a contact plug in a wafer
according to the prior art;
[0017] FIG. 4 is a schematic cross-sectional diagram illustrating
another method for forming a contact plug in a wafer according to
the prior art;
[0018] FIGS. 5-9 are schematic cross-sectional diagrams
illustrating a method for forming a plug structure according to a
first preferred embodiment of the invention;
[0019] FIG. 10 is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to a second
preferred embodiment of the invention;
[0020] FIGS. 11-12 are schematic cross-sectional diagrams
illustrating a method for forming a plug structure according to a
third preferred embodiment of the invention;
[0021] FIG. 13 is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to a fourth
preferred embodiment of the invention;
[0022] FIGS. 14-17 are schematic cross-sectional diagrams
illustrating a method for forming a plug structure according to a
fifth preferred embodiment of the invention;
[0023] FIGS. 18-20 are schematic cross-sectional diagrams
illustrating a method for forming a plug structure according to a
sixth preferred embodiment of the invention;
[0024] FIG. 21 is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to a seventh
preferred embodiment of the invention;
[0025] FIG. 22 is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to an eighth
preferred embodiment of the invention; and
[0026] FIGS. 23 is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to a ninth
preferred embodiment of the invention.
DETAILED DESCRIPTION
[0027] The method is suitable for cleaning any kind of opening in a
semiconductor wafer, such as a via hole, a contact hole, a trench,
or a damascene opening.
[0028] Please refer to FIGS. 5-9. FIGS. 5-9 are schematic
cross-sectional diagrams illustrating a method for forming a plug
structure according to a first preferred embodiment of the
invention, where like number numerals designate similar or the same
parts, regions or elements. It is to be understood that the
drawings are not drawn to scale and are served only for
illustration purposes. It is to be understood that some details
about etch stop layers, horizontal interconnects, advanced
structures, such as dual damascene structures, lithographic and
etching processes relating to the present invention method are
known in the art and thus not explicitly shown in the drawings. As
shown in FIG. 5, a wafer 110 is provided first. The wafer 110
comprises a substrate 112, a MOS device 114 formed on the substrate
112, and a dielectric layer 116 covering the substrate 112. An
opening 118 exposing one corresponding conducting region 104 of the
MOS device 114 can be formed in the dielectric layer 116 by, for
example, photolithography and etching. The opening 118 can be a
high aspect ratio opening, and the width of the opening 118 is
relative small to the depth. For example, the opening 118 is a
contact hole in this embodiment.
[0029] There are usually some unwanted oxides 50, such as native
oxides, formed on the surface of the MOS device 114. For instance,
the oxides 50 might be formed on the conducting regions 104 of the
MOS device 114. These oxides 50 may degrade the electrical
connection between the MOS device 114 and the subsequently formed
contact plug in the opening 118. In addition, residues (not shown
in the drawing) might also formed at the bottom of the opening 118
during an etching process of forming the opening 118, where the
residues usually contains high-molecule polymers with carbon,
silicon, nitrogen, fluorine, titanium, or other impurities.
[0030] The wafer 110 can also be taken as a semiconductor
substrate, and can further include more devices or components (not
shown in the drawing) therein. The substrate 112 can be made from
semiconductor materials, such as a silicon substrate, a
silicon-containing substrate, or a silicon-on-insulator (SOI). The
conducting regions 104 of the MOS device 114 can contain salicide,
such as nickel silicide (NiSi), for reducing the contact resistance
between the MOS device 114 and the following-formed plugs. It
should be noted that the MOS device 114 could be replaced with any
component or device, such as a diode, a capacitor, a resistor, or
even a metallic structure, that should be electrically connected to
a plug or to a trench. The dielectric layer 116 is usually
sandwiched between one metal layer on the top and the substrate 112
at the bottom, or between two metal layers. The dielectric layer
116 can contain lower dielectric constant (low-k) materials, such
as a silicon -containing layer including fluorinated silicate glass
(FSG) or a carbon-containing layer including carbon-doped oxide
(CDO). In other embodiment, the dielectric layer 116 can be
replaced by other material layers.
[0031] As shown in FIG. 6, a glue layer 122 is substantially formed
over wafer 110, and a portion of the glue layer 122 can be disposed
at the bottom and sidewall of the opening 118. The glue layer 122
can be applied to protect the structure of the opening 118, and to
improve the adhesion between the dielectric layer 116 and the
subsequently formed metal plug. Accordingly, the glue layer 122 can
include metal materials, such as titanium, tantalum, or tungsten.
For example, the glue layer 122 includes a titanium layer formed by
a physical vapor deposition process in this embodiment.
[0032] As shown in FIG. 7, a punching through process is performed.
The portion of the glue layer 122 disposed at the bottoms of the
openings 118 is punched through until the MOS device 114 is exposed
so as to remove the unwanted oxide 50. The portion of the glue
layer 122 disposed at the bottoms of the openings 118 can be
punched through by using an anisotropic etching process, such as a
radio-frequency (RF) sputtering process. The RF sputtering process
includes a gas or metal, such as nitrogen gas, flushed into a
reaction chamber, and a RF power source used to ionize the gas into
ions. The wafer 110 is applied with a voltage to produce electric
field, which energizes ions by accelerating ions in order to
bombard the wafer 110. Accordingly, the unwanted oxide 50 and the
portion of the glue layer 122 disposed at the bottom of the opening
118 are removed.
[0033] An opening having overhang structure may degrade the step
coverage performance for the subsequent process for a formation of
a plug. If the opening 118 has an overhang structure on each upper
corner of the opening 118, the overhang structure can also be
remove by utilizing the above-mentioned punching through process.
The avoidance of the overhang structure of the glue layer on the
upper corners of the opening can improve the step coverage
performance.
[0034] It deserves to be mentioned that other portions of the glue
layer 122 disposed on the surface of the dielectric layer 116 might
also be removed in the above-mentioned punching through process.
For example, the top surface of the dielectric layer 116 outside
the opening 118 might be exposed in this embodiment after the
punching through process. In other embodiments, portions of the
glue layer 122 disposed on the sidewalls of the openings 118 might
be removed, or portions of the glue layer 122 disposed on the top
surface of the dielectric layer 116 might not be removed. The
removed portions and the remained portions of the glue layer 122
can be modified by adjusting parameters of the punching through
process or by a patterned hard mask.
[0035] As shown in FIG. 8, a barrier layer 124 is next formed over
the wafer 110, and a conductive material 126 is thereafter formed
to fill the opening 118. The barrier layer 124 can cover the bottom
of the opening 118 and the surface of the glue layer 122. The
barrier layer 124 can be applied to improve the ohmic contact
between the conducting regions 104 of the MOS device 114 and the
conductive material 126. Accordingly, the barrier layer 124 can
include refractory or noble metal or compound, such as titanium
nitride, tantalum nitride, tungsten nitride, or their combination.
For example, the barrier layer 124 can include a titanium nitride
layer formed by a chemical vapor deposition (CVD) process in this
embodiment. The conductive material 126 can be any material having
a high conductivity, such as tungsten, copper, aluminum, other
metals or their alloy. For instance, the conductive material 126
can include tungsten formed by a deposition process in this
embodiment.
[0036] Afterward, as shown in FIG. 9, a planarization process, such
as a chemical mechanical polishing process, is performed to remove
excessive portions of the conductive material 126, and excessive
portions of the barrier layer 124, so as to form a plurality of
plug structures 128 in the dielectric layer 116. The remained
conductive material 126 therefore becomes a conductive structure. A
plug structure is usually applied to interconnect two conductive
components for an interconnection between devices. In this
embodiment, the plug structures 128 function as contact plugs to
electrically connect the lower MOS devices 114 with the upper metal
layer or with other devices. In practice, the punching through
process can be applied to any fabrication, in which an opening
should be cleaned. For example, the present invention can be
applied to a fabrication of a via plug, a fabrication of a contact
plug, a fabrication of a damascene structure, or even a fabrication
of a shallow trench isolation.
[0037] It is worthy of note that the fabrication of the barrier
layer 124 can be eliminated in some embodiments. Please refer to
FIG. 10, which is a schematic cross-sectional diagram illustrating
a method for forming a plug structure according to a second
preferred embodiment of the invention. As shown in FIG. 10, the
fabrication of the barrier layer 124 can be eliminated if the
conductive material 126 is formed by a chemical vapor deposition
process, where tungsten hexafluoride (WF.sub.6), tungsten chloride
(WCl.sub.6) or tungsten trioxide (WO.sub.3) is utilized as the
tungsten source. In addition, if the conductive material 126 is
formed in a co-reactant system, where organometallic precursors,
such as tungsten hexacarbonyl (W(CO).sub.6), is employed, or the
conductive material 126 is formed by a metal organic chemical vapor
deposition (MOCVD) process, where Cl.sub.4(CH.sub.3CN)W(NPr) is
utilized as precursor, the fabrication of the barrier layer 124 can
be eliminated.
[0038] In other embodiments, another glue layer can be formed over
the wafer 110 after the glue layer 122 is punched through. Please
refer to FIGS. 11-12, which are schematic cross-sectional diagrams
illustrating a method for forming a plug structure according to a
third preferred embodiment of the invention, where like number
numerals designate similar or the same parts, regions or elements.
In this embodiment, a wafer 110 having a structure similar to the
wafer 110 shown in FIG. 5 can be first provided. Subsequently, a
glue layer 122 can be formed over the wafer 110, and a punching
through process can be performed to remove the portion of glue
layer 122 and the oxide 50 positioned at the bottom of the opening
118 according to the steps shown in FIG. 6 and FIG. 7.
[0039] Thereafter, as shown in FIG. 11, another glue layer 132 can
be formed over the wafer 110, a barrier layer 124 is next formed on
the glue layer 132, and a conductive material 126 is next formed to
fill the opening 118. A portion of the glue layer 132 is disposed
at the bottom of the opening 118, and covers the surface of the
glue layer 122. The glue layer 132 can include metal materials,
such as titanium, tantalum, or tungsten. For example, the glue
layer 132 can include a titanium layer formed by a physical vapor
deposition process.
[0040] Afterward, as shown in FIG. 12, a planarization process is
performed to remove excessive portions of the conductive material
126, excessive portions of the barrier layer 124, and excessive
portions of the glue layer 132, so as to form a plurality of plug
structures 228 in the dielectric layer 116. In this embodiment, the
glue layer 132 can be applied for improving the adhesion between
the MOS devices 114 and the subsequently formed metal plug.
[0041] The fabrication of the barrier layer 124 shown in FIG. 12
can also be eliminated. Please refer to FIG. 13, which is a
schematic cross-sectional diagram illustrating a method for forming
a plug structure according to a fourth preferred embodiment of the
invention. As shown in FIG. 13, the fabrication of the barrier
layer 124 can be eliminated, so the conductive material 126 covers
the surface of the glue layer 132 and contacts the MOS devices
114.
[0042] Portions of the barrier layer 124 shown in FIG. 8 can also
be punched through. Please refer to FIGS. 14-17, which are
schematic cross-sectional diagrams illustrating a method for
forming a plug structure according to a fifth preferred embodiment
of the invention, where like number numerals designate similar or
the same parts, regions or elements. As shown in FIG. 14, a wafer
110, which has undergone the steps shown in FIGS. 5-8, is provided,
and thus has a structure as same as the wafer 110 shown in FIG.
8.
[0043] Subsequently, as shown in FIG. 15, portions of the barrier
layer 124 disposed at the bottoms of the openings 118 is punched
through until the MOS device 114 is exposed, where the glue layer
122 can be punched through by using an anisotropic etching process,
such as a radio-frequency sputtering process. If the opening 118
has an overhang structure of the barrier layer 124 on each upper
corner of the opening 118, the overhang structure can also be
removed during this punching through process.
[0044] Afterward, as shown in FIG. 16, another barrier layer 134 is
formed on the barrier layer 124, and a conductive material 126 is
next formed to fill the opening 118. Next, as shown in FIG. 17, a
planarization process is performed to remove excessive portions of
the conductive material 126 and excessive portions of the barrier
layer 134 so as to form a plurality of plug structures 528 in the
dielectric layer 116.
[0045] Furthermore, portions of the barrier layer 124 can be
punched through immediately after the glue layer 122 is punched
through in other embodiments. Please refer to FIGS. 18-20, which
are schematic cross-sectional diagrams illustrating a method for
forming a plug structure according to a sixth preferred embodiment
of the invention. As shown in FIG. 18, a wafer 110, which has
undergone the steps shown in FIGS. 5-6, is provided, and a barrier
layer 124 is next formed over the wafer 110. The glue layer 122
covers the oxides 50, and the barrier layer 124 can cover the
surface of the glue layer 122.
[0046] Subsequently, as shown in FIG. 19, portions of the barrier
layer 124 and portions of the glue layer 122 disposed at the
bottoms of the openings 118 are punched through until the MOS
device 114 is exposed, where the barrier layer 124 and the glue
layer 122 are punched through by using an anisotropic etching
process. Afterward, as shown in FIG. 20, another barrier layer 134
is formed on the barrier layer 124, a conductive material 126 is
next formed to fill the opening 118, and a planarization process is
performed to remove excessive portions of the conductive material
126 and excessive portions of the barrier layer 134 so as to form a
plurality of plug structures 628 in the dielectric layer 116.
[0047] In other embodiments, the fabrication of the barrier layer
134 shown in FIG. 16 or FIG. 20 can also be eliminated. Please
refer to FIG. 21 and FIG. 22. FIG. 21 is a schematic
cross-sectional diagram illustrating a method for forming a plug
structure according to a seventh preferred embodiment of the
invention, and FIG. 22 is a schematic cross-sectional diagram
illustrating a method for forming a plug structure according to an
eighth preferred embodiment of the invention. As shown in FIG. 21,
the fabrication of the barrier layer 134 can be eliminated, so the
conductive material 126 covers the surface of the barrier layer
124, and contacts the MOS devices 114.
[0048] In the above-mentioned embodiments, tungsten process is
taken as examples to specifically illustrate the cleaning method of
the present invention. In other embodiments, the utilized
materials, the patterns of the openings, or the devices positioned
under the plugs can be change or modified. For example, the present
invention can be applied to a copper process. Please refer to FIGS.
23, which is a schematic cross-sectional diagram illustrating a
method for forming a plug structure according to a ninth preferred
embodiment of the invention, where like number numerals designate
similar or the same parts, regions or elements. The main
differences between the first preferred embodiment and the ninth
preferred embodiment are the semiconductor devices positioned under
the plugs and the materials of the glue layer, the barrier layer,
and the conductive material.
[0049] As shown in FIG. 23, the MOS devices 114 are replaced with
metallic structures 214, the glue layer 122 is replaced with a glue
layer 222, the barrier layer 124 is replaced with a barrier layer
224, and the conductive material contains copper. In this
embodiment, the glue layer 222 includes a tantalum layer, and the
barrier layer 224 can include a tantalum nitride layer in
accordance with a copper process. The glue layer 222 and the
barrier layer 224 can further prevent the diffusion of copper into
the dielectric layer 116, which would short out the dielectric
between neighboring via, or the diffusion of oxygen from the
dielectric 116 into the metallic structures 214, which reduces the
conductivity of the plug. In the case of copper process, the
filling process typically includes a physical vapor deposition or
sputtering deposition of the copper seed layer 238 followed by an
electrochemical plating (ECP) of copper into the openings 118.
Therefore, a plurality of plug structures 928 is formed, where each
opening 118 is filled with a conductive structure. Each conductive
structure includes a seed layer 238 covering a surface of the
barrier layer, and a conductive material 236 filling the opening
118.
[0050] In addition, it should be noted that a pre-cleaning process
could be further performed before the deposition of the glue layer
122 in the above-mentioned embodiments. For example, an Ar
pre-cleaning process or an F-base pre-cleaning process can be
performed to remove portions of the oxides. In order to protect the
structures of the openings, the Ar pre-cleaning process must be
soft and delicate, and should not be performed for a long time, in
which most of the oxides remain in the openings.
[0051] Since the present invention utilizes a punch through process
to remove the unwanted oxides disposed at the bottom of the
opening, there are some advantages for the present invention as
following listed. First, the method can contain no Ar cleaning
process nor F-base cleaning process that deforms the structure of
the opening. Therefore, the contact profile of the plug structure
is improved, and a short circuit between two plugs, and a short
circuit between the plug and the lower device can be avoided.
Subsequently, the unwanted oxides are easily and effectively
removed, so the contact resistance between the plug and the lower
device can be decreased. Furthermore, the step coverage for the
glue layer and the step coverage for the barrier layer are also
improved due to the punch through process. As a result, the device
performance can be increased as desired by an IC design.
[0052] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention.
* * * * *