U.S. patent application number 12/271134 was filed with the patent office on 2009-04-16 for multilayer circuit devices and manufacturing methods using electroplated sacrificial structures.
This patent application is currently assigned to MEDTRONIC MINIMED, INC.. Invention is credited to James D. Holker, John J. Mastrototaro, Rajiv Shah.
Application Number | 20090098643 12/271134 |
Document ID | / |
Family ID | 32033320 |
Filed Date | 2009-04-16 |
United States Patent
Application |
20090098643 |
Kind Code |
A1 |
Mastrototaro; John J. ; et
al. |
April 16, 2009 |
MULTILAYER CIRCUIT DEVICES AND MANUFACTURING METHODS USING
ELECTROPLATED SACRIFICIAL STRUCTURES
Abstract
A multilayer circuit includes a dielectric base substrate,
conductors formed on the base substrate and a vacuum deposited
dielectric thin film formed over the conductors and the base
substrate. The vacuum deposited dielectric thin film is patterned
using sacrificial structures formed by electroplating techniques.
Substrates formed in this manner enable significant increases in
circuit pattern miniaturization, circuit pattern reliability,
interconnect density and significant reduction of over-all
substrate thickness.
Inventors: |
Mastrototaro; John J.; (Los
Angeles, CA) ; Shah; Rajiv; (Rancho Palos Verdes,
CA) ; Holker; James D.; (Alta Loma, CA) |
Correspondence
Address: |
FOLEY & LARDNER
555 South Flower Street, SUITE 3500
LOS ANGELES
CA
90071-2411
US
|
Assignee: |
MEDTRONIC MINIMED, INC.
|
Family ID: |
32033320 |
Appl. No.: |
12/271134 |
Filed: |
November 14, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11086936 |
Mar 22, 2005 |
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12271134 |
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10331186 |
Dec 26, 2002 |
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11086936 |
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10671996 |
Sep 26, 2003 |
7138330 |
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10331186 |
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60414289 |
Sep 27, 2002 |
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Current U.S.
Class: |
435/287.1 ;
422/50; 422/68.1 |
Current CPC
Class: |
H05K 2203/0278 20130101;
H05K 3/4667 20130101; H05K 3/4061 20130101; H01L 21/4857 20130101;
H05K 3/467 20130101; H05K 3/4647 20130101; H01L 2924/0002 20130101;
H01L 2924/0002 20130101; H05K 2201/0179 20130101; H05K 1/092
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
435/287.1 ;
422/50; 422/68.1 |
International
Class: |
C12M 1/00 20060101
C12M001/00; G01N 33/00 20060101 G01N033/00; G01N 33/66 20060101
G01N033/66 |
Claims
1.-31. (canceled)
32. A device comprising: a tube having a wall defining an outer
peripheral surface of the tube; and a sensor supported by the
wall.
33. The device of claim 32, wherein the sensor is supported on the
outer peripheral surface of the tube.
34. The device of claim 33, wherein the sensor is supported on a
first radial portion of the outer peripheral surface of the
tube.
35. The device of claim 34, wherein a second radial portion of the
outer peripheral surface of the tube is configured to engage with a
slotted needle.
36. The device of claim 34, wherein the sensor comprises a
substrate having a first surface, and wherein the first surface of
the substrate is in contact with the first radial portion of the
outer peripheral surface of the tube.
37. The device of claim 36, wherein the substrate is a flexible
substrate.
38. The device of claim 36, wherein the substrate is a rigid
substrate.
39. The device of claim 36, wherein the substrate is formed of a
dielectric material.
40. The device of claim 36, wherein the substrate has a second
surface opposite the first surface of the substrate, and wherein
the sensor further comprises a sensor electrode located on the
second surface of the substrate.
41. The device of claim 32, wherein the tube is formed of a liquid
polymer.
42. The device of claim 41, wherein the liquid polymer is
biocompatible.
43. The device of claim 41, wherein the liquid polymer comprises at
least one of polyurethane, polycarbonate, silicone and acrylic.
44. The device of claim 32, wherein the sensor is for sensing blood
glucose.
45. The device of claim 32, wherein the sensor comprises a sensor
enzyme for sensing blood glucose.
Description
RELATED APPLICATIONS
[0001] This application is a continuation application of U.S.
patent application Ser. No. 11/086,936, filed on Mar. 22, 2005,
which is a continuation-in-part application of U.S. patent
application Ser. No. 10/671,996, filed 26 Sep. 2003, which claims
priority under 35 USC .sctn. 119(e) from U.S. Provisional
Application Ser. No. 60/414,289, filed 27 Sep. 2002, entitled
"Multilayer Substrate;" and is a continuation-in-part application
of U.S. patent application Ser. No. 10/331,186, filed 26 Dec. 2002,
entitled "Multilayer Substrate," the entirety of each of which is
incorporated herein by reference and forms a basis for priority.
This application also claims priority to U.S. patent application
Ser. No. 09/779,282, filed 8 Feb. 2001, entitled "Improved Analyte
Sensor and Method of Making the Same," which is incorporated herein
by reference.
[0002] In addition, this application is related to U.S. patent
application Ser. No. 10/038,276, filed 31 Dec. 2001, entitled
"Sensor Substrate and Method of Fabricating Same," the entirety of
which is incorporated herein by reference.
BACKGROUND
[0003] 1. Field of the Invention
[0004] Embodiments of the invention relate to multilayer electronic
devices and methods for fabrication of multi-layer electronic
devices in which electroplated sacrificial structures are used
during fabrication to pattern certain dielectric or other material
in one or more layers. Particular embodiments of the invention
relate to highly stable multilayer electronic devices and methods
of fabrication thereof, for use in caustic or sensitive
environments, such as medical and implant environments, in which
the material used for a patterned dielectric or other patterned
layers in the device are selected, in part, for suitable
environmental compatibility.
[0005] 2. Description of Related Art
[0006] A variety of multilayer electronic structures comprised of
multiple layers of conductors interposed between multiple layers of
dielectric material have been developed for various purposes. For
multilayer electronic structures used in caustic or sensitive
environments, the materials selected for the dielectric layer or
other layers in the multilayer electronic structure preferably not
only have suitable electrical characteristics to provide an
intended electrical function, but also have suitable
characteristics to be compatible with the environment. However,
such environmentally compatible materials can, in some contexts,
present manufacturing difficulties.
[0007] For example, materials traditionally considered compatible
(or inert) with respect to certain medical or biological
environments may have physical characteristics that render them
incapable or impractical to form in layers of suitably precise
patterns or suitably large spanses, using traditional multilayer
device manufacturing techniques. Materials, such as Al2O3 (alumina)
may have suitable dielectric characteristics and may be suitably
compatible (or inert) with respect to medical or biological
environments. However, traditionally, alumina has been difficult to
form in precise patterns.
[0008] To address such problems, example processes for patterning
alumina by using sacrificial structures formed by shadow masking
techniques are described in U.S. patent application Ser. No.
10/671,996, filed 26 Sep. 2003, which is incorporated herein by
reference. Shadow masking techniques typically employ machined,
laser-drilled masks for defining the pattern of deposition of the
patterned layer material. Because of the cost and physical
limitations of such masks and laser drilling processes, shadow
masking techniques can be impractical for forming certain pattern
shapes or precision details in patterned layers. Also, shadow
masking techniques can be impractical for forming patterns in large
spanses, such as for large devices or for forming multiple devices
simultaneously (such as a multiple-device wafer that is cut into
separate devices after formation of the wafer).
[0009] Multiple layer circuit devices and processes of making such
devices using ceramic substrate materials as described in the
above-referenced U.S. patent application Ser. No. 10/671,996 and
embodiments included herein are distinguished from silicon-based
multi-layer devices in which doped regions of silicon are connected
by layers having conductive material. In contrast to silicon based
devices, ceramic-based multiple layer circuit devices as described
in the above-referenced U.S. patent application Ser. No. 10/671,996
and embodiments included herein may be configured with thick film
layers, thin film layers or combinations of thick and thin film
layers.
[0010] Other multilayer substrates are conventionally fabricated by
lamination techniques in which metal conductors are formed on
individual dielectric layers, and the dielectric layers are then
stacked and bonded together. However, various conventional
lamination techniques have limitations that restricts their
usefulness. For example, high temperature ceramic co-fire (HTCC)
lamination techniques form conductors on "green sheets" of
dielectric material that are bonded by firing at temperatures in
excess of 1500 degrees C. in a reducing atmosphere. The high firing
temperature precludes the use of noble metal conductors such as
gold and platinum. As a result, substrates formed by high
temperature processing are limited to the use of refractory metal
conductors such as tungsten and molybdenum, which have very low
resistance to corrosion in the presence of moisture and are
therefore not appropriate for use in certain environments.
[0011] Low temperature ceramic co-fire (LTCC) techniques also
utilize green sheets of ceramic materials. However the dielectric
materials used in low-temperature processes are generally provided
with a high glass content and therefore have relatively poor
resistance to environmental corrosion, as well as a relatively low
dielectric constant and relatively poor thermal conductivity.
[0012] Thick film (TF) techniques form multilayer substrates by
firing individual dielectric layers and then laminating the layers
to form a multilayer stack. However, thick film techniques require
the use of relatively thick dielectric layers and thus it is
difficult to produce a thin film multilayer device or a device
having a combination of thick and thin film layers using
traditional thick film processing techniques. Thick film
dielectrics also have relatively low dielectric constants,
relatively poor thermal conductivity, and poor corrosion
resistance.
[0013] In addition to the problems listed above, the conventional
lamination techniques cannot use green sheets of less than 0.006
inches in thickness because thinner green sheets cannot reliably
survive necessary processing such as drilling or punching of via
holes. Also, because the designer has limited control over the
thickness of individual green sheets, the number of layers of the
multilayer substrate is often limited according to the maximum
allowable substrate thickness for the intended application. Thus,
where a thin multilayer substrate device is desired or a multilayer
substrate device having both thick and thin layers, lamination
techniques generally do not provide optimal results.
[0014] In addition, the firing required in the conventional
lamination techniques can cause shrinkage in excess of 10% in both
dielectric and conductor materials, which can produce distortions
that result in misalignment of vias and conductors after firing.
While shrinkage effects can be addressed to some extent during
design for substrates having a modest interconnect density, the
design process is made more time consuming and a significant
reduction in yield may occur in applications with higher densities
and tighter dimensional tolerances.
SUMMARY OF THE DISCLOSURE
[0015] Therefore, embodiments of the invention may be employed to
address some or all of the limitations of conventional processes
described above, to provide multiple layer electronic devices (such
as electronic circuit substrates, portions of electronic circuits
or circuit elements), where processes of forming such devices are
compatible with a large variety of layer materials and layer
thicknesses. Improved processing techniques that employ
electroplated sacrificial structures to pattern one or more layers
of a multiple layer device, as described herein, may be employed
with a many different materials and layer thicknesses. As a result,
aspects of the invention can provide a greater number of design
options for layer materials, layer thicknesses and layer patterns
designed to meet desired electrical, structure and environmental
comparability properties.
[0016] In accordance with embodiments of the invention, a
multilayer circuit substrate is comprised of a base substrate and
one or more additional dielectric and conductive thin films formed
over the base substrate. One or more of the dielectric film layers
is formed in a pattern having openings that allow interconnections
between conductive layers or between a conductive layer and the
base substrate located on opposite sides of the dielectric film
layer.
[0017] Deposited dielectrics are patterned through the use of
sacrificial structures that may be removed using highly selective
etch chemistry. The sacrificial structures are formed using
electroplating techniques. Electroplating techniques may be used to
provide precise patterns and sacrificial structure configurations
that could not be formed (or would be impractical to form) using
shadow mask deposition techniques. In addition, electroplating
techniques can allow dielectric patterns to be precisely registered
to underlying structures and thus enabling high interconnect
densities and narrow dimensional tolerances not achievable by
conventional lamination techniques.
[0018] In accordance with further embodiments of the invention,
patterning techniques such as electroplating, shadow masking,
chemical etch and photoresist lift-off may be used for patterning
conductive materials in the multilayer device. Conductors may
therefore be precisely aligned with underlying structures and
formed with linewidths not achievable by conventional lamination
techniques.
[0019] In accordance with further embodiments of the invention,
hermetic vias may be formed in the dielectric base substrate, for
example, by forming successive thin layers of a conductive material
on the sidewalls of a via hole using a dilute conductive ink,
followed by formation of a conductive plug using a concentrated
conductive ink and sintering of the conductive material, as
described in U.S. patent application Ser. No. 10/671,996, filed 26
Sep. 2003, which is incorporated herein by reference.
[0020] Example embodiments of the invention employ vacuum
deposition methods for depositing dielectric materials. Vacuum
deposited dielectric layers may be formed significantly thinner
than the dielectric layers used in conventional lamination
techniques, allowing for the formation of multilayer circuit
devices that have overall thicknesses significantly thinner than
those formed by conventional lamination techniques. Because vacuum
deposited dielectrics are deposited in an "as-fired" state that
undergoes essentially no shrinkage during subsequent processing,
yield reduction due to misalignment may be significantly reduced or
eliminated. In addition, vacuum deposition techniques do not impose
limitations on the types of conductors or dielectric materials that
may be employed, enabling the use of a wide variety of materials
with highly tunable properties. Vacuum deposition techniques also
produce hermetic layers that facilitate the production of highly
reliable substrates.
[0021] In accordance with example embodiments of the invention, a
multilayer circuit device is characterized by a dielectric base
substrate having conductors formed thereon, and at least one layer
of a patterned vacuum deposited thin film dielectric overlying the
conductors. One or more of the deposited thin film dielectrics have
a pattern formed by using electroplated sacrificial structures. In
various implementations, multiple layers of conductors and
deposited dielectrics may be used, multiple layers may be formed on
one or both sides of the base substrate, and the base substrate may
include hermetic vias.
[0022] Also in accordance with example embodiments of the
invention, a multilayer circuit device is produced according to a
process in which a dielectric base substrate is provided.
Conductors are then formed on the base substrate, preferably by
patterning of a blanket layer of conductive thin film deposited by
a vacuum deposition method. Sacrificial structures are then formed
by electroplating sacrificial material on the base substrate and
conductors. The sacrificial structures define areas of the base
substrate and conductors that are to be protected during subsequent
dielectric deposition. A thin film dielectric layer is vacuum
deposited on the base substrate, the conductors and the sacrificial
structures, and the sacrificial structures are removed to leave a
patterned deposited thin film dielectric layer on the conductors
and the base substrate. Further processing such as forming
additional conductor layers and dielectric layers or mounting of an
electronic component to the substrate may be performed.
DESCRIPTION OF THE DRAWINGS
[0023] FIGS. 1a, 1b, 1c, 1d, 1e and if show structures formed
during fabrication of a general multilayer circuit device in
accordance with an embodiment of the invention;
[0024] FIGS. 2a, 2b, 2c, 2d, 2e, 2f, 2g, 2h, 2i, 2j and 2k show
structures formed during fabrication of a medical sensor device
having a multilayer circuit in accordance with an embodiment of the
invention;
[0025] FIG. 3 shows a process flow according to an embodiment of
the invention; and
[0026] FIG. 4 shows an example of a medical sensor device made in
accordance with the structures of FIGS. 2a-2k.
[0027] FIG. 5 shows an example of a medical sensor device made in
accordance with the structures of FIGS. 2a-2k and having a
bead.
[0028] FIG. 6 is a transverse section illustrating the engagement
of the device of FIG. 5 and a slotted insertion needle.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
[0029] Embodiments of the invention relate to multilayer electronic
devices and methods for fabrication of multi-layer electronic
devices. Particular embodiments of the invention relate to highly
stable multilayer electronic devices and methods of fabrication
thereof, for use in caustic or sensitive environments, such as
medical and implant environments. In such embodiments, the material
used for a patterned dielectric or other patterned materials in the
multilayer electronic device are selected, in part, for suitable
environmental compatibility.
[0030] However, as described above, materials that are selected
based on environmental compatibility may not be the materials best
suited for being formed into the precise patterns that may be
required for an electronic circuit design, using traditional
manufacturing processes. Accordingly, embodiments of the present
invention employ improved techniques for forming sacrificial
structures that are removed during fabrication, to leave a pattern
(the reverse pattern of the sacrificial structure pattern) of a
dielectric material in the layered structure. Processes using
sacrificial structures formed by shadow masking techniques are
described in U.S. patent application Ser. No. 10/671,996, filed 26
Sep. 2003, which has been incorporated herein by reference.
However, shadow masking techniques can be impractical for forming
certain pattern shapes or precision details in patterned layers.
Also, shadow masking techniques can be impractical for forming
patterns in large spanses, such as for large devices or for forming
multiple devices simultaneously.
[0031] Accordingly, embodiments of the present invention relate to
multilayer electronic devices and processes for making such
multilayer devices in which electroplated sacrificial structures
are used during fabrication to pattern certain dielectric or other
material in one or more layers. Electroplating techniques used in
embodiments of the invention are capable of providing sacrificial
structures to form layer patterns that are more precise or in
configurations not possible or practical with shadow mask
deposition techniques. Furthermore, electroplating techniques used
in embodiments of the invention are capable of efficiently and
economically forming such sacrificial structures in relatively
large spanses, such as for making relatively large electronic
devices or for making a relatively large arrangement of multiple
electronic devices, such as a wafer that is cut, after formation,
into multiple electronic devices.
[0032] As described in further detail below, a dielectric material
(or other material) in the multilayer device may be formed in a
pattern by depositing a layer of the dielectric material (or other
material) over sacrificial structures that have been electroplated
in a selected pattern on an underlying layer. The dielectric
material (or other material) may be deposited over the
electroplated pattern of sacrificial structures, using a vacuum
deposition process. Thereafter, some or all of the sacrificial
structures may be removed, for example, with an etching process
that attacks the sacrificial structures from exposed or lightly
covered side edges of the sacrificial structures, but does not
remove the dielectric material (or other deposited material),
leaving a selected pattern of the dielectric material (or other
deposited material).
[0033] A variety of different dielectric materials (or other
materials) may be formed in selected patterns in a multilayer
electronic device in accordance with such processes as described
below, including materials that have been difficult or impractical
to form in precise patterns using traditional processes.
Accordingly, embodiments of the invention can provide an electronic
device designer with a greater variety of options for selecting
materials to use in the patterned portions of a multilayer
electronic device. In contexts in which the electronic device is to
be operated or otherwise located in a caustic or sensitive
environment, embodiments of the present invention may provide the
designer with a greater variety of options of materials that are
suitably compatable or inert with respect to the environment may be
employed.
[0034] Therefore, particular embodiments of the invention relate to
highly stable multilayer electronic devices and methods of
fabrication thereof, for use in caustic or sensitive environments,
such as medical and implant environments. In such embodiments, the
material used for a patterned dielectric or other patterned
materials in the device are selected, in part, for suitable
environmental compatibility. Environmental compatibility may
involve one or more of the ability for the material to provide its
intended function over an intended operational life while disposed
within the intended operational environment, the ability of the
material to avoid contaminating or otherwise harming its
operational environment during its intended operational life, or
the like.
[0035] Example embodiments of a method for producing a multilayer
circuit are described below, in the context of production of
medical devices and, in particular a hermetic blood glucose sensor
circuit designed to be implanted into a patient's body. Other
embodiments may be employed in the context of production of other
types of electronic circuits or electronic components (collectively
referred to as electronic devices) used in medical devices and, in
particular, to electronic devices designed to be implanted in a
biological entity and, thus, subjected to an implant environment.
Yet other embodiments may be employed for electronic devices
designed for non-biological or non-medical applications that are
subject to other forms of caustic or sensitive environmental
conditions. Examples of alternative applications are provided
below.
[0036] Because aspects of embodiments of the invention may be
employed for a variety of different types of electronic devices and
components, a generalized description of aspects of the invention
is provided with respect to FIGS. 1a-1f, which shows the formation
of a portion of a multilayer electronic circuit device. The example
multilayer electronic circuit device formed according to FIGS.
1a-1f may be configured for any suitable context of use, including,
but not limited to the medical device context for which a similarly
labeled device is shown in FIGS. 2a-2k and 4. In particular, FIGS.
2a-2k show an example of a multilayer electronic circuit configured
as part of a medical device, such as an implantable blood glucose
level sensor. A generalized flow chart of a process of forming a
multilayer circuit or circuit component as described herein is
shown in FIG. 3. FIG. 4 shows an example of a medical device having
a multilayer circuit as formed in accordance with FIGS. 2a-2k.
[0037] According to embodiments of the invention described herein,
an electronic circuit or circuit component is formed with multiple
layers of selected materials that are deposited (as described
below) on a suitable support structure, such as a base substrate.
FIGS. 1a through 1f show side views of structures formed during
processing in accordance with an example embodiment of a process
for producing a multilayer circuit for any suitable application of
use. FIG. 1a shows a base substrate 30 having one or two major
surfaces (the surfaces facing upward and downward in the
drawing).
[0038] More specifically, FIG. 1a shows the substrate 30, after
formation of patterned conductors 36 on the upward-facing major
surface of the base substrate 30. In one example embodiment, the
conductors 36 are formed of consecutive layers of titanium,
platinum and titanium that are patterned by a photoresist lift-off
process. In the lift-off process, a photoresist layer is patterned
to form a negative image of the conductors 36 using a conventional
exposure and developing technique. A blanket metal thin film is
formed over the substrate and the photoresist pattern such as by
physical vapor deposition (sputtering), and a photoresist stripping
chemistry is then used to remove the photoresist pattern. Metal
deposited on the photoresist is lifted off as the underlying
photoresist is dissolved, while metal deposited on the base
substrate adheres to the base substrate and remains after lift-off.
Accordingly, precise lithographically patterned thin film
conductors may be formed with precise alignment to the base
substrate 30 and any vias that may be formed in the substrate. In
other embodiments, the patterned conductors 36 are formed by other
suitable processes for forming patterned conductive material on a
substrate.
[0039] FIG. 1b shows the structure of FIG. 1a after formation of a
seed layer 12 for electroplating on or sufficiently near the
opposite surface of the substrate from the surface on which
electroplated material is to be deposited. The seed layer comprises
electrically conductive material disposed in a selected pattern.
The seed layer may be formed by a photolithography process or other
suitable process for applying a conductive material to the
substrate. Photolithography may be a preferred manner of applying a
seed layer, in contexts in which a fine or precise pattern is
desired. Photolithographic processes can produce finer, more
intricate patterns than may be practical with conventional masking
techniques.
[0040] FIG. 1c shows the structure of FIG. 1b after formation of
sacrificial structures 38 on the base substrate 30 and the
conductors 36. The sacrificial structures 38 are used to define
areas of the base substrate 30 and conductors 36 that are to be
protected during subsequent deposition of a dielectric material.
The sacrificial structures 38 are preferably formed of a material
that will survive subsequent vacuum deposition of dielectric and
that is easily removed in later processing by an etchant that is
selective of the sacrificial material with respect to other exposed
materials.
[0041] The sacrificial structures 38 may be formed of gold that is
applied in a desired pattern using an electroplating process, where
the seed layer (bearing a positive image of the desired pattern)
controls the location at which the sacrificial structures are
formed. Gold is electroplated in a pattern corresponding to the
pattern on the seed layer. In other embodiments, other suitable
sacrificial materials may be employed, as described below. In
particular, a suitable sacrificial material may be a material that
is capable of being applied by electroplating processes, is
compatable with the substrate 30, conductors 36 and the selected
overlying dielectric material (described below), yet is readily
soluable or otherwise removeable with an etchant or other suitable
agent that will not effectively remove the dielectric material
selected of the overlying dielectric layer (described below).
[0042] FIG. 1d shows the structure of FIG. 1c, after the
electroplating seed layer is removed, leaving patterned gold
sacrificial structures 38. It is preferable to form the sacrificial
structures 38 to be substantially thicker than the subsequent
dielectric layer that is to be patterned using the sacrificial
structures 38.
[0043] FIG. 1e shows the structure of FIG. 1d after forming a
dielectric thin film 40 over the base substrate, the conductors and
the sacrificial structures. In an example embodiment the dielectric
material is alumina and is vacuum deposited by a method such as
sputtering or evaporation, producing a highly hermetic dielectric
material in an "as fired" form, that is, in a form that will not
undergo significant structural changes such as shrinkage during
subsequent processing. To enhance the density, adhesion and
hermeticity of the dielectric thin film 40, ion beam assisted
deposition (IBAD) may be employed, wherein the deposited dielectric
material is bombarded with low energy ions during deposition to
provide improved adhesion and coating density. Formation of
dielectric thin films by vacuum deposition can produce layers
having thicknesses in the range of 100 angstroms to 20 microns
(0.00004-0.0008 inches), compared to the conventional minimum green
sheet thickness of 0.006 inches or approximately 150 microns.
Accordingly, the use of vacuum deposited dielectric thin films
rather than conventional sheet dielectrics allows the production of
significantly thinner multilayer substrates or the production of
multilayer substrates having significantly more layers than those
formed by conventional lamination methods. In addition, vacuum
deposited layers are highly hermetic and provide significant
protection of underlying materials against the outside
environment.
[0044] FIG. 1f shows the structure of FIG. 1e after patterning of
the deposited dielectric layer 40 by selective removal of the gold
sacrificial structures. The gold sacrificial structures may be
removed selectively with respect to the titanium conductors, and
alumina base substrate, using a ferric chloride solution or another
mild etchant that is selective with respect to the gold sacrificial
structures.
[0045] The etchant reaches the gold sacrificial structures through
pin-holes and other imperfections in the extremely thin layers of
dielectric material that are deposited on the sidewalls 42 of the
sacrificial structures 38. By forming the sacrificial structures 38
to be substantially thicker (taller in the drawings) than the
dielectric layer 40, it is ensured that there will be sufficiently
thin sidewall coverage and sufficient sidewall surface area to
enhance penetration of the etchant. As the gold sacrificial
structures 38 dissolve, the portion of the dielectric thin film 40
overlying the sacrificial structures 38 collapses and is rinsed
away in subsequent cleaning, leaving a patterned dielectric thin
film as shown in FIG. 1f that protects selected portions of the
conductors 36 and base substrate 30 surface area while also
selectively exposing portions of the conductors 36 for connection
to overlying conductors.
[0046] The sacrificial structures 38 may be precisely positioned
relative to the base substrate 30 and conductors 36 using the
electroplating process described above. In addition, because the
deposited dielectric thin film 40 will not undergo significant
structural changes during further processing, the openings in the
deposited dielectric thin film 40 may be precisely aligned with the
underlying conductors 36 and base substrate 30. Accordingly, the
dielectric film 40 may be formed with a relatively high level of
pattern precision and in relatively intricate pattern
configurations.
[0047] Depending upon the type of circuit or circuit component
being formed, one or more additional layers of conductive material,
electroplated sacrificial structures and/or dielectric material may
be formed over the structure shown in FIG. 1f. In this regard,
further embodiments of the present invention may involve a layered
electrical circuit or circuit component that has more than one
dielectric layer, each of which are patterned using electroplated
sacrificial structures, as described above. Also, depending upon
the type of circuit or circuit component being formed, layers of
material may be formed on both major surfaces of the substrate 30,
according to processing as described above.
[0048] Embodiments of the invention may be employed to produce a
wide variety of different types of electronic circuits and circuit
elements. As an example for assisting in the description of aspects
of the invention, processes are described below for forming a
multilayer circuit and a medical device that includes a multilayer
circuit, such as a blood glucose sensor device 10 as shown in FIG.
4. However, it will be understood that aspects of the invention may
be employed for multilayer circuits or circuit elements for other
medical or non-medical devices.
[0049] The sensor device 10 of FIG. 4 includes multiple layers 20
of dielectric, conductive and insulative materials formed on at
least one side of a base substrate 30 to form an electronic circuit
and/or circuit elements. One or more of the multiple layers 20 are
formed in patterns, by processes that use electroplated sacrificial
structures, as described below. Depending upon the type of device
formed with the inventive processes, the multiple layers 20 may be
part of an overall electronic circuit, a complete electronic
circuit or one or more electronic components. Also depending upon
the type of device formed by the inventive process, the electronic
circuit or circuit elements formed by the layers 20 may be
electrically coupled to one or more further electronic components,
represented in the medical device embodiment of FIG. 4 as an
integrated circuit 52 and a discrete capacitor 54. In further
embodiments, circuit components (such as the discrete capacitor 54)
may be formed in accordance with the multilayer processing
techniques described herein.
[0050] Processes for forming a multiple layer electrical circuit 20
using electroplated sacrificial structures according to embodiments
of the invention described herein may be employed with a variety of
different types of dielectric or other materials in the layered
circuit 20. Such processes are capable of forming many different
types of dielectric or other materials in patterns with precision
and configurations that were not practical with shadow masking
deposition techniques.
[0051] In some embodiments, the base substrate 30 may provide an
hermetic seal between two opposite sides of the base substrate,
such as in contexts in which a sensitive circuit or circuit element
formed with the layers 20 and/or components 52 and 54 on one side
of the base substrate 30 is to be protected from environmental
conditions on the other side of the substrate. For example, as
shown in FIG. 4, a reactive sensor element 60, such as a sensor
enzyme, may be located on one side of the base substrate 20 and may
be exposed to biological media 62 present in a medical or implant
environment. Examples of various sensor configurations that include
enzymes for use in medical sensor circuit devices are described in
U.S. Pat. Nos. 6,477,395, 6,498,043, 6,512,939 and 6,809,507, each
of which is incorporated herein by reference.
[0052] An electronic circuit may be formed with layers 20 on the
other side of the base substrate and protected from the medical or
implant environment, at least in part, by the hermetic base
substrate. A cap 56 over the layers 20 and components 52 and 54 may
provide a further portion of the hermetic seal. Hermetically sealed
conductive vias 32 may be provided through the base substrate to
connect conductors 44 on the enzyme side of the base substrate with
circuit elements formed in the layers on the other side of the base
substrate. An example process for forming hermetic vias in a base
substrate is described in U.S. patent application Ser. No.
10/671,996, filed 26 Sep. 2003, which has been incorporated herein
by reference. However, other embodiments may employ other suitable
processes for providing hermetic vias in the base substrate 30. Yet
other embodiments may employ a base substrate and vias that need
not provide an hermetic seal, wherein the vias may be formed in any
suitable via forming process.
[0053] FIGS. 2a through 2k show structures formed during processing
in accordance with an example embodiment of a process, as generally
described above, but for producing a blood glucose sensor using a
base substrate having vias formed therein. Each of FIGS. 2a through
2k provides a top plan view, a cross-section taken along line A-A'
of the top plan view, and a bottom plan view of a section of a
substrate upon which processing is performed in accordance with the
preferred embodiment.
[0054] FIG. 2a shows a base substrate 30 having a plurality of
hermetic vias 32 extending between its major surfaces, as described
above. FIGS. 2b-2k show the formation of multiple layers
(represented by the layers 20 in FIG. 1) on the base substrate
30.
[0055] FIG. 2b shows the structure of FIG. 2a after formation of
conductive welding pads 34 on the top surface of the substrate 30.
The welding pads 34 provide connection points for external wires to
the circuitry that will be mounted on the substrate. The welding
pads of the preferred embodiment are formed by screen printing
using a platinum conductive ink, however in alternative embodiments
contacts may be formed by other suitable techniques.
[0056] FIG. 2c shows the structure of FIG. 2b after formation of
patterned conductors 36 on the top surface of the base substrate 30
and over at least a portion of the conductive pads 34. In one
example embodiment, the conductors 36 are formed of consecutive
layers of titanium, platinum and titanium that are patterned by a
photoresist lift-off process, as described above with respect to
FIG. 1a.
[0057] FIG. 2d shows the structure of FIG. 2c after formation of
sacrificial structures 38 on the base substrate 30 and the
conductors 36. The sacrificial structures 38 are used to define
areas of the base substrate 30 and conductors 36 that are to be
protected during subsequent deposition of a dielectric material.
The sacrificial structures 38 are preferably formed of a material
that will survive subsequent vacuum deposition of dielectric and
that is easily removed in later processing by an etchant that is
selective of the sacrificial material with respect to other exposed
materials. In one example embodiment, the sacrificial structures 38
are gold that is formed in a desired pattern using an
electroplating process as described above. The sacrificial
structures 38 are formed to be substantially thicker than the
subsequent dielectric layers that is to be patterned using the
sacrificial structures 38.
[0058] FIG. 2e shows the structure of FIG. 2d after vacuum
deposition of a dielectric thin film 40 over the base substrate,
the conductors and the sacrificial structures. In an example
embodiment the dielectric material is alumina and is vacuum
deposited by a method such as sputtering or evaporation, producing
a highly hermetic dielectric material in an "as fired" form, as
described above. To enhance the density, adhesion and hermeticity
of the dielectric thin film 40, ion beam assisted deposition (IBAD)
may be employed, also as described above.
[0059] FIG. 2f shows the structure of FIG. 2e after patterning of
the deposited dielectric layer 40 by selective removal of the gold
sacrificial structures. The gold sacrificial structures may be
removed selectively with respect to the titanium conductors, and
alumina base substrate, using a ferric chloride solution or another
mild etchant that is selective with respect to the gold sacrificial
structures, as described above. Because the sacrificial structures
38 are precisely positioned relative to the base substrate 30 and
conductors 36 using the electroplating process described above, and
because the deposited dielectric thin film 40 will not undergo
significant structural changes during further processing, the
openings in the deposited dielectric thin film 40 are precisely
aligned with the underlying conductors 36 and base substrate 30,
enabling greater via and conductor densities and providing greater
process yield.
[0060] FIG. 2g shows the structure of FIG. 2f after formation of
additional welding pads 42 on the top surface of the base substrate
30, followed by formation of sensor electrodes 44 on the bottom
surface of the base substrate 30. The sensor electrodes 44 may be
formed, for example, of successive thin films of titanium, platinum
and titanium that are patterned on the bottom surface of the base
substrate 30 by a photoresist lift-off process.
[0061] FIG. 2h shows the structure of FIG. 2g after formation of
caps 46 over portions of the sensor electrodes 44 that are in
contact with vias 32 that extend through the dielectric base
substrate 30. The caps 46 prevent access of fluid contaminants to
the vias 32 and portions of the base substrate 30 in the vicinities
of the vias that may be somewhat amorphous as a result of laser
drilling and therefore more susceptible to chemical degradation. In
the preferred embodiment the caps 46 are highly pure alumina caps
that are formed using a positive shadow mask process, thus allowing
precise registration of the caps 46 to the vias 32.
[0062] FIG. 2i shows the structure of FIG. 2h after formation of
gold contact pads 48 on exposed portions of the conductors 36. The
gold contact pads 48 provide contact points for electrical
connection of integrated circuits and discrete devices to the
conductors 36. A gold ring 50 is also formed at the perimeter of
the deposited dielectric thin film 40 and defines an area within
which circuit components will be mounted. The gold ring 50 is used
in later processing for bonding a protective cap over the circuit
components. The gold contact pads 48 and gold ring 50 may be
formed, for example, by a photoresist lift-off process.
[0063] FIG. 2j shows the structure of FIG. 2i after mounting of an
integrated circuit 52 and a discrete capacitor 54 to the multilayer
substrate composed of the base substrate 30, the conductors 36 and
the deposited dielectric thin film 40. The integrated circuit 52 is
connected to the gold contact pads 48 by wire bonds. In the
preferred embodiment, the integrated circuit is in electrical
communication with the sensor electrodes 44 on the bottom of the
base substrate 30 through the conductors 36 formed on the top
surface of the base substrate 30 and the hermetic vias 32 formed
through the base substrate 30. The integrated circuit 52 makes
oxygen and glucosine measurements using readings taken from the
sensor electrodes 44 and provides a digital output representing
those measurements. While the preferred embodiment connects the
integrated circuit 52 using wire bonds, in alternative other
connection structures such as flip chip and ball grid array
structures may be used.
[0064] FIG. 2k shows the structure of FIG. 2j after bonding of a
protective cap 56 to encase the circuit components. The cap 56 is
preferably a gold cap that is bonded to the gold ring formed on the
deposited dielectric thin film. In the resulting structure the
protective cap 56 provides a hermetic seal against fluids at the
top surface of the substrate, while the hermetic vias 32 and their
associated caps 46 provide hermetic seals against fluids at the
exposed bottom surface where the sensor electrodes 44 are located.
The deposited dielectric thin film 40 that lies between the gold
cap and the base substrate is also hermeticity bonded to the base
substrate 30 by virtue of its vacuum deposition, and as a result
the circuit components are completely hermeticity sealed against
the outside environment.
[0065] While the processing shown in FIGS. 2a-2k represents a
preferred embodiment for producing a blood glucose monitor, the
techniques used in the disclosed processing are generally
applicable to a wide range of applications in which it is desired
to produce thin multilayer substrates. For example, techniques
employing electroplated sacrificial structures may be employed in
processes in which it is desirable to pattern a dielectric or other
material, such as alumina, with a precision or in configurations
that have, traditionally, been impractical with shadow masking
techniques. Alternatively or in addition, such techniques may be
used to produce thin multilayer substrates with a high degree of
alignment precision, relatively little shrinkage, and/or a
potentially high conductor and via density.
[0066] In general terms the techniques of the preferred embodiment
may be adapted to form multilayer substrates comprised of any
desired number of dielectric and conductors layers. The substrate
is formed of patterned dielectric and conductive thin films that
are deposited on a base substrate. Deposited dielectric layers are
patterned using electroplated sacrificial structures to form
openings in the dielectric layers for vias or for exposing larger
contact areas of conductors.
[0067] The thin films used in accordance with embodiments of the
invention are preferably vacuum deposited. For purposes of this
disclosure, the term vacuum deposited refers deposition of a
material at a low pressure in a controlled atmosphere. Such
techniques include evaporation, sputtering (PVD) and chemical vapor
deposition (CVD). Evaporation is preferably used where it is
desired to form a relatively thick layer, e.g. 10 microns. However
evaporation provides relatively poor adhesion and density. The
adhesion and density of evaporated layers may be improved through
the use of ion bombardment (ion-assisted evaporation). Sputtering
(PVD) is preferred where adhesion is a priority. However the growth
rate of layers formed by sputtering is approximately an order of
magnitude slower than those formed by evaporation. CVD may be used
as needed to form layers of materials that are not easily formed by
evaporation or sputtering.
[0068] While embodiments described above employ a vacuum deposited
alumina dielectric material and gold sacrificial structures that
are etched using a ferric chloride solution, other embodiments may
employ other suitable sacrificial materials, dielectric materials
and etchants. The dielectric material (or other material to be
patterned by the electroplated sacrificial structures) may be any
suitable material that provides intended electrical and/or
structural functions within the multi-layer electrical circuit or
circuit component, and that is compatable with the selected
sacrificial material, etchant and the underlying or overlying
layers. By using electroplated sacrificial structures to pattern
the dielectric (or other) material, many materials that were,
heretofor, difficult or impractical to pattern using conventional
processes may employed.
[0069] Accordingly, embodiments of the invention also provide great
freedom of choice with respect to the deposited dielectric
material. In some embodiments, the dielectric layer should be
capable of formation by a vacuum deposition technique that provides
good adhesion to underlying materials and good process control for
producing very thin layers. As a general matter any dielectric
material that can be obtained in a substantially pure form may be
evaporated and vacuum deposited as a thin film on a substrate. A
variety of deposited dielectric materials may be used including
alumina, aluminum nitride, silicon oxide, silicon nitride, silicon
oxynitride, titanium nitride and the like. Vacuum deposited
dielectric thin films provide a number of desirable properties,
including highly controllable thickness, high hermeticity,
dimensional stability, thermal and chemical stability, and tunable
dielectric and thermal conductance properties. For purposes of this
disclosure, the term "deposited dielectric" is therefore used not
only to describe the processing by which the dielectric is formed,
but also the resulting structural features of the deposited
dielectric that distinguish it from conventional laminated
dielectrics, including its conformality and hermeticity with
respect to the materials on which it is formed, its high density
and adhesion, and its dimensional, thermal and chemical
stability.
[0070] As described above, a suitable sacrificial material may be
any material that is capable of being applied by electroplating
processes, is compatable with the substrate 30, conductors 36 and
the selected overlying dielectric material (described below), yet
is readily soluable or otherwise removeable with an etchant or
other suitable agent that will not effectively remove the
dielectric material selected of the overlying dielectric layer
(described below). While gold is used as the sacrificial material
in embodiments described above, other suitable sacrificial
materials may include, but are not limited to, silver, copper,
nickel, aluminum or combinations thereof, depending upon their
electrical and/or structural characteristics and compatibility with
other layers and the intended environment of use. Examples of
various types of electroplatable sacrificial materials and
corresponding compatible dialectic materials and etchant materials
are shown in the respective rows of table 1, below. However, it
will be understood that aspects of the invention may be employed
with other suitable electroplatable sacrificial materials,
dielectric materials and etchant materials, or other suitable
combinations thereof.
[0071] With regard to the base substrate, a rigid sheet of an
as-fired dielectric ceramic material may be used in accordance with
some embodiments of the present invention. However, the base
substrate may be composed of a wide variety of substrate materials
since the deposition processes used to form forming dielectric and
conductive thin films are performed at relatively low temperatures,
and patterning of those thin films using sacrificial structures
utilizes relatively mild etchants. While the preferred embodiment
uses a substrate comprising 92-96% purity alumina, high purity
berillia and aluminum nitride base substrates may also be used.
[0072] Other types of dielectric substrates such as flexible
materials, including, but not limited to polyimide flex board,
flexible substrate tape, or the like, or nonflexible materials,
including but not limited to standard printed circuit board
substrates comprised of epoxy resin with or without impregnated
glass fiber may also be used. Further embodiments of flexible
substrates and processes for forming multiple layer circuit devices
therewith are described in U.S. patent application Ser. No.
09/779,282 filed Feb. 8, 2001, and U.S. patent application Ser. No.
09/502,204, filed Feb. 10, 2000, each of which is incorporated
herein by reference.
[0073] For example, as shown in FIG. 5, a bead, which can be hollow
(see FIG. 5, bead 150), is formed on the lower surface 18 of the
substrate 30. The bead can be formed on the surface of the
substrate by a variety of means, such as by securing a cylindrical
element to the surface, by molding, laminating, or the like. The
bead can be provided either before or after the sensor is removed
from the remainder of the substrate 30. Once formed, the bead
directly engages a slotted insertion needle 114 (FIG. 6) of a
sensor set as described herein.
[0074] Flexible substrates may be employed, for example, in
contexts in which the multilayer circuit device is to be bent or
otherwise flexed during operation or while being positioned within
its operational environment or within the structure of a housing,
packaging or the like. In addition, in certain contexts, flexible
substrates may be beneficial for forming relatively large
multilayer circuit structures (e.g., relatively large circuit
devices or relatively large structures of multiple circuit
devices). Furthermore, flexible substrates may be used in
manufacturing processes in which the substrate and/or the
manufactured multilayer circuit device are manufactured, packaged,
stored or otherwise disposed in one or more windings or coils, for
example, for space efficiency. According to embodiments of the
present invention, processes for forming vias and multi-layer
electronic structures as described herein may employ thin film
flexible substrates. In some embodiments, such electronic
structures formed with flexible substrates in accordance with
aspects of the present invention may be employed in subcutaneous
sensors (for subcutaneous implantation in a biological entity). For
example, sensors designed for short term usage (in the order of a 1
to 3 days, a week, a month or the like) may employ via and
multi-layer technology described herein to provide a relatively
thin (narrow) structure by allowing at least some of leads to pass
through the substrate, while providing sufficient structural
integrity to function properly for at least for the period of
intended use.
[0075] In optical applications, substrates such as glass and
sapphire may be used. For radiation hardened applications a gallium
arsenide (GaAs) substrate may be used, and may be provided with a
thin dielectric protective layer as required. In advanced
applications, the substrate may be a semiconductor substrate such
as silicon or GaAs that has an application specific integrated
circuit (ASIC) formed therein by conventional lithographic
techniques. Thin film dielectric and metal layers may then be
formed on the semiconductor substrate in the manner of the present
invention to protect the ASIC and to form sensor electrodes and
metal patterns for connection of discrete components to the
ASIC.
[0076] With regard to conductors, it is preferred to utilize thin
film conductors that are patterned by shadow masking, photoresist
lift-off patterning or chemical etching. However in alternative
embodiments conductors may be formed by other methods such as
screen printing. The thickness of the conductors may be selected in
accordance with a type of joining operation that will be performed
on the conductor. For example, conductors that will be resistance
welded may be formed of a thick layer, while conductors that will
be connected by a low power technique such as wire bonding may be
formed of a thin film. Further, while the preferred embodiment
provides conductors that are designed for wire bonding, in
alternative embodiments the conductors may be patterned for use in
other integrated circuit connection structures, such as flip chip
and ball grid array structures. The types of conductor materials
that may be used are not limited by processing conditions as in
some conventional lamination methods, and may therefore be chosen
in accordance with the particular application. Conductor materials
may include metals such as platinum, gold, silver, copper,
titanium, tungsten, and aluminum, as well as alloys, conductive
compounds such as silicides, or any other conductor that is
applicable in a particular implementation. While the conductors of
the preferred embodiment are formed of successive layers of
different conducting materials, single conducting materials may
also be employed.
[0077] In accordance with embodiments of the present invention, one
or more thin film dielectric layers in the multiple layer circuit
20 are patterned using sacrificial structures formed by
electroplating. While the example embodiment described above
utilized a single dielectric thin film having relatively large
patterned openings, in alternative embodiments multiple layers of
dielectric thin films may be employed, and the dielectric thin
films may have very small patterning features such as vias for
connecting conductors in adjacent layers. The pattern precision
available by using electroplated sacrificial structures allows the
dielectric thin films to be formed in smaller or finer patterns, in
configurations or shapes that were not practical with shadow
masking techniques. Because shadow mask apertures are typically
formed by laser drilling methods, the aperture pattern is limited
by the laser capabilities. In particular, electroplated sacrificial
structures enable formation of vias with diameters smaller than the
0.002 inches and with spacings smaller than 0.006 inches.
[0078] Accordingly, using conductive and dielectric thin films and
patterning techniques (with electroplated sacrificial structures)
in accordance with embodiments of the invention, the dimensions of
multilayer substrate features may be significantly reduced compared
to those produced through conventional lamination techniques.
[0079] While the multilayer substrates of example embodiments
described herein are comprised solely of vias, conductors and
dielectric layers, alternative embodiments may integrate or embed
passive components such as capacitors, resistors and inductors into
the multilayer substrate. For example, while the circuit of one
example embodiment described herein comprises a discrete capacitor,
in alternative embodiments a capacitor may be integrally formed in
the multilayer substrate from conductors separated by a deposited
dielectric layer. Capacitors may be formed, for example, using a
silicon oxide or silicon nitride dielectric layer between
conductive plates. Interdigitated capacitors and trench may also be
formed. The degree of material control and geometrical precision
provided by vacuum deposition and patterning of the dielectric
layers allows for precise patterning of the capacitor structure as
well as tuning of the capacitor parameters through control of the
thickness and dielectric constant of the deposited dielectric
layer. Thin film inductors and thin film resistors may also be
integrated into the multilayer substrate. Thin film resistors may
be patterned from layers of materials such as tantalum nitride
(TaN), polysilicon, titanium, cermet or nichrome. In other
embodiments, substrate layers may be patterned to form
micro-electro-mechanical systems (MEMS) that are integrated with
the layers of the substrate. For example, the patterning techniques
described above can be used to fabricate structures such as
microfluidic structures, valves, reaction chambers, strain gages,
micro-actuators, electromechanical sensors arrays and optical
detectors. Additional properties of the multilayer substrate such
as thermal management, power management, shielding and grounding
can be precisely controlled through choices of layout and
materials.
[0080] A wide variety of embodiments may therefore be implemented
in accordance with the invention. In general terms, multilayer
circuit substrates fabricated in accordance with example
embodiments of the invention are characterized by a base substrate
or other support having conductors supported therewith, and at
least one layer of a vacuum deposited dielectric thin film
overlying the conductors and formed in a pattern with electroplated
sacrificial structures. In various implementations, multiple layers
of conductors and dielectric thin films may be used, conductors may
be formed from thin films or combinations of thin and thick films,
multiple layers may be formed on one or both sides of the base
substrate, and the base substrate may include hermetic vias.
[0081] FIG. 3 shows a generalized process flow for producing a
multilayer circuit substrate that encompasses the preferred
embodiment, the aforementioned alternative embodiments, and further
alternatives. Initially a dielectric base substrate is provided
(60). Conductors are then formed on the base substrate (62),
preferably by patterning of a blanket layer of a conductive thin
film deposited by a vacuum deposition method. Sacrificial
structures are then electroplated on the base substrate and
conductors (64). The sacrificial structures define areas of the
base substrate and conductors that are to be protected during
subsequent dielectric deposition. A dielectric thin film is then
vacuum deposited on the base substrate, the conductors and the
sacrificial structures (66), and the sacrificial structures are
removed (68) to leave a patterned dielectric thin film on the
conductors and the base substrate. Further processing such as
forming additional conductor layers and dielectric layers or
mounting of electronic components may be performed.
[0082] It will be apparent to those having ordinary skill in the
art that the tasks described in the above processes are not
necessarily exclusive of other tasks, but rather that further tasks
may be incorporated into the above processes in accordance with the
particular structures to be formed. For example, intermediate
processing tasks such as formation and removal of passivation
layers or protective layers between processing tasks, formation and
removal of photoresist masks and other masking layers, application
and removal of antireflective layers, doping, cleaning,
planarization, annealing and other tasks, may be performed along
with the tasks specifically described above. Further, the processes
may be performed selectively on sections of a base substrate or at
multiple locations on the base substrate simultaneously. Thus,
while the embodiments illustrated in the figures and described
above are presently preferred, it should be understood that these
embodiments are offered by way of example only. The invention is
not limited to a particular embodiment, but extends to various
modifications, combinations, and permutations encompassed by the
appended claims and their equivalents.
* * * * *