U.S. patent application number 11/857576 was filed with the patent office on 2009-03-19 for depletion mode field effect transistor for esd protection.
This patent application is currently assigned to TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Josef Muenz, Yohichi Okumura.
Application Number | 20090072314 11/857576 |
Document ID | / |
Family ID | 40453528 |
Filed Date | 2009-03-19 |
United States Patent
Application |
20090072314 |
Kind Code |
A1 |
Okumura; Yohichi ; et
al. |
March 19, 2009 |
Depletion Mode Field Effect Transistor for ESD Protection
Abstract
The object of this invention is to present a field effect
transistor by which the drain capacitance per unit gate width can
be reduced. The gate electrode 21 (G) having a plurality of sides
is formed in first-conductivity first semiconductor region 14,
drain region 18D (D) is formed inside the gate electrode, and
source regions 18S (S) are formed in the respective regions outside
the plurality of sides in widths that do not reduce the
corresponding channel widths of the drain region. The gate
electrode is formed along all the plurality of sides of the drain
region in order to form a transistor.
Inventors: |
Okumura; Yohichi;
(Nerima-Ku, JP) ; Muenz; Josef; (Muenchen,
DE) |
Correspondence
Address: |
TEXAS INSTRUMENTS INCORPORATED
P O BOX 655474, M/S 3999
DALLAS
TX
75265
US
|
Assignee: |
TEXAS INSTRUMENTS
INCORPORATED
Dallas
TX
|
Family ID: |
40453528 |
Appl. No.: |
11/857576 |
Filed: |
September 19, 2007 |
Current U.S.
Class: |
257/355 ;
257/E29.264 |
Current CPC
Class: |
H01L 21/823425 20130101;
H01L 27/0266 20130101; H01L 27/0207 20130101 |
Class at
Publication: |
257/355 ;
257/E29.264 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Claims
1. Claim 1 is a field effect transistor, comprising: a
semiconductor region of a first conductivity type with a channel
formation region; a gate electrode that is formed in a pattern with
a plurality of sides on a gate insulation film above the channel
formation region of the first semiconductor region; a drain region
that is formed in the first semiconductor region within an inner
region of the gate electrode; and second-conductivity type source
regions that are formed in the first semiconductor region in
regions opposite to said inner region of the gate electrode in
predetermined widths.
2. The field effect transistor of claim 1, wherein the gate
electrode is formed in a two-dimensional grid pattern, and the
drain region and the source region are formed alternately and
repeatedly in two dimensions in regions of the two-dimensional grid
pattern.
3. The field effect transistor of claim 2, wherein back gates are
formed in the first semiconductor region.
4. The field effect transistor of claim 3, wherein the back gates
and the source regions are connected to each other, and a common
potential is applied to them.
5. The field effect transistor of claim 4, wherein the
first-conductivity type is p-type and the second-conductivity type
is n-type.
6. The field effect transistor of claim 5, wherein a
second-conductivity type channel region is formed in the channel
formation region of the semiconductor region.
7. An ESD depletion mode field effect transistor, comprising: a
semiconductor layer of a first conductivity type formed on a
semiconductor substrate; a square drain region of a second
conductivity type formed in the first semiconductor layer; a
plurality of source regions of a second conductivity type formed in
first semiconductor layer at a predetermined distance from the
drain region; a grid-shaped gate electrode formed on a gate
insulating layer above a channel region of the first semiconductor
layer, which is positioned between the drain region and the
multiple source regions and surrounding the drain region, wherein
the multiple source regions are provided at positions that
correspond to respective sides of the drain region; and the
multiple source regions are connected to each other
electrically.
8. The transistor of claim 7 further comprising: the drain region,
the multiple source regions, and the gate electrode all formed in a
repetitive pattern; the drain regions formed in the repetitive
pattern being connected to each other electrically; and the
multiple source regions formed in the repetitive pattern being
connected to each other electrically.
9. The transistor of claim 7 further comprising: a back gate region
of a first conductivity type formed in the first semiconductor
layer; and the multiple source regions and the back gate region
connected to each other electrically.
10. The transistor of claim 9, wherein the channel region comprises
a first-conductivity type semiconductor layer formed in the first
semiconductor layer.
11. The transistor of claim 10, wherein the first-conductivity type
is p-type and the second-conductivity type is n-type.
Description
FIELD OF THE INVENTION
[0001] The present invention pertains to a field effect transistor.
In particular, it pertains to a depletion type n-channel MOS field
effect transistor that is used in a circuit to protect against
electrostatic breakdown of a magnetic head.
BACKGROUND OF THE INVENTION
[0002] For example, in the case of a magnetic head, such as a GMR
magnetic head, incorporated into a magnetic recording device such
as an HDD (hard disk drive), a depletion type n-channel MOS field
effect transistor is utilized inside a preamplifier IC as a
protective circuit to protect the magnetic head from an
electrostatic breakdown.
[0003] FIG. 8(A) is a plan view of a depletion type n-channel MOS
field effect transistor according to the prior art. As shown in the
Figure, gate electrode 41 is formed in a p-type semiconductor
region provided on a semiconductor substrate via a gate insulation
film, and n-type source region 40S and drain region 40D are formed
at surface parts of the p-type semiconductor region at either side
part of gate electrode 41. Furthermore, an n-type channel region is
formed on the surface part of the p-type semiconductor region
immediately below gate electrode 41 so as to form a depletion type
n-channel MOS field effect transistor.
[0004] Due to increased speeds and capacities of HDDs, there is a
demand for depletion type n-channel field effect transistors with
lower on resistances in order to improve the performance of ESD
protection elements at low capacitances. To realize this,
reductions in the on resistance and the drain capacitance are
required, and a technique for reducing the on resistance while
keeping the drain capacitance unchanged has been adopted.
[0005] FIG. 8(B) is a plan view of a depletion type n-channel MOS
field effect transistor according to the prior art. Two gate
electrodes 41a and 41b are formed in a p-type semiconductor region
provided on a semiconductor substrate via a gate insulation film;
and source region 40Sa, drain region 40D, and source region 40Sb
are formed in 3 respective regions that are separated by the two
gate electrodes 41a and 41b on the surface part of the p-type
semiconductor region. N-channel regions are formed in the p-type
semiconductor regions immediately below the two gate electrodes 41a
and 41b so as to form a depletion type n-channel MOS field effect
transistor.
[0006] As opposed to the field effect transistor with the
configuration shown in FIG. 8(A), in the case of the field effect
transistor with the configuration shown in FIG. 8(B), because the
gate width is set approximately two times as wide while keeping the
drain capacitance unchanged, the on resistance is reduced to
approximately one half. That is, the drain capacitance per unit
gate width is reduced by approximately one half.
[0007] However, in recent years, there is a greater demand for
faster driving, and further reduction in the on resistance and the
drain capacitance is needed. The present invention was devised in
light of the aforementioned situation, and its objective is to
present a field effect transistor by which the drain capacitance
per unit gate width can be reduced.
SUMMARY OF THE INVENTION
[0008] In order to achieve the aforementioned objective, the field
effect transistor of the present invention has a first-conductivity
type first semiconductor region with a channel formation region, a
gate electrode that is formed in a pattern with a plurality of
sides above the channel formation region of the first semiconductor
region on a gate insulation film, a second conductivity type drain
region that is formed on the surface part of the first
semiconductor region within the inner region of the gate electrode,
and second-conductivity type source regions that are formed in the
surface layer part of said first semiconductor region in respective
regions outside the plurality of sides of the gate electrode in
widths that do not reduce the corresponding channel widths of the
drain region when looked at from said respective outside
regions.
[0009] In the aforementioned field effect transistor of the present
invention, the gate electrode with the plurality of sides is formed
in the first-conductivity type first semiconductor region with a
channel formation region, a drain region is formed on the inner
side of the gate electrode, and source regions are formed in
respective regions on the outer side of the plurality of sides in
widths that do not reduce the corresponding channel widths of the
drain region. That is, the gate electrode is formed along all the
sides of the drain region when the transistor is configured.
[0010] Preferably, in the aforementioned field effect transistor of
the present invention, the gate electrode is formed repeatedly
two-dimensionally in a grid pattern, and drain regions and the
source regions are formed alternately and repeatedly
two-dimensionally in the inner regions of the aforementioned grids
in such a manner that either a drain region or a source region
corresponds to a grid. In some instances, the back gates are formed
inside the aforementioned first semiconductor region. Furthermore,
the back gates and the source regions are connected to each other
and a common potential is applied to them.
[0011] The field effect transistor of the present invention is used
as a switch in a breakdown protection circuit for a magnetic head
in order to protect the magnetic head from an electrostatic
breakdown.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1(A) is a plan view of the field effect transistor
according to a first embodiment of the present invention.
[0013] FIG. 1(B) is a cross sectional view along A-B-C in FIG.
1(A).
[0014] FIG. 2 is a plan view of a field effect transistor according
to a second embodiment of the instant invention.
[0015] FIG. 3(A) is a cross sectional view along X-X' in FIG. 2
[0016] FIG. 3(B) is a cross sectional view along Y-Y' in FIG.
2.
[0017] FIG. 4 is a plan view showing the layout of first-layer
wirings connected to the source regions, the drain regions, and the
back gate regions of the field effect transistor according to the
second embodiment of the instant invention.
[0018] FIG. 5 is a plan view showing the layout of first-layer
wirings that connect the source regions and the back gate regions
and second-layer wirings that are formed to connect to respective
first-layer wirings that connect the drain regions in the field
effect transistor according to the second embodiment of the instant
invention.
[0019] FIG. 6(A) is a partial cross sectional view of a field
effect transistor according to a third embodiment of the instant
invention
[0020] FIG. 6(B) is a partial cross sectional view of another
example according to a third embodiment of the instant
invention.
[0021] FIG. 7 is a circuit diagram of a circuit for protecting a
magnetic head, such as a GMR magnetic head, against electrostatic
breakdown (ESD) incorporated into a magnetic recording device.
[0022] FIG. 8(A) and FIG. 8(B) are plan views of a depletion type
n-channel MOS field effect transistors according to the prior
art.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] According to the field effect transistor of the present
invention, the gate electrode is formed along all sides of a drain
region. The on resistance can be reduced by a quarter with the same
drain capacity, that is, the drain capacity per unit gate width can
be reduced by a quarter.
[0024] Embodiments of the field effect transistor pertaining to the
instant invention will be explained below with reference to
Figures.
[0025] FIG. 1(A) is a plan view of the field effect transistor
according to the instant embodiment, and FIG. 1(B) is a cross
sectional view along A-B-C in FIG. 1(A). As shown in FIG. 1(B), a
first n-type semiconductor layer (n-type tank) 11 is formed in the
p-type silicon substrate (p-sub) 10. A second n-type semiconductor
layer 12 is then formed on the n-type tank 11. The p-type well
(first-conductivity type first semiconductor region) 14 having a
channel formation region within an element formation region is
formed in the second n-type epitaxial semiconductor layer 12. The
p.sup.+-type buried layer 13 to be used as a back gate is formed at
the bottom surface of p-type well 14 at a depth close to the
boundary between first n-type semiconductor layer 11 and second
n-type semiconductor layer 12. In addition, for example,
element-separating insulation film 15 (I) is formed in a prescribed
pattern on the surface of p-type well 14 to separate elements from
each other. Element-separating insulation film 15 (I) may be formed
by means of a LOCOS (local oxidation of silicon) method or an STI
(shallow trench isolation) method, for example; and an insulation
film formed using the LOCOS method is shown in the figure.
[0026] The polysilicon gate electrode 21 (G) is formed in a pattern
with a plurality of sides above p-type well 14 having a channel
formation region beneath the gate insulation film 20. In addition,
a sidewall insulation film 22 is formed on either side part of gate
electrode 21 (G). The n.sup.+-type source region 18S (S) and drain
region 18D (D) containing a high concentration of an n-type
conductive impurity substance (e.g. arsenic and/or phosphorous) are
formed in the p-type well 14 at either side part of sidewall
insulation film 22. Here, as shown in FIG. 1(A), gate electrode 21
(G) is formed in a square shape, and drain region 18D (D) is formed
within the inner region thereof, whereas source regions 18S (S) are
formed in respective regions outside the plurality of sides of gate
electrode 21 (G) in widths that do not reduce the corresponding
channel widths of drain region 18D (D) when looked at from said
respective regions on the outer side. Referring to FIG. 1(B),
furthermore, LDD (lightly doped drain) region 17 containing a low
concentration of an n-type conductive impurity substance is formed
in the p-type well 14 below sidewall insulation film 22 to a depth
less than that of the source region 18D and drain region 18D in
order to configure a so-called LDD-type source region and drain
region. The n-type channel region 16 containing an n-type
conductive impurity substance is formed in the p-type well 14
serving as the channel formation region below gate electrode 21
(G). For example, it is formed as a shallow region where a high
concentration of As is introduced reducing both the transistor off
current and on resistance.
[0027] The p.sup.30 -type back gate regions 18 BG (BG), which are
electrically connected to p.sup.+-type back gate buried layer 13
are formed in the p-type well 14 corner portions of the gate
electrode 21 (G). Back gate regions 18 BG (BG) may be configured in
such a manner that while they are separated from source regions 18S
(S) by element-separating insulation film 15 (I), the
aforementioned gate electrode 21 (G) is extended as far as the
boundary regions between back gate regions 18 BG (BG) and source
regions 18S (S). In this case, gate electrode 21 (G) takes the
shape of a grid.
[0028] In addition, for example, inter-layer insulation film 23
made of silicon oxide is formed to cover the aforementioned field
effect transistor; opening parts that reach source regions 18S (S),
drain region 18D (D), and back gate regions 18BG (BG) are formed;
and wires (24S, 24D, and 24 BG) connected to source regions 18S
(S), drain region 18D (D), and back gate regions 18 BG (BG) are
formed as one body with plugs buried inside the opening parts.
[0029] According to the depletion type n-channel MOS field effect
transistor of the present embodiment described above, because a
gate electrode is formed along all the sides of the drain region,
when compared with a field effect transistor that has the same
drain region area with a gate electrode along a single side, the on
resistance can be reduced by a quarter with the same drain
capacity, that is, the drain capacity per unit gate width can be
reduced by a quarter using the structure of the instant
invention.
[0030] In the case of the field effect transistor of the present
embodiment configured in the aforementioned manner, wires (24S and
24 BG) are connected, back gate regions 18BG (BG) and source
regions 18S (S) are connected, and a common potential is applied.
In addition, for example, the field effect transistor of the
present embodiment is used as a switch in an electrostatic
breakdown protection circuit for a magnetic head in order to
protect the magnetic head against electrostatic breakdown.
[0031] FIG. 2 is a plan view of a field effect transistor according
to a further embodiment of the instant invention. Gate electrodes
of the kind pertaining to the first embodiment are repeated
two-dimensionally in a grid pattern so as to configure gate
electrode G where either a drain region or a source region
corresponds to a single grid inside the area of the grid pattern,
and drain regions D and source regions S are repeated
two-dimensionally. Drain regions D and source regions S are formed
in a so-called checkered pattern in the aforementioned manner.
[0032] Here, a drain region D is not provided at the outermost
circumference. That is, source regions S are formed at the
positions corresponding to the sides of a square drain region, and
back gate regions BG are laid out between them. As described above,
because the sides cannot be used for a drain region at the
outermost circumference when configuring the transistor, it is
desirable that the outermost region be used for source regions or
back gate regions. However, it is also possible to provide drain
regions at the outermost circumference.
[0033] Although the gate electrode is provided to surround all
source regions S and back gate regions BG at the outermost
circumferential part in consideration of the ease of removing gate
electrode in the aforementioned configuration, the gate electrode
between source regions S and back gate regions BG at said outermost
circumferential part may be deleted, and back gate regions BG and
source regions S may be separated from each other using
element-separation insulation film I.
[0034] Shown in FIG. 3(A) is a cross sectional view along X-X' in
FIG. 2. As in the first embodiment, for example, first n-type
semiconductor layer 11 is formed in p-type silicon substrate 10.
The p.sup.+-type buried layer 13 to be used as the back gate, and a
p-type well (first-conductivity type first semiconductor region) 14
with a channel formation region is further formed. In addition,
gate electrode 21 (G) made of polysilicon is formed in a grid
pattern over the aforementioned p-type well 14 and the channel
formation region (16) is formed beneath the gate insulation film
20, and sidewall insulation film 22 made of silicon oxide or
silicon nitride is formed on either side part of gate electrode 21.
Furthermore, n.sup.+-type source regions 18S and drain regions 18D
are formed alternately and repeatedly in the region inside the
grid, and source regions are provided at the outermost
circumference. The LDD region 17 is formed in the p-type well 14
below sidewall insulation film 22. The n-type channel region 16
containing an n-type conductive impurity substance such as is
formed on the surface part of p-type well 14 serving as the channel
formation region below gate electrode 21.
[0035] Shown in FIG. 3(B) is a cross sectional view along Y-Y' in
FIG. 2. The configuration shown here is similar to that shown in
FIG. 3(A), except that p.sup.+-type back gate regions 18BG
connected electrically to p.sup.+-type buried layer 13 to be used
as back gates are formed at the outermost circumference, and source
regions 18S and drain regions 18D are formed alternately and
repeatedly in the region between them.
[0036] As shown in the Figure, the gate electrode 21 (G) is formed
in the shape of a grid, and extends as far as the boundary between
back gate region 18BG (BG) and source region 18S (S) in the
aforementioned configuration. Here the back gate region 18BG (BG)
and source region 18S (S) may be separated from each other using
element-separating insulation film 15 (I). The multiple source
regions 18S and drain region 18D are connected into a single
system, respectively, using wires to be described later, and back
gate regions 18BG are further connected to source regions 18S.
[0037] FIG. 4 is a plan view showing the layout of a first-layer
wiring connected to the source regions, the drain regions, and the
back gate regions of the field effect transistor pertaining to the
present embodiment. Upper-layer wirings (24S, 24D, and 24BG) are
formed via contacts CT with respect to source regions S, drain
regions D, and back gate regions BG. Source regions S are connected
into a single system using wiring 24S; and because wiring 24 BG is
connected to wiring 24S, source regions S are connected into a
single overall system with back gate regions BG. The drain regions
D are divided into sections where they can be connected to each
other between wirings 24S, that is, into multiple systems in the
figure, and they are connected to wiring 24D.
[0038] FIG. 5 is a plan view showing the layout of first-layer
wirings that connect the source regions and the back gate regions,
the second-layer wirings are formed to connect to respective
first-layer wirings that connect the drain regions in the field
effect transistor pertaining to the present embodiment. The
first-layer wirings 24D divided into multiple sections and are all
connected together into a single system by second-layer wirings
25D. In addition, while wirings 24S (wirings 24 BG) are already
connected into a single system, in this case, the wiring resistance
is reduced by second-layer wirings 25S when they are connected into
the system. Furthermore, for example, the second wirings (25S and
25D) may be formed in regions other than those shown above in order
to reduce the wiring resistance.
[0039] In the aforementioned configuration, the source regions and
the drain regions are divided into multiple sections in a so-called
a checkered pattern, and the gate electrode is provided at
grid-like boundaries between the respective source regions and the
drain regions. As such, while the source regions and the drain
region that are adjacent to each other via the gate electrode
constitute the field effect transistor, the respective source
regions and the drain regions are put together into a single system
and a single depletion type n-channel MOS field effect transistor
is configured as a whole.
[0040] In comparison to a field effect transistor that has the same
drain region area but only a single drain region, the
aforementioned depletion type n-channel MOS field effect transistor
of the present embodiment is equivalent to one in which the gate
width of the transistor is significantly widened. As such, the on
resistance can be reduced with the same drain capacitance, that is,
the drain capacitance per unit gate width can be reduced.
[0041] In the aforementioned field effect transistors of the first
embodiment and the second embodiment, the back gate regions are
separated from the source regions by an element-separating
insulation film, or the gate electrode extends as far as the
boundaries between the back gate regions and the source regions,
and the source regions and the back gate regions are connected
using upper-layer wirings. However, when connection of the source
regions to the back gate regions is assumed, there is no need to
divide the source regions and the back gate regions into separate
regions using the element-separating insulation film. In the case
of the field effect transistor of the present embodiment, the
source regions and the back gate regions are provided next to each
other without separating them using an element-separating
insulation film.
[0042] Shown in FIG. 6(A) is a partial cross sectional view of a
field effect transistor according to a further embodiment of the
instant invention. As shown in FIG. 3(A), gate electrodes 21 are
formed in a grid pattern, n.sup.+-type source regions 18S and drain
regions 18D are formed in the inner regions of the respective grids
alternately and repeatedly, and source regions 18S are provided at
the outermost circumference.
[0043] As shown in FIG. 6(A), p.sup.+-type back gate regions 18BG
are provided adjacent to source regions 18S provided at the outmost
circumference without separating them using an element-separating
insulation film. In this case, contacts common to respective source
regions 18S and back gate regions 18BG can be used to connect them
to an upper-layer wiring. Source regions 18S and back gate regions
18BG provided adjacent to each other without an element-separating
insulation film as in the aforementioned manner can be formed by
providing a mask opening part for implanting an n-type impurity to
form source regions 18S and a mask opening part for injecting an
p-type impurity substance so as to form back gate regions 18BG
adjacent to each other, that is, by injecting impurity substances
into adjoining regions.
[0044] Shown in FIG. 6(B) is a partial cross sectional view of
another example of a field effect transistor according to a further
embodiment of the instant invention. As shown in the Figure, in a
configuration in which n.sup.+-type source regions 18S and drain
regions 18D are repeated alternately, p.sup.+-type back gate
regions 18BG are provided adjacent to regions further inside source
regions 18S without separation using an element-separating
insulation film with respect to source regions 18S in regions
sandwiched by drain regions 18D. Similarly, source regions 18S and
back gate regions 18BG may be connected using common contacts
common to them, and said structure can be formed by implanting
respective impurity substances into adjoining regions. The
configuration of the present embodiment can be applied to the
aforementioned respective embodiments. Furthermore, because the
back gate regions for establishing connections to the back gates
can be laid out adjacent to the source regions, the element area of
the structure is reduced.
[0045] FIG. 7 is a circuit diagram of a circuit for protecting a
magnetic head against electrostatic breakdown (ESD) and is used for
a magnetic head, such as a GMR magnetic head, incorporated into a
magnetic recording device. The field effect transistors in the
aforementioned respective embodiments can be used as a switch
element of the protective circuit. For example, magnetic head 30,
such as a GMR magnetic head, is connected to preamplifier 32 via
line 31a and line 31b. Here, field effect transistors 33 and 34 are
connected to line 31a and line 31b, respectively, to serve as ESD
protection circuits. The ESD protection circuits are configured
using the aforementioned depletion type n-channel field effect
transistors with the aforementioned respective embodiments, their
drain regions are connected to lines 31a and 31b, and their source
regions are connected to a reference potential (for example,
ground).
[0046] Because the ESD protection circuits become conductive when
an excessive voltage is applied to lines 31a and 31b so as to
release said excessive voltage to the reference potential, a
negative potential is applied to gate terminals 33a and 34a of the
depletion type field effect transistors 33 and 34 to keep
transistors 33 and 34 non-conductive while under the steady state.
A bias current is supplied to magnetic head 30 through a path
comprising a positive-side power supply, line 31a, magnetic head
30, line 31b, and a negative-side power supply. At this time, the
voltage of the positive-side power supply is +3V to +5V, and the
voltage of the negative-side power supply is -2V to -5V. In this
case, gate electrodes 33a and 34a of field effect transistors 33
and 34 may be connected to the negative-side power supply. In
addition, a voltage difference of roughly 100 mV is created between
line 31a and line 31b, that is, across the two ends of magnetic
head 30.
[0047] While preamplifier 32 and field effect transistors 33 and 34
can be formed on a single semiconductor integrated circuit (IC),
magnetic head 30 is attached to said semiconductor integrated
circuit externally.
[0048] The present invention is not restricted to the explanation
given above. For example, a silicide layer may be formed partially
or entirely over the surfaces of the source regions, the drain
regions, the back gate regions, and the gate electrode. For
example, it can be formed over the entire surfaces of the source
regions, the drain regions, the back gate regions, and the gate
electrode by means of siliciding process. Although depletion type
field effect transistors were explained in the aforementioned
embodiments, application to an enhancement type by not forming a
channel region is also possible. In addition, although an n-channel
depletion mode field effect transistor was explained, application
to a p-channel depletion mode field effect transistor is also
possible by simply reversing the n-type and p-type regions of the
structures shown in the Figures.
* * * * *