U.S. patent application number 12/273272 was filed with the patent office on 2009-03-19 for semiconductor device having high voltage mos transistor and fabrication method thereof.
This patent application is currently assigned to Dongbu Hitek Co., Ltd.. Invention is credited to Yong Keon CHOI.
Application Number | 20090072299 12/273272 |
Document ID | / |
Family ID | 36641058 |
Filed Date | 2009-03-19 |
United States Patent
Application |
20090072299 |
Kind Code |
A1 |
CHOI; Yong Keon |
March 19, 2009 |
SEMICONDUCTOR DEVICE HAVING HIGH VOLTAGE MOS TRANSISTOR AND
FABRICATION METHOD THEREOF
Abstract
A semiconductor device having a high voltage MOS transistor. The
device includes a gate oxide layer disposed between a gate
electrode and a substrate on an active area and having relatively
thick portions at edges thereof. A fabrication method includes
forming on the substrate is a nitride layer having an opening in a
high voltage region. An oxide layer is deposited over the substrate
and anisotropically etched to remain only on sidewalls of the
opening. A first gate oxide layer is formed on the substrate in the
opening, and the nitride layer is removed. Then a second gate oxide
layer is formed over the substrate such that the second gate oxide
layer has a relatively thinner thickness than the first gate oxide
layer. Gate electrodes are then formed in the high voltage region
and the low voltage region.
Inventors: |
CHOI; Yong Keon;
(Gyeonggi-do, KR) |
Correspondence
Address: |
LOWE HAUPTMAN HAM & BERNER, LLP
1700 DIAGONAL ROAD, SUITE 300
ALEXANDRIA
VA
22314
US
|
Assignee: |
Dongbu Hitek Co., Ltd.
Seoul
KR
|
Family ID: |
36641058 |
Appl. No.: |
12/273272 |
Filed: |
November 18, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11320859 |
Dec 30, 2005 |
7468300 |
|
|
12273272 |
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Current U.S.
Class: |
257/327 ;
257/E29.242 |
Current CPC
Class: |
Y10S 438/981 20130101;
H01L 29/7833 20130101; H01L 29/66553 20130101; H01L 29/42368
20130101; H01L 29/66659 20130101 |
Class at
Publication: |
257/327 ;
257/E29.242 |
International
Class: |
H01L 29/786 20060101
H01L029/786 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 31, 2004 |
KR |
10-2004-0117677 |
Claims
1-3. (canceled)
4. A semiconductor device comprising: a semiconductor substrate
having a field area defining an active area; a gate electrode
disposed on the active area of the substrate; a gate oxide layer
disposed between the gate electrode and the substrate on the active
area, having relatively thick portions at edges thereof; and a
source/drain formed around the gate electrode in the active area of
the substrate.
5. The device of claim 4, further comprising: a drift area formed
in the substrate to surround the source/drain.
6. The device of claim 4, wherein the gate oxide layer has a
thickness of 500.about.1500 .ANG..
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This U.S. non-provisional application claims priority under
35 U.S.C. .sctn.119 from Korean Patent Application No. 2004-117677,
which was filed in the Korean Intellectual Property Office on Dec.
31, 2004, the contents of which are incorporated by reference
herein in its entirety.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates generally to semiconductor
integrated circuit (IC) technology and, more particularly, to a
semiconductor device having a high voltage MOS transistor allowing
an increase in breakdown and fabricated with a more simple
process.
[0004] 2. Description of the Related Art
[0005] Dramatically growing semiconductor IC technology allows a
variety of devices, such as transistors, capacitors and resistors,
to be integrated in a single chip. Furthermore, various approaches
to effectively embody such devices in the chip have been
continuously studied and introduced in the art.
[0006] For example, modern silicon device technology attempts to
combine logic technology represented by a CPU (central processing
unit) for data processing and memory technology for data storing.
Furthermore, such attempts intend to combine analog technology and
RF technology together with logic and memory technologies.
[0007] In general, a transistor holds an important position common
to logic and memory technologies. However, logic technology
considers current drivability, whereas memory technology does
reduced leakage current and improved breakdown voltage. Hence, it
is required to effectively embody MOS (metal oxide semiconductor)
transistors with different gate dielectrics in thickness on a
single chip.
[0008] FIGS. 1 to 4 are cross-sectional views showing a method of
fabricating a conventional semiconductor device having a high
voltage MOS transistor. In the drawings, a reference character "A"
indicates a region where a high voltage MOS transistor is formed.
Hereinafter, this region will be referred to as a high voltage
region. Similarly, a reference character "B" indicates a region
where a low voltage MOS transistor is formed and which will be
referred to as a low voltage region.
[0009] Referring to FIG. 1, a field area 3 is formed in a
semiconductor substrate 1, defining an active area. In most cases,
the substrate 1 is selectively etched to form a trench for the
field area 3. Suitable insulating material is deposited to fill the
trench and then planarized.
[0010] Next, gate oxide layers are formed on the substrate 1. That
is, a relatively thick first gate oxide layer 5 is formed in the
high voltage region (A), and a relatively thin second gate oxide
layer 7 is formed in the low voltage region (B). Well-known various
techniques may be used for forming the gate oxide layers 5 and 7
with different thickness. For example, a nitride layer is formed on
the entire substrate 1 and removed from the high voltage region (A)
by using typical photo etching process. Then the thick gate oxide
layer 5 is thermally grown in the high voltage region. The
remaining nitride layer is removed from the low voltage region (B),
and the thin gate oxide layer 7 is thermally grown in the low
voltage region.
[0011] Subsequently, a gate conductive layer 9, 11 is formed on the
gate oxide layer 5, 7, and a first photoresist pattern 13 is formed
thereon by using typical photo process. The first photoresist
pattern 13 selectively exposes the high voltage region (A), fully
covering the low voltage region (B).
[0012] Next, referring to FIG. 2, the gate conductive layer 9 in
the high voltage region (A) is selectively etched until the first
gate oxide layer 5 is exposed. Here, the first photoresist pattern
13 is used as an etch mask. As a result, a first gate electrode 9a
is formed in the high voltage region (A).
[0013] Next, referring to FIG. 3, the first gate oxide layer 5 is
selectively etched using the first photoresist pattern 13 as an
etch mask. Here, the first gate oxide layer 5 may partially remain
after etching. As a result, the first gate oxide layer 5 is
composed of an unetched portion 5a under the first gate electrode
9a and a partially etched portion 5b remaining on the substrate 1.
The remaining gate oxide layer 5b may act as a buffer layer during
the subsequent ion implanting process. A low doping part 14 of a
source/drain is formed in the substrate 1 through a shallow ion
implantation.
[0014] Next, referring to FIG. 4, the first photoresist pattern 13
is removed, and a second photoresist pattern 15 is formed instead.
The second photoresist pattern 15 selectively exposes the low
voltage region (B), fully covering the high voltage region (A).
Then, the gate conductive layer 11 is selectively etched using the
second photoresist pattern 15 as an etch mask, so a second gate
electrode 11a is formed in the low voltage region (B).
[0015] Thereafter, spacers are formed on sidewalls of the gate
electrodes 9a and 11a, and a high doping part of the source/drain
is formed in the substrate 1.
[0016] FIG. 5 shows, in a cross-sectional view, a conventional MOS
transistor in the high voltage region.
[0017] Referring to FIG. 5, the spacer 17 is formed on the sidewall
of the gate electrode 9a, and the source/drain 21 is formed in the
substrate 1. The source/drain 21 has the low doping part 14 and the
high doping part 19.
[0018] As discussed hereinbefore, to fabricate MOS transistors in
both the high and low voltage regions requires additional processes
such as partial removal of the first gate oxide layer 5 in the high
voltage region (A). Furthermore, undesirable breakdown may occur in
a place 25 between the gate electrode 9a and the drain 21 due to
high electric field applied thereto.
SUMMARY OF THE INVENTION
[0019] Exemplary, non-limiting embodiments of the present invention
provide a semiconductor device having a high voltage MOS transistor
allowing an increase in breakdown, and also provide a related
fabrication method with a more simple process.
[0020] According to one exemplary embodiment of the present
invention, the method comprises forming a field area in a
semiconductor substrate so as to define an active area in a high
voltage region and a low voltage region, forming a nitride layer on
the substrate, the nitride layer having an opening in the high
voltage region, depositing an oxide layer over the substrate,
anisotropically etching the oxide layer such that the oxide layer
remains only on sidewalls of the opening, forming a first gate
oxide layer on the substrate in the opening, removing the nitride
layer, forming a second gate oxide layer over the substrate such
that the second gate oxide layer has a relatively thinner thickness
than the first gate oxide layer, forming gate electrodes in the
high voltage region and the low voltage region, and forming
source/drain around the gate electrodes in the active area of the
substrate.
[0021] In the method, the first gate oxide layer can have a
thickness of 500.about.1500 .ANG. and the second gate oxide layer
can have a thickness of 50.about.300 .ANG.. The method can further
comprise, after the forming of the field area, forming a drift area
in the substrate of the high voltage region.
[0022] According to one exemplary embodiment of the present
invention, the semiconductor device comprises a semiconductor
substrate having a field area defining an active area, a gate
electrode disposed on the active area of the substrate, a gate
oxide layer disposed between the gate electrode and the substrate
on the active area, having relatively thick portions at edges
thereof, and a source/drain formed around the gate electrode in the
active area of the substrate.
[0023] The device can further comprise a drift area formed in the
substrate to surround the source/drain. In the device, the gate
oxide layer can have a thickness of 500.about.1500 .ANG..
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIGS. 1 to 4 are cross-sectional views showing a method of
fabricating a conventional semiconductor device having a high
voltage MOS transistor.
[0025] FIG. 5 is a cross-sectional view showing a conventional MOS
transistor in a high voltage region.
[0026] FIG. 6 is a cross-sectional view showing a MOS transistor in
a high voltage region in accordance with an exemplary embodiment of
the present invention.
[0027] FIGS. 7 to 11 are cross-sectional views showing a method of
fabricating a semiconductor device having a high voltage MOS
transistor in accordance with an exemplary embodiment of the
present invention.
DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION
[0028] An exemplary, non-limiting embodiment of the present
invention will now be described more fully hereinafter with
reference to the accompanying drawings. This invention may,
however, be embodied in many different forms and should not be
construed as limited to the exemplary embodiment set forth herein.
Rather, the disclosed embodiment is provided so that this
disclosure will be thorough and complete, and will fully disclose
the invention to those skilled in the art. The principles and
features of this invention may be employed in varied and numerous
embodiments without departing from the scope of the invention.
[0029] In is noted that well-known structures and processes are not
described or illustrated in detail to avoid obscuring the essence
of the present invention. It is also noted that the figures are not
drawn to scale.
[0030] FIG. 6 is a cross-sectional view showing a MOS transistor in
a high voltage region in accordance with an exemplary embodiment of
the present invention.
[0031] Referring to FIG. 6, a field area 103 is formed in a
semiconductor substrate 101, defining an active area. A gate oxide
layer 111 and a gate electrode 115a are disposed in a stack on the
active area of the substrate 101, and a source/drain 117a is formed
around the gate electrode 115a in the active area of the substrate
101. The source/drain 117a is surrounded with a drift area 105 in
the substrate 101. The gate oxide layer 111 has relatively thick
portions 109a at edges thereof. These thick portions 109a allow an
increase in breakdown between the gate electrode 115a and the drain
117a.
[0032] FIGS. 7 to 11 are cross-sectional views showing a method of
fabricating a semiconductor device having a high voltage MOS
transistor in accordance with an exemplary embodiment of the
present invention. Like previous drawings, reference characters "A"
and "B" indicate a high voltage region and a low voltage region,
respectively.
[0033] Referring to FIG. 7, after a well (not shown) is formed in
the substrate 101, the field area 103 is formed in the substrate
101. For example, to form the field area 103, a trench is formed in
the substrate 101 by selective etching and filled with suitable
insulating material deposited thereon. Then, the insulating
material is planarized. While the field area 103 is formed, a thin
first oxide layer 104 is simultaneously formed on the substrate
101. Next, the drift area 105 is formed in the substrate 101 of the
high voltage region (A).
[0034] Next, referring to FIG. 8, a nitride layer 107 is formed on
the substrate 101 and selectively etched to form an opening 108 for
the gate electrode in the high voltage region (A).
[0035] Next, referring to FIG. 9, a second oxide layer is fully
deposited over the substrate 101 and anisotropically etched until
the nitride layer 107 is exposed. Hence, the aforementioned thick
portions 109a of the gate oxide layer are formed in the shape of
spacers on sidewalls of the opening 108.
[0036] Next, referring to FIG. 10, the substrate 101 is subjected
to thermal oxidation, and thereby the first gate oxide layer 111 is
formed on the substrate 101 in the opening 108. For example, the
first gate oxide layer 111 can be formed at a thickness of
500.about.1500 .ANG.. Thereafter, the nitride layer 107 and the
first oxide layer 104 are completely removed.
[0037] Next, referring to FIG. 11, a second gate oxide layer 113
and a gate conductive layer are sequentially formed over the
substrate 101. The second gate oxide layer 113 has a relatively
thinner thickness, for example, 50.about.300 .ANG., in comparison
with the first gate oxide layer 111. Then, the gate conductive
layer is selectively etched, so the gate electrodes 115a and 115b
are respectively formed in the high voltage region (A) and the low
voltage region (B).
[0038] Next, by using typical technique, the source/drain 117a and
117b are formed around the gate electrodes 115a and 115b in the
active area of the substrate 101.
[0039] As discussed above, the thick portions of the first gate
electrode in the high voltage region allow an increase in breakdown
between the gate electrode and the drain. Additionally, the method
of the invention becomes simpler since it does not require a
process of partially removing a gate oxide layer, for a shallow ion
implantation, in the high voltage region.
[0040] While this invention has been particularly shown and
described with reference to an exemplary embodiment thereof, it
will be understood by those skilled in the art that various changes
in form and details may be made therein without departing from the
spirit and scope of the invention as defined by the appended
claims.
* * * * *