U.S. patent application number 11/898384 was filed with the patent office on 2009-03-12 for charge pump device and operating method thereof.
Invention is credited to Hsin Chang Lin, Cheng Ying Wu.
Application Number | 20090066406 11/898384 |
Document ID | / |
Family ID | 40431214 |
Filed Date | 2009-03-12 |
United States Patent
Application |
20090066406 |
Kind Code |
A1 |
Lin; Hsin Chang ; et
al. |
March 12, 2009 |
CHARGE PUMP DEVICE AND OPERATING METHOD THEREOF
Abstract
A charge pump device and an operating method thereof are
proposed. The charge pump device is composed of a plurality of
stages of charge transfer units and an output unit that are
cascaded together. Each stage of the charge transfer units includes
a first node for input, a second node for output, a first circuit
and a first capacitor. The first node or the second node is biased
at a bias provided for the first circuit. Thereby, the first
capacitors of the odd-numbered stage and the even-numbered stage of
charge transfer units can respectively receive two clock signals
that are mutually opposite in phase for complementary switching
operating. Collocated with the switching of the output unit, an
output voltage with a high negative level can be generated.
Inventors: |
Lin; Hsin Chang; (Chu-pei
City, TW) ; Wu; Cheng Ying; (Chu-pei City,
TW) |
Correspondence
Address: |
ROSENBERG, KLEIN & LEE
3458 ELLICOTT CENTER DRIVE-SUITE 101
ELLICOTT CITY
MD
21043
US
|
Family ID: |
40431214 |
Appl. No.: |
11/898384 |
Filed: |
September 12, 2007 |
Current U.S.
Class: |
327/536 |
Current CPC
Class: |
H02M 3/073 20130101;
H02M 2003/078 20130101 |
Class at
Publication: |
327/536 |
International
Class: |
G05F 3/02 20060101
G05F003/02 |
Claims
1. A charge pump device comprising: an input node connected to a
voltage source; an output node for providing an output voltage; a
clock control unit for providing a first clock signal and a second
clock signal that are mutually opposite in phase; at least two
cascaded stages of charge transfer units each comprising a first
node, a second node, a first circuit connected between said first
and second nodes, a first capacitor, said first capacitor being
connected to said second node and said clock control unit, said
first node of the first stage of said charge transfer units being
connected to said input node, said first node and said second node
of another stage of said charge transfer units being connected to
said second node and said first circuit of the previous stage of
said charge transfer units, respectively; and an output unit
comprising a third node, a second circuit and a second capacitor
connected to said clock control unit, said third node being
connected to said second node of the last stage of said charge
transfer units, said second circuit being connected to said third
node, said output node, said second capacitor, and said first
circuit of the last stage of said charge transfer units; wherein
said first circuit comprises a fourth node, a fifth node, a first
transistor, a second transistor, a third transistor and a fourth
transistor, substrates of said first transistor, said second
transistor and said third transistor are connected to said first
node, said fifth node is connected to the substrate of said fourth
transistor and said second node of the next stage of said charge
transfer units, said second circuit comprises a sixth node, a
seventh node, a fifth transistor, a sixth transistor, a seventh
transistor and an eighth transistor, substrates of said fifth
transistor, said sixth transistor and said seventh transistor are
connected to said seventh node, the substrate of said eighth
transistor is connected to said output node, said sixth node is
connected to said eighth transistor, said second capacitor and said
fifth node of the last stage of said charge transfer units.
2. The charge pump device as claimed in claim 1, wherein the
voltage level of said voltage source is ground.
3. (canceled)
4. The charge pump device as claimed in claim 1, wherein said first
transistor, said second transistor, said third transistor, said
fifth transistor, said sixth transistor and said seventh transistor
are PMOS transistors, and said fourth transistor and said eighth
transistor are NMOS transistors.
5. The charge pump device as claimed in claim 1, wherein a drain
and a gate of said first transistor, a drain of said second
transistor and a source of said third transistor are connected to
said first node, a source of said first transistor, a source of
said second transistor, a gate of said third transistor and a gate
of said fourth transistor are connected to said second node, a gate
of said second transistor, a drain of said third transistor and a
drain of said fourth transistor are connected to said fourth node,
a source of said fourth transistor is connected to said fifth node
in said first circuit, a source of said fifth transistor, a gate of
said sixth transistor, a drain and a gate of said seventh
transistor and a source of said eighth transistor are connected to
said third node, a gate of said fifth transistor, a source of said
sixth transistor, a source of said seventh transistor and a gate of
said eighth transistor are connected to said sixth node, and a
drain of said fifth transistor and a drain of said sixth transistor
are connected to said seventh node in said second circuit.
6. The charge pump device as claimed in claim 5, wherein said first
transistor, said second transistor, said third transistor, said
fifth transistor, said sixth transistor and said seventh transistor
are PMOS transistors, and said fourth transistor and said eighth
transistor are NMOS transistors.
7. A charge pump device comprising: an input node connected to a
voltage source; an output node for providing an output voltage; a
clock control unit for providing a first clock signal and a second
clock signal that are mutually opposite in phase; at least two
cascaded stages of charge transfer units each comprising a first
node, a second node, a first circuit connected between said first
and second nodes, and a first capacitor, said first capacitor being
connected to said second node and said clock control unit, said
first node of the first stage of said charge transfer units being
connected to said input node, said first node and said second node
of another stage of said charge transfer units being connected to
said second node and said first circuit of the previous stage of
said charge transfer units, respectively; and an output unit
comprising a third node, a second circuit and a second capacitor
connected to said clock control unit, said third node being
connected to said second node of the last stage of said charge
transfer units, said second circuit being connected to said third
node, said output node, said second capacitor, and said first
circuit of the last stage of said charge transfer units; wherein
said first circuit comprises a fourth node, a fifth node, an eighth
node, a first transistor, a second transistor, a third transistor,
a fourth transistor and a first well bias circuit, said first well
bias circuit comprises a ninth transistor and a tenth transistor
and used to provide a first bias for said eighth node, substrates
of said first transistor, said second transistor and said third
transistor are connected to said eighth node, said fifth node is
connected to a substrate of said fourth transistor and said second
node of the next stage of said charge transfer units, said second
circuit comprises a sixth node, a seventh node, a second well bias
circuit, a seventh transistor and an eighth transistor, said second
well bias circuit comprises a fifth transistor and a sixth
transistor and used to provide a second bias for said seventh
transistor, substrates of said fifth transistor, said sixth
transistor and said seventh transistor are connected to said
seventh node, a substrate of said eighth transistor is connected to
said output node, said sixth node is connected to said eighth
transistor, said second capacitor and said fifth node of the last
stage of said charge transfer units.
8. The charge pump device as claimed in claim 7, wherein said first
transistor, said second transistor, said third transistor, said
fifth transistor, said sixth transistor, said seventh transistor,
said ninth transistor and said tenth transistor are PMOS
transistors, and said fourth transistor and said eighth transistor
are NMOS transistors.
9. The charge pump device as claimed in claim 7, wherein, in said
first circuit, a drain and a gate of said first transistor, a drain
of said second transistor, a source of said third transistor, a
source of said ninth transistor and a gate of said tenth transistor
are connected to said first node, a source of said first
transistor, a source of said second transistor, a gate of said
third transistor, a gate of said fourth transistor, a gate of said
ninth transistor and a source of said tenth transistor are
connected to said second node, a gate of said second transistor, a
drain of said third transistor and a drain of said fourth
transistor are connected to said fourth node, a source of said
fourth transistor is connected to said fifth node, a drain and a
substrate of said ninth transistor and a drain and a substrate of
said tenth transistor are connected to said eighth node; in said
second circuit, a source of said fifth transistor, a gate of said
sixth transistor, a drain and a gate of said seventh transistor and
a source of said eighth transistor are connected to said third
node, a gate of said fifth transistor, a source of said sixth
transistor, a source of said seventh transistor and a gate of said
eighth transistor are connected to said sixth node, and a drain of
said fifth transistor and a drain of said sixth transistor are
connected to said seventh node.
10. The charge pump device as claimed in claim 9, wherein said
first transistor, said second transistor, said third transistor,
said fifth transistor, said sixth transistor, said seventh
transistor, said ninth transistor and said tenth transistor are
PMOS transistors, and said fourth transistor and said eighth
transistor are NMOS transistors.
11. An operating method for a charge pump device comprising the
steps of: (a) establishing a charge pump device comprising: an
input node connected to a voltage source; an output node for
providing an output voltage; a clock control unit for providing a
first clock signal and a second clock signal that are mutually
opposite in phase; at least two cascaded stages of charge transfer
units each comprising a first node, a second node, a first circuit
connected between said first and second nodes, a first capacitor,
said first capacitor being connected to said second node and said
clock control unit, said first node of the first stage of said
charge transfer units being connected to said input node, said
first node and said second node of another stage of said charge
transfer units being connected to said second node and said first
circuit of the previous stage of said charge transfer units,
respectively; and an output unit comprising a third node, a second
circuit and a second capacitor connected to said clock control
unit, said third node being connected to said second node of the
last stage of said charge transfer units, said second circuit being
connected to said third node, said output node, said second
capacitor, and said first circuit of the last stage of said charge
transfer units; (b) generating said first clock signal and said
second clock signal both of which have an amplitude of voltage
level of V.sub.DD; (c) applying said first clock signal to said
first capacitor of the odd-numbered stage of said charge transfer
units and said second capacitor of said output unit and applying
said second clock signal to said first capacitor of the
even-numbered stage of said charge transfer units at the same time;
(d) enabling the odd-numbered stage of said charge transfer units
and said output unit and disabling the even-numbered stage of said
charge transfer units in a first mode so that the odd-numbered
stage of said charge transfer units can completely transfer charges
from the next stage (even-numbered stage) of said charge transfer
units and said output unit can completely transfer charges from
said output node with the even-numbered stage of said charge
transfer units not transferring charges; (e) enabling the
even-numbered stage of said charge transfer units and disabling the
odd-numbered stage of said charge transfer units and said output
unit in a second mode so that the even-numbered stage of said
charge transfer units can completely transfer charges from the next
stage (odd-numbered stage) of said charge transfer units with the
odd-numbered stage of said charge transfer units not transferring
charges; and (f) repeating said step (d) to said step (e) until
said output node finally generates said output voltage with a
maximum level up to -N.times.V.sub.DD.
12. An operating method for the charge pump device comprising the
steps of: (a) establishing a charge pump device comprising: an
input node connected to a voltage source; an output node for
providing an output voltage; a clock control unit for providing a
first clock signal and a second clock signal that are mutually
opposite in phase; at least two cascaded stages of charge transfer
units each comprising a first node, a second node, a first circuit
connected between said first and second nodes, a first capacitor,
said first capacitor being connected to said second node and said
clock control unit, said first node of the first stage of said
charge transfer units being connected to said input node, said
first node and said second node of another stage of said charge
transfer units being connected to said second node and said first
circuit of the previous stage of said charge transfer units,
respectively; and an output unit comprising a third node, a second
circuit and a second capacitor connected to said clock control
unit, said third node being connected to said second node of the
last stage of said charge transfer units, said second circuit being
connected to said third node, said output node, said second
capacitor, and said first circuit of the last stage of said charge
transfer units; wherein said first circuit comprises a fourth node,
a fifth node, a first transistor, a second transistor, a third
transistor and a fourth transistor, substrates of said first
transistor, said second transistor and said third transistor are
connected to said first node, said fifth node is connected to the
substrate of said fourth transistor and said second node of the
next stage of said charge transfer units, said second circuit
comprises a sixth node, a seventh node, a fifth transistor, a sixth
transistor, a seventh transistor and an eighth transistor,
substrates of said fifth transistor, said sixth transistor and said
seventh transistor are connected to said seventh node, the
substrate of said eighth transistor is connected to said output
node, said sixth node is connected to said eighth transistor, said
second capacitor and said fifth node of the last stage of said
charge transfer units; (b) generating said first clock signal and
said second clock signal both of which have an amplitude of voltage
level of V.sub.DD; (c) applying said first clock signal to the
odd-numbered stage of said charge transfer units and said output
unit and applying said second clock signal to the even-numbered
stage of said charge transfer units at the same time; (d) enabling
said first transistor, said second transistor and said fourth
transistor of the odd-numbered stage of said charge transfer units
and said sixth transistor, said seventh transistor and said eighth
transistor of said output unit and disabling said first transistor,
said second transistor and said fourth transistor of the
even-numbered stage of said charge transfer units in a first mode
so that the odd-numbered stage of said charge transfer units can
completely transfer charges from the next stage (even-number-stage)
of said charge transfer units and said output unit can completely
transfer charges from said output node with the even-numbered stage
of said charge transfer units not transferring charges; (e)
enabling said first transistor, said second transistor and said
fourth transistor of the even-numbered stage of said charge
transfer units and disabling said first transistor, said second
transistor and said fourth transistor of the odd-numbered stage of
said charge transfer units and said eighth transistor, said ninth
transistor and said tenth transistor of said output unit in a
second mode so that the even-numbered stage of said charge transfer
units can completely transfer charges from the next stage
(odd-numbered stage) of said charge transfer units with the
odd-numbered stage of said charge transfer units not transferring
charges; and (f) repeating said step (d) to said step (e) until
said output node finally generates said output voltage with a
maximum level up to -N.times.V.sub.DD.
13. An operating method for the charge pump device comprising the
steps of: (a) establishing a charge pump device comprising: an
input node connected to a voltage source; an output node for
providing an output voltage; a clock control unit for providing a
first clock signal and a second clock signal that are mutually
opposite in phase; at least two cascaded stages of charge transfer
units each comprising a first node, a second node, a first circuit
connected between said first and second nodes, and a first
capacitor, said first capacitor being connected to said second node
and said clock control unit, said first node of the first stage of
said charge transfer units being connected to said input node, said
first node and said second node of another stage of said charge
transfer units being connected to said second node and said first
circuit of the previous stage of said charge transfer units,
respectively; and an output unit comprising a third node, a second
circuit and a second capacitor connected to said clock control
unit, said third node being connected to said second node of the
last stage of said charge transfer units, said second circuit being
connected to said third node, said output node, said second
capacitor, and said first circuit of the last stage of said charge
transfer units; wherein said first circuit comprises a fourth node,
a fifth node, an eighth node, a first transistor, a second
transistor, a third transistor, a fourth transistor and a first
well bias circuit, said first well bias circuit comprises a ninth
transistor and a tenth transistor and used to provide a first bias
for said eighth node, substrates of said first transistor, said
second transistor and said third transistor are connected to said
eighth node, said fifth node is connected to a substrate of said
fourth transistor and said second node of the next stage of said
charge transfer units, said second circuit comprises a sixth node,
a seventh node, a second well bias circuit, a seventh transistor
and an eighth transistor, said second well bias circuit comprises a
fifth transistor and a sixth transistor and used to provide a
second bias for said seventh transistor, substrates of said fifth
transistor, said sixth transistor and said seventh transistor are
connected to said seventh node, a substrate of said eighth
transistor is connected to said output node, said sixth node is
connected to said eighth transistor, said second capacitor and said
fifth node of the last stage of said charge transfer units; (b)
generating said first clock signal and said second clock signal
both of which have an amplitude of voltage level of V.sub.DD; (c)
applying said first clock signal to the odd-numbered stage of said
charge transfer units and said output unit and applying said second
clock signal to the even-numbered stage of said charge transfer
units at the same time; (d) enabling said first transistor, said
second transistor, said fourth transistor and said tenth transistor
of the odd-numbered stage of said charge transfer units and said
sixth transistor, said seventh transistor and said eighth
transistor of said output unit and disabling said first transistor,
said second transistor, said fourth transistor and said tenth
transistor of the even-numbered stage of said charge transfer units
in a first mode so that the odd-numbered stage of said charge
transfer units can completely transfer charges from the next stage
(even-numbered stage) of said charge transfer units and said output
unit can completely transfer charges from said output node with the
even-numbered stage of said charge transfer units not transferring
charges; (e) enabling said first transistor, said second transistor
and said fourth transistor of the even-numbered stage of said
charge transfer units and disabling said first transistor, said
second transistor and said fourth transistor of the odd-numbered
stage of said charge transfer units and said eighth transistor,
said ninth transistor and said tenth transistor of said output unit
in a second mode so that the even-numbered stage of said charge
transfer units can completely transfer charges from the next stage
(odd-numbered-stage) of said charge transfer units with the
odd-numbered stage of said charge transfer units not transferring
charges; and (f) repeating said step (d) to said step (e) until
said output node finally generates said output voltage with a
maximum level up to -N.times.V.sub.DD.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a charge pump technology
and, more particularly, to a charge pump device capable of
eliminating the body effect and having a high pumping gain and an
operating method thereof.
[0003] 2. Description of Related Art
[0004] Negative voltages are required for general flash memories or
electrically erasable programmable read only memories (EEPROM) to
generate a sufficient relative potential difference for data erase
or data programming function.
[0005] FIG. 1 shows a prior art charge pump device 10, which makes
use of cascaded PMOS transistors to transfer charges in the load
capacitor of the output node. The input node of this charge pump
device 10 is grounded. The drain of each of the PMOS transistors
P0.about.P4 is connected to the gate thereof. The PMOS transistors
are cascaded together in the so-called diode-connected manner. All
the substrates of the PMOS transistors P0.about.P4 are biased at
the voltage level V.sub.DD of the power source. The input node and
the drain of the transistor P0 are connected to the node D1. The
source of the transistor P1 and the drain of the transistor P2 are
connected to the node D2. The source of the transistor P2 and the
drain of the transistor P3 are connected to the node D3. The source
of the transistor P3 and the drain of the transistor P4 are
connected to the node D4. The source of the transistor P4 is
connected to the output node. The nodes D1.about.D4 are connected
to capacitors C1.about.C4 (all of the same capacitance value of C),
respectively.
[0006] Please refer to FIGS. 1(a) and 1(b) at the same time. The
capacitors C1 and C3 are connected to a first clock signal A, and
the capacitors C2 and C4 are connected to a second clock signal B.
The first clock signal A and the second clock signals B are
mutually opposite in phase, and change their signal levels between
the voltage level of the power source and the ground level. When
the voltage level of the first clock signal A is at the voltage
level V.sub.DD of the power source, the voltage levels of the nodes
D1 and D3 are increased by V.sub.C=V.sub.DD.times.C/(CP+C) through
the coupling of the capacitors C1 and C3, where CP is the parasitic
capacitance value of the node D1 or D3. At the same time, the
voltage level of the second clock signal B is at the ground level,
and the voltage levels of the nodes D2 and D4 are decreased by
V.sub.C=V.sub.DD.times.C/(CP+C) through the coupling of the
capacitors C2 and C4, where CP is the parasitic capacitance value
of the node D2 or D4. Because the voltage levels of the nodes D1
and D3 are raised while the voltage levels of the nodes D2 and D4
are lowered, the transistors P0, P2 and P4 are on, and currents
flow from the nodes D1 and D3 and the output node to the input node
(the ground terminal), and the nodes D2 and D4, respectively.
Before the end of the voltage level V.sub.DD of the first clock
signal A, the voltage levels of the nodes D1 and D3 and the output
node will drop because charges in the capacitors C1 and C3 and the
load capacitor Cout are transferred to the ground terminal and the
capacitors C2 and C4, respectively.
[0007] On the contrary, when the voltage level of the first clock
signal A is at the ground level, the voltage levels of the nodes D1
and D3 are decreased by V.sub.C=V.sub.DD.times.C/(CP+C) through the
coupling of the capacitors C1 and C3. At the same time, the voltage
level of the second clock signal B is at voltage level V.sub.DD of
the power source, and the voltage levels of the nodes D2 and D4 are
increased by V.sub.C=V.sub.DD.times.C/(CP+C) through the coupling
of the capacitors C2 and C4. Because the voltage levels of the
nodes D1 and D3 are lowered while the voltage levels of the nodes
D2 and D4 are raised, the transistors P1 and P3 are on, and
currents flow from the nodes D2 and D4 to the nodes D1 and D3,
respectively. Before the end of the ground level of the first clock
signal A, the voltage levels of the nodes D2 and D4 will drop
because charges in the capacitors C2 and C4 and the load capacitor
Cout are transferred to the capacitors C1 and C3, respectively.
Therefore, through the continual interaction to the capacitors
C1.about.C4 by the first clock signal A and the second clock signal
B, the current constantly flows from the output node to the ground
terminal to continually lower the voltage level of the output node,
finally reaching the desired negative voltage.
[0008] The threshold voltages of the PMOS transistors of the above
charge pump device 10 are raised because the potential difference
between the substrate and the source (V.sub.BS=V.sub.DD-V.sub.S,
where V.sub.S is a negative voltage) is affected by the reduced
voltage level of the source. This is the so-called body effect. An
obvious body effect or a raised threshold voltage of a transistor
will reduce the conduction performance (charge transfer efficiency)
of the transistor. Higher threshold voltages of the PMOS
transistors P0.about.P4 in FIG. 1(a) means more PMOS transistors
are cascaded to cause an inferior charge transfer efficiency so as
to be unable to provide an efficient load current. That is, the
generated negative voltage is smaller (closer to the ground level,
0V).
[0009] FIG. 2(a) shows another prior art charge pump device 20.
Reference is made to FIG. 2(b) as well as FIG. 2(a). The charge
pump device 20 makes use of NMOS transistors to transfer charges in
the load capacitor of the output node. The charge pump device 20
differs from the above charge pump device 10 in that the PMOS
transistors P0.about.P4 of the charge pump device 10 are replaced
with NMOS transistors N0.about.N4. The drain of each of the NMOS
transistors N0.about.N4 is connected to the gate thereof. The NMOS
transistors are cascaded together in the so-called diode-connected
manner. The principle of operation of FIG. 2(a) is the same as that
of FIG. 1(a). Therefore, the charge pump device 20 also has an
obvious body effect or raised threshold voltages of transistor,
hence lowering the conduction performance (charge transfer
efficiency) of transistor.
[0010] Accordingly, the present invention aims to propose a charge
pump device and an operating method thereof in order to solve the
above problems in the prior art.
SUMMARY OF THE INVENTION
[0011] The primary object of the present invention is to provide a
charge pump device and an operating method thereof to eliminate the
body effect for providing an output voltage with a high negative
level and also have the advantage of a high pumping gain.
[0012] To achieve the above object, the present invention provides
a charge pump device and an operating method thereof. The charge
pump device comprises several stages of charge transfer units and
an output unit that are cascaded between the input node and the
output node of the charge pump device. Each of the charge transfer
units comprises a first node for input, a second node for output, a
first circuit connected to the first node and the second node, and
a first capacitor connected to the second node. The first node of
the first-stage charge transfer unit is connected to the input
node. The first node and the second node of another stage of charge
transfer units are connected to the second node and the first
circuit of the previous-stage charge transfer unit. The output unit
comprises a third node for input, a second circuit and a second
capacitor connected to the second circuit. The second circuit is
connected to the third node, the output node, the second capacitor,
and the first circuit of the last-stage charge transfer unit.
[0013] Because providing a bias for the first circuit of a charge
transfer unit can enable or disable the charge transfer unit, the
first capacitor can be used to receive two clock signals of the
same amplitude but opposite phases to let odd-numbered-stage and
even-numbered-stage charge transfer units perform complementary
switching operations. That is, odd-numbered-stage charge transfer
units provide the charge transfer function while
even-numbered-stage charge transfer units don't (or vice verse),
and their switching states are alternately changed. Collocated with
the switching operation of the output unit, an output voltage with
a high negative level can finally be generated.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The various objects and advantages of the present invention
will be more readily understood from the following detailed
description when read in conjunction with the appended drawing, in
which:
[0015] FIG. 1(a) is a diagram of a prior art charge pump
device;
[0016] FIG. 1(b) is a diagram of the clock signal applied to the
charge pump device of FIG. 1(a);
[0017] FIG. 2(a) is a diagram of another prior art charge pump
device;
[0018] FIG. 2(b) is a diagram of the clock signal applied to the
charge pump device of FIG. 2(a);
[0019] FIG. 3(a) is a diagram of a charge pump device according to
a first embodiment of the present invention;
[0020] FIG. 3(b) is a diagram of the clock signal applied to the
charge pump device of the first embodiment of the present
invention;
[0021] FIG. 4(a) is a diagram of a charge pump device according to
a second embodiment of the present invention;
[0022] FIG. 4(b) is a diagram of the clock signal applied to the
charge pump device of the second embodiment of the present
invention; and
[0023] FIG. 5 is a cross-sectional view showing how a
P.sup.+/N-well junction diode aids in reducing the on-resistance
and increasing the on-time of the first transistor to improve the
charge transfer efficiency of the charge transfer unit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0024] FIG. 3(a) is a diagram of a charge pump device according to
the first embodiment of the present invention. Please also refer to
FIG. 3(b). A charge pump device 30 is composed of a first-stage
charge transfer unit 31, a second-stage charge transfer unit 32 and
an output unit 33 that are cascaded between an input node Nin and
an output node Nout. In order to get a negative voltage, the
voltage level of the power source connected to the input node Nin
is at the ground level, and the output node is used to provide the
output voltage.
[0025] Each stage of charge transfer units comprises a first node X
(X'), a second node Y (Y'), a first circuit 34 (35) connected
between the two nodes, and a first capacitor C1 (C2) connected to
the second node Y (Y'). The first circuit 34 (35) includes a fourth
node Z (Z'), a fifth node W (W'), an eighth node NW1 (NW2), a first
transistor M30 (M34), a second transistor M31 (M35), a third
transistor M32 (M36), a fourth transistor M33 (M37), and a first
well bias circuit 37 (38). All of the first transistor M31 (M34),
the second transistor M32 (M35), the third transistor M33 (M36) are
PMOS transistors. The fourth transistor M34 (M37) is an NMOS
transistor. The first well bias circuit 37 (38) includes a ninth
transistor Ma (Mc) and a tenth transistor Mc (Md). Both of the
ninth transistor Ma (Mc) and the tenth transistor Mc (Md) are PMOS
transistors. The function of the first well bias circuit 37 (38) is
to provide a bias for the eighth node NW1 (NW2). The drain and gate
of the first transistor M30 (M34) are connected to the first node X
(X'), the source thereof is connected to the second node Y (Y'),
and the substrate thereof is connected to the eighth node NW1
(NW2). The drain of the second transistor M31 (M35) is connected to
the first node X (X'), the gate thereof is connected to the fourth
node Z (Z'), the source thereof is connected to the second node Y
(Y'), and the substrate thereof is connected to the eighth node NW1
(NW2). The drain of the third transistor M32 (M36) is connected to
the fourth node Z (Z'), the gate thereof is connected to the second
node Y (Y'), the source thereof is connected to the first node X
(X'), and the substrate thereof is connected to the eighth node NW1
(NW2). The source and substrate of the fourth transistor M33 (M37)
are connected to the fifth node W (W'), the gate thereof is
connected to the second node Y (Y'), and the drain thereof is
connected to the fourth node Z (Z'). The drain and substrate of the
ninth transistor Ma (Mc) are connected to the eighth node NW1
(NW2), the gate thereof is connected to the second node Y (Y'), and
the source thereof is connected to the first node X (X'). The drain
and substrate of the tenth transistor Mb (Md) are connected to the
eighth node NW1 (NW2), the gate thereof is connected to the first
node X (X'), and the source thereof is connected to the second node
Y (Y'). Moreover, the second node Y' of the second-stage charge
transfer unit 32 is connected to the fifth node W of the
first-stage charge transfer unit 31. Besides, the first capacitors
C1 and C2 are connected to a clock control unit (not shown) to
receive a first clock signal A and a second clock signal B that are
mutually opposite in phase, respectively.
[0026] The output unit 33 comprises a third node P, a second
circuit 36, and a second capacitor C3. The second circuit 36
includes a sixth node Q, a seventh node NW3, a fifth transistor Me,
a sixth transistor Mf, a seventh transistor M39, and an eighth
transistor M38. All of the fifth transistor Me, the sixth
transistor Mf and the seventh transistor M39 are PMOS transistors.
The eighth transistor M38 is an NMOS transistor. A second well bias
circuit 39 is composed of the fifth transistor Me and the sixth
transistor Mf to provide a second bias for the seventh node NW3.
The third node P is connected to the second node Y' of the
second-stage charge transfer unit 32. The drain and substrate of
the fifth transistor Me are connected to the seventh node NW3, the
gate thereof is connected to the sixth node Q, and the source
thereof is connected to the third node P. The drain and substrate
of the sixth transistor Mf are connected to the seventh node NW3,
the gate thereof is connected to the third node P, and the source
thereof is connected to the sixth node Q. The drain and gate of the
seventh transistor M39 are connected to the third node P, the
source thereof is connected to the sixth node Q, and the substrate
thereof is connected to the seventh node NW3. The drain and
substrate of the eighth transistor M38 are connected to the output
node Nout of the charge pump device 30, the gate thereof is
connected to the sixth node Q, and the source thereof is connected
to the sixth node P. The second capacitor C3 is connected to the
sixth node Q and the first clock signal A.
[0027] The actions of each component in the above embodiment at
different times will be illustrated below with reference to FIGS.
3(a) and 3(b).
[0028] Assume the amplitude of voltage level of the first clock
signal A and the second clock signal B is V.sub.DD, the coupling
effect of the first capacitors C1 and C2 and the second capacitor
C3 is 100%. The first clock signal A and the second clock signal B
are used to switch the charge transfer units 31 and 32 and the
output unit 33 between a first mode and a second mode.
[0029] (1) t=0 [0030] At the beginning, the first node X (connected
to the input node Nin) of the first-stage charge transfer unit 31
is grounded, the voltage level of the second node Y of the
first-stage charge transfer unit 31 is V.sub.Y0, the voltage level
of the second node Y' of the second-stage charge transfer unit 32
is equal to that of the third node P of the output unit 33 (both
being V.sub.P0), the voltage level of the sixth node Q of the
output unit 33 is V.sub.Q0, the voltage level of the output node
Nout is V.sub.OUT0.
[0031] (2) t=t.sub.0 (the first mode) [0032] At time t.sub.0, the
first clock signal A rises from the low level to the high level,
while the second clock signal B drops from the high level to the
low level. The increase of the voltage level of the first clock
signal A is V.sub.DD. Through the coupling effect of the first
capacitor C1, the voltage level of the second node Y of the
first-stage charge transfer unit 31 is also increased by V.sub.DD,
i.e., V.sub.Y,t0=V.sub.Y0+V.sub.DD. Similarly, through the coupling
effect of the second capacitor C3, the voltage level of the sixth
node Q of the output unit 33 is also increased by V.sub.DD, i.e.,
V.sub.Q,t0=V.sub.Q0+V.sub.DD. The decrease of the voltage level of
the second clock signal B is V.sub.DD. Through the coupling effect
of the first capacitor C2, the voltage level of the second node Y'
of the second-stage charge transfer unit 32 is also decreased by
V.sub.DD, i.e., V.sub.Y',t0=V.sub.P,t0=V.sub.P0-V.sub.DD. The
actions of the charge transfer units 31 and 32 and the output unit
33 will be illustrated in detail below. [0033] (a) the first-stage
charge transfer unit 31 [0034] In the first well bias circuit 37,
the ninth transistor Ma is off because the relative potential
between the source and gate thereof is lower than the threshold
voltage |V.sub.tp0| of PMOS transistor (i.e.,
V.sub.SG,Ma=V.sub.X,t0-V.sub.Y,t0=0-(V.sub.Y0+V.sub.DD)<|V.sub.tp0|),
the tenth transistor Mb is on because the relative potential
between the source and gate thereof is higher than the threshold
voltage |V.sub.tp0| (i.e.,
V.sub.SG,Mb=V.sub.Y,t0-V.sub.X,t0=V.sub.Y0+V.sub.DD>|V.sub.tp0|-
). Therefore, the voltage level of the eighth node NW1 is equal to
that of the second node Y (i.e., V.sub.NW1=V.sub.Y0+V.sub.DD). In
other words, the first well bias circuit 37 lets the substrates of
all the PMOS transistors (including the first transistor M30, the
second transistor M31, the third transistor M32, the ninth
transistor Ma and the tenth transistor Mb) of the first-stage
charge transfer unit 31 be biased at the second node Y having a
higher voltage level in the first-stage charge transfer unit 31.
Because there is no relative potential between the source and gate
of the first transistor M30, the second transistor M31, the third
transistor M32, the ninth transistor Ma and the tenth transistor
Mb, their threshold voltage is equal to |V.sub.tp0|, i.e., the
threshold voltage when there is no body effect. The first
transistor M30 is on because the relative potential between the
source and gate thereof is higher than the threshold voltage
|V.sub.tp0| (i.e.,
V.sub.SG,M30=V.sub.Y,t0-V.sub.X,t0=V.sub.Y0+V.sub.DD>|V.sub.tp0|).
A current flows from the second node Y to the first node X, and
charges are transferred from the first capacitor C1 to the first
node X (i.e., the ground terminal). Before t=t1 (i.e., t=t1_), the
voltage level of the second node Y will be steadily held at
|V.sub.tp0| (i.e., V.sub.Y,t1.sub.--=|V.sub.tp0|). The charge
transfer efficiency of the first transistor M30 is equal to
(V.sub.Y0+V.sub.DD-V.sub.Y,t1.sub.--)/V.sub.DD. If
V.sub.Y,t1.sub.-- can be reduced, the charge transfer efficiency of
the first-stage charge transfer unit 31 can be further improved.
The third transistor M32 is off because the relative potential
between the source and gate thereof is lower than the threshold
voltage |V.sub.tp0| of PMOS transistor (i.e.,
V.sub.SG,M32=V.sub.X,t0-V.sub.Y,t0=0-(V.sub.Y0+V.sub.DD)<|V.sub.tp0|).
The fourth transistor M33 is on because the relative potential
between the gate and source thereof is higher than the threshold
voltage V.sub.tN of NMOS transistor (i.e.,
V.sub.GS,M33=V.sub.Y,t0-V.sub.P,t0=(V.sub.Y0+V.sub.DD)-(V.sub.P0-V.sub.DD-
)=2V.sub.DD+V.sub.Y0-V.sub.P0>V.sub.tN). The voltage level of
the fourth node Z is therefore equal to that of the second node Y'
(i.e., V.sub.Z=V.sub.P0-V.sub.DD=V.sub.G,M31<0V). Because the
voltage level of the gate of the second transistor M31 is lower
than that of the gate of the first transistor M30, the second
transistor M31 has a superior charge transfer efficiency than does
the first transistor M30, and the voltage level of the second node
Y is lower than |V.sub.tp0| and even close to 0V (i.e.,
V.sub.Y,t1.sub.--.apprxeq.0V). Therefore, the second transistor M31
can assist the first transistor M30 in enhancing the charge
transfer efficiency of the first-stage charge transfer unit 31.
[0035] (b) the second-stage charge transfer unit 32 [0036] The
ninth transistor Mc is on because the relative potential between
the source and gate thereof is higher than the threshold voltage of
PMOS transistor |V.sub.tp0| (i.e.,
V.sub.SG,Mc=V.sub.Y,t0-V.sub.P,t0=(V.sub.Y0+V.sub.DD)-(V.sub.P0-V.sub.DD)-
=2V.sub.DD+V.sub.Y0-V.sub.P0>|V.sub.tp0|). The tenth transistor
Md is off because the relative potential between the source and
gate thereof is lower than the threshold voltage |V.sub.tp0| (i.e.,
V.sub.SG,Md=V.sub.P,t0-V.sub.Y,t0=(V.sub.P0-V.sub.DD)-(V.sub.Y0+V.sub.DD)-
=V.sub.P0-V.sub.Y0-2V.sub.DD<|V.sub.tp0|). The voltage level of
the eighth node NW2 is therefore equal to that of the second node
X'(i.e., V.sub.NW2=V.sub.Y'0+V.sub.DD). In other words, the first
well bias circuit 38 lets the substrates of all the PMOS
transistors (including the first transistor M34, the second
transistor M35, the third transistor M36, the ninth transistor Mc
and the tenth transistor Md) of the second-stage charge transfer
unit 32 be biased at the second node X' having a higher voltage
level in the second-stage charge transfer unit 32. Because there is
no relative potential between the source and gate of the first
transistor M34, the second transistor M35, the third transistor
M36, the ninth transistor Mc and the tenth transistor Md, their
threshold voltage is equal to |V.sub.tp0|, i.e., the threshold
voltage when there is no body effect. The first transistor M34 is
off because the relative potential between the source and gate
thereof is lower than the threshold voltage |V.sub.tp0| (i.e.,
V.sub.SG,M34=V.sub.P,t0-V.sub.Y,t0=(V.sub.P0-V.sub.DD)-(V.sub.Y0+V.sub.DD-
)=V.sub.P0-V.sub.Y0-2V.sub.DD<|V.sub.tp0|). The third transistor
M36 is on because the relative potential between the source and
gate thereof is higher than the threshold voltage |V.sub.tp0|
(i.e.,
V.sub.SG,M36=V.sub.Y,t0-V.sub.P,t0-V.sub.P,t0=(V.sub.Y0+V.sub.DD)-(V.sub.-
P0-V.sub.DD)=2V.sub.DD+V.sub.Y0-V.sub.P0>|V.sub.tp0|). The
fourth transistor M37 is off because the relative potential between
the gate and source thereof is lower than the threshold voltage of
NMOS transistor V.sub.tN (i.e.,
V.sub.GS,M37=V.sub.P,t0-V.sub.Q,t0=(V.sub.P0-V.sub.DD)-(V.sub.Q0+V.sub.DD-
)=(V.sub.P0-V.sub.Y0)-2V.sub.DD<V.sub.tN). The second transistor
M35 is off because the voltage level of the gate thereof is equal
to that of the second node Y (i.e.,
V.sub.G,M35=V.sub.Y=V.sub.Y0+V.sub.DD) and the relative potential
between the source and gate thereof is lower than the threshold
voltage of PMOS transistor |V.sub.tp0| (i.e.,
V.sub.SG,M35=V.sub.P,t0-V.sub.G,M35=(V.sub.P0-V.sub.DD)-(V.sub.Y0+V.sub.D-
D)=(V.sub.P0-V.sub.Y0)-2V.sub.DD<|V.sub.tp0|). At t=t0, because
both the first transistor M34 and the second transistor M35 are
off, the second-stage charge transfer unit 32 has no charge
transfer function. [0037] (c) the output unit 33 [0038] The fifth
transistor Me is off because the relative potential between the
source and gate thereof is lower than the threshold voltage of PMOS
transistor |V.sub.tp0| (i.e.,
V.sub.SG,Me=V.sub.P,t0-V.sub.Q,t0=(V.sub.P0-V.sub.DD)-(V.sub.Q0+V.sub.DD)-
=V.sub.P0-V.sub.Q0-2V.sub.DD<|V.sub.tp0|). The sixth transistor
Mf is on because the source and gate thereof is higher than the
threshold voltage |V.sub.tp0| (i.e.,
V.sub.SG,Mf=V.sub.Q,t0-V.sub.P,t0=(V.sub.Q0+V.sub.DD)-(V.sub.P0-V.sub.DD)-
=2V.sub.DD+V.sub.Q0-V.sub.P0>|V.sub.tp0|). The voltage level of
the seventh node NW3 is equal to that of the sixth node Q (i.e.,
V.sub.NW3=V.sub.Q0+V.sub.DD). Because there is no relative
potential between the source and gate of the fifth transistor Me,
the sixth transistor Mf and the seventh transistor M39, their
threshold voltage is equal to |V.sub.tp0|, i.e., the threshold
voltage when there is no body effect. The seventh transistor M39 is
on because the relative potential between the source and gate
thereof is higher than the threshold voltage |V.sub.tp0| (i.e.,
V.sub.SG,M39=V.sub.Q,t0-V.sub.P,t0=(V.sub.Q0+V.sub.DD)-(V.sub.P0-V.sub.DD-
)=2V.sub.DD+V.sub.Q0-V.sub.P0>|V.sub.tp0|). The eighth
transistor M38 is on because the relative potential between the
gate and source thereof is higher than the threshold voltage
V.sub.tN of NMOS transistor (i.e.,
V.sub.GS,M38=V.sub.Q,t0-V.sub.P,t0=(V.sub.Q0+V.sub.DD)-(V.sub.P0-V.sub.DD-
)=2V.sub.DD+V.sub.Q0-V.sub.P0>V.sub.tN). Therefore, a current
flows from the output node Nout to the third node P, and charges
are transferred from a load capacitor Cout to the first capacitor
C2. Before t1 (t=t1_, the voltage level of the output node Nout of
the charge pump device 30 will gradually decrease from the initial
value V.sub.OUT0 to be steadily held at V.sub.P0-V.sub.DD, i.e.,
V.sub.OUT1.sub.--=V.sub.P0-V.sub.DD,
V.sub.Pt1.sub.--=V.sub.P0-V.sub.DD,
V.sub.Qt1.sub.--=V.sub.P0-V.sub.DD+|V.sub.tp0|.
[0039] (3) t=t1 (the second mode) [0040] At time t1, the first
clock signal A drops from the high level to the low level, while
the second clock signal B rises from the low level to the high
level. The decrease of the voltage level of the first clock signal
A is V.sub.DD. Through the coupling effect of the first capacitor
C1, the voltage level of the second node Y of the first-stage
charge transfer unit 31 is also decreased by V.sub.DD, i.e.,
V.sub.Y,t1=V.sub.Y,t1-V.sub.DD=0-V.sub.DD. Similarly, through the
coupling effect of the second capacitor C3, the voltage level of
the sixth node Q of the output unit 33 is also decreased by
V.sub.DD, i.e.,
V.sub.Q,t1=V.sub.Q,t1-V.sub.DD=(V.sub.P0-V.sub.DD+|V.sub.tp0|)-V.sub.DD=V-
.sub.P0-2V.sub.DD+|V.sub.tp0|. The increase of the voltage level of
the second clock signal B is V.sub.DD. Through the coupling effect
of the first capacitor C2, the voltage level of the second node Y'
of the second-stage charge transfer unit 32 is also increased by
V.sub.DD, i.e.,
V.sub.P,t1=V.sub.P,t1.sub.--+V.sub.DD=V.sub.P0-V.sub.DD+V.sub.DD=V.sub.P0-
. [0041] (a) the first-stage charge transfer unit 31 [0042] The
ninth transistor Ma is on because the relative potential between
the source and gate thereof is higher than the threshold voltage
|V.sub.tp0| of PMOS transistor (i.e.,
V.sub.SG,Ma=V.sub.X,t1-V.sub.Y,t1=0-(-V.sub.DD)=V.sub.DD>|V.sub.tp0|).
The tenth transistor Mb is off because the relative potential
between the source and gate thereof is lower than the threshold
voltage |V.sub.tp0| (i.e.,
V.sub.SG,Mb=V.sub.Y,t1-V.sub.X,t1=-V.sub.DD<|V.sub.tp0|).
Therefore, the voltage level of the eighth node NW1 is equal to
that of the first node X (i.e., V.sub.NW1=0V). In other words, the
first well bias circuit 37 lets the substrates of all the PMOS
transistors (including the first transistor M30, the second
transistor M31, the third transistor M32, the ninth transistor Ma
and the tenth transistor Mb) of the first-stage charge transfer
unit 31 be biased at the first node X (i.e., the input node Nin)
having a higher voltage level in the first-stage charge transfer
unit 31. Because there is no relative potential between the source
and gate of the first transistor M30, the second transistor M31,
the third transistor M32, the ninth transistor Ma and the tenth
transistor Mb, their threshold voltage is equal to |V.sub.tp0|,
i.e., the threshold voltage when there is no body effect. The first
transistor M30 is off because the relative potential between the
source and gate thereof is lower than the threshold voltage
|V.sub.tp0| (i.e.,
V.sub.SG,M32=V.sub.Y,t1-V.sub.X,t1=-V.sub.DD<|V.sub.tp0|). The
third transistor M32 is on because the relative potential between
the source and gate thereof is higher than the threshold voltage
|V.sub.tp0| (i.e.,
V.sub.SG,M32=V.sub.X,t1-V.sub.Y,t1=0-(-V.sub.DD)=V.sub.DD>|V.sub.tp0|)-
. The fourth transistor M33 is off because the relative potential
between the gate and source thereof is lower than the threshold
voltage of NMOS transistor V.sub.tN (i.e.,
V.sub.GS,M33=V.sub.Y,t1-V.sub.P,t1=(-V.sub.DD)-V.sub.P0<V.sub.tN).
The second transistor M31 is off because the voltage level of the
gate thereof is equal to that of the first node X (i.e.,
V.sub.G,M31=0V) and the relative potential between the source and
gate thereof is lower than the threshold voltage of PMOS transistor
|V.sub.tp0| (i.e.,
V.sub.SG,M31=V.sub.Y,t1-V.sub.X,t1=-V.sub.DD<|V.sub.tp0|). At
t=t1, because both the first transistor M30 and the second
transistor M31 are off, the first-stage charge transfer unit 31 has
no charge transfer function. [0043] (b) the second-stage charge
transfer unit 32 [0044] The ninth transistor Mc is off because the
relative potential between the source and gate thereof is lower
than the threshold voltage |V.sub.tp0| of PMOS transistor (i.e.,
V.sub.SG,Mc=V.sub.Y,t1-V.sub.P,t1=-V.sub.DD-V.sub.P0<|V.sub.tp0|).
The tenth transistor Md is on because the relative potential
between the source and gate thereof is higher than the threshold
voltage |V.sub.tp0| (i.e.,
V.sub.SG,Md=V.sub.P,t1-V.sub.Y,t1=V.sub.P0-(-V.sub.DD)>|V.sub.t-
p0|). Therefore, the voltage level of the eighth node NW2 is equal
to that of the third node P (i.e., V.sub.NW2=V.sub.P0). In other
words, the first well bias circuit 37 lets the substrates of all
the PMOS transistors (including the first transistor M34, the
second transistor M35, the third transistor M36, the ninth
transistor Mc and the tenth transistor Md) of the second-stage
charge transfer unit 32 be biased at the second node Y' having a
higher voltage level in the second-stage charge transfer unit 32.
Because there is no relative potential between the source and gate
of the first transistor M34, the second transistor M35, the third
transistor M36, the ninth transistor Mc and the tenth transistor
Md, their threshold voltage is equal to |V.sub.tp0|, i.e., the
threshold voltage when there is no body effect. The first
transistor M34 is on because the relative potential between the
source and gate thereof is higher than the threshold voltage
|V.sub.tp0| (i.e.,
V.sub.SG,M34=V.sub.P,t1-V.sub.Y,t1=V.sub.P0-(-V.sub.DD)>|V.sub.tp0|).
A current flows from the second node Y' to the first node X', and
charges are transferred from the first capacitor C2 to the first
capacitor C1. Before t=t2 (i.e., t=t2_, the voltage level of the
second node Y' (also the third node P of the output unit 33) will
be steadily held at |V.sub.tp0|-V.sub.DD (i.e.,
V.sub.P,t2.sub.--=|V.sub.tp0|-V.sub.DD). The charge transfer
efficiency of the first transistor M34 is equal to
(V.sub.P,t1.sub.---V.sub.P,t2.sub.--)/V.sub.DD. If
V.sub.P,t2.sub.-- can be reduced, the charge transfer efficiency of
the second-stage charge transfer unit 32 can be further improved.
The third transistor M36 is off because the relative potential
between the source and gate thereof is lower than the threshold
voltage |V.sub.tp0| of PMOS transistor (i.e.,
V.sub.SG,M36=V.sub.Y,t1-V.sub.P,t1=-V.sub.DD-V.sub.P0<|V.sub.tp0|).
The fourth transistor M37 is on because the relative potential
between the gate and source thereof is higher than the threshold
voltage V.sub.tN of NMOS transistor (i.e.,
V.sub.GS,M37=V.sub.P,t1-V.sub.Q,t1=V.sub.P0-(V.sub.P0-2V.sub.DD+V.sub.tp0-
|)=2V.sub.DD-|V.sub.tp0|>V.sub.tN). The voltage level of the
gate of the second transistor M35 is equal to that of the sixth
node Q (i.e.,
V.sub.G,M35=V.sub.P0-2V.sub.DD+|V.sub.tp0|<V.sub.G,M34=-V.sub.DD).
Because the voltage level of the gate of the second transistor M35
is lower than that of the gate of the first transistor M34, the
second transistor M35 has a superior charge transfer efficiency
than does the first transistor M34, and the voltage level of the
third node P is lower than |V.sub.tp0|-V.sub.DD and even close to
-V.sub.DD (i.e., V.sub.P,t2.sub.--.apprxeq.-V.sub.DD). Therefore,
the second transistor M35 can assist the first transistor M34 in
enhancing the charge transfer efficiency of the second-stage charge
transfer unit 32. [0045] (c) the output unit 33 [0046] The fifth
transistor Me is on because the relative potential between the
source and gate thereof is higher than the threshold voltage of
PMOS transistor |V.sub.tp0| (i.e.,
V.sub.SG,Me=V.sub.P,t1-V.sub.Q,t1=V.sub.P0-(V.sub.P0-2V.sub.DD+|V.sub.tp0-
|)=2V.sub.DD-|V.sub.tp0|>|V.sub.tp0|). The sixth transistor Mf
is off because the source and gate thereof is lower than the
threshold voltage |V.sub.tp0| (i.e.,
V.sub.SG,Mf=V.sub.Q,t1-V.sub.P,t1=(V.sub.P0-2V.sub.DD+|V.sub.tp0|)-V.sub.-
P0=|V.sub.tp0|2V.sub.DD<|V.sub.tp0|). The voltage level of the
seventh node NW3 is equal to that of the third node P (i.e.,
V.sub.NW3=V.sub.P0). In other words, the second well bias circuit
39 lets the substrates of all the PMOS transistors (including the
fifth transistor Me, the sixth transistor Mf and the seventh
transistor M39) of the output unit 33 be biased at the third node P
having a higher voltage level in the output unit 33. Because there
is no relative potential between the source and gate of the fifth
transistor Me, the sixth transistor Mf and the seventh transistor
M39, their threshold voltage is equal to |V.sub.tp0|, i.e., the
threshold voltage when there is no body effect. The seventh
transistor M39 is off because the relative potential between the
source and gate thereof is lower than the threshold voltage
|V.sub.tp0| (i.e.,
V.sub.SG,M39=V.sub.Q,t1-V.sub.P,t1=(V.sub.P0-2V.sub.DD+|V.sub.tp0|)-V.sub-
.P0=|V.sub.tp0|-2V.sub.DD<|V.sub.tp0|). The eighth transistor
M38 is off because the relative potential between the gate and
source thereof is lower than the threshold voltage V.sub.tN of NMOS
transistor (i.e.,
V.sub.GS,M38=V.sub.Q,t1-V.sub.P,t1=(V.sub.P0-2V.sub.DD+|V.sub.tp0|)-V.sub-
.P0=|V.sub.tp0|-2V.sub.DD<V.sub.tN). Therefore, the output unit
33 has no charge transfer function, and
V.sub.OUT2.sub.--=V.sub.OUT1.sub.--=V.sub.P0-V.sub.DD,
V.sub.Qt2.sub.--=V.sub.P0-2V.sub.DD+|V.sub.tp0|.
[0047] (4) t=t2 (the first mode) [0048] At time t2, the first clock
signal A rises from the low level to the high level, while the
second clock signal B drops from the high level to the low level.
The increase of the voltage level of the first clock signal A is
V.sub.DD. Through the coupling effect of the first capacitor C1,
the voltage level of the second node Y of the first-stage charge
transfer unit 31 is also increased by V.sub.DD, i.e.,
V.sub.Y,t2=V.sub.Yt2.sub.--+V.sub.DD=-V.sub.DD+V.sub.DD=0V
Similarly, through the coupling effect of the second capacitor C3,
the voltage level of the sixth node Q of the output unit 33 is also
increased by V.sub.DD, i.e.,
V.sub.Q,t2=V.sub.Qt2.sub.--+V.sub.DD=(V.sub.P0-2V.sub.DD+|V.sub.tp0-
|)+V.sub.DD=V.sub.P0-V.sub.DD+|V.sub.tp0|. The decrease of the
voltage level of the second clock signal B is V.sub.DD. Through the
coupling effect of the first capacitor C2, the voltage level of the
second node Y' (also the third node P of the output unit 33) of the
second-stage charge transfer unit 32 is also decreased by V.sub.DD,
i.e.,
V.sub.P,t2=V.sub.P,t2.sub.---V.sub.DD=-V.sub.DD-V.sub.DD=-2V.sub.DD.
[0049] (a) the first-stage charge transfer unit 31 [0050]
V.sub.Y,t2=V.sub.X,t2=0V meaning the second node Y of the
first-stage charge transfer unit 31 changes with the first clock
signal A between 0V and -V.sub.DD to completely transfer charges
from the second-stage charge transfer unit 32. [0051] (b) the
second-stage charge transfer unit 32 [0052] The ninth transistor Mc
is on because
V.sub.SG,Mc=V.sub.Y,t2-V.sub.P,t2=0-(-2V.sub.DD)=2V.sub.DD>|V.sub.tp0|-
. The tenth transistor Md is off because
V.sub.SG,Md=V.sub.P,t21-V.sub.Y,t2=-2V.sub.DD<|V.sub.tp0|. The
voltage level of the eighth node NW2 is therefore equal to that of
the first node X' (also the second node Y), i.e.,
V.sub.NW2=V.sub.Y,t2=0V. The first transistor M34 is off because
V.sub.SG,M34=V.sub.P,t2-V.sub.Y,t2=-2V.sub.DD<|V.sub.tp0|. The
third transistor M36 is on because
V.sub.SG,M36=V.sub.Y,t2-V.sub.P,t2=0-(-2V.sub.DD)=2V.sub.DD>|V.sub.tp0-
|. The fourth transistor M37 is off because
V.sub.GS,M37=V.sub.P,t2-V.sub.Q,t2=(-2V.sub.DD)-(V.sub.P0-V.sub.DD+|V.sub-
.tp0|)=-V.sub.P0-V.sub.DD-|V.sub.tp0|<V.sub.tN. The second
transistor M35 is off because
V.sub.SG,M35=V.sub.P,t2-V.sub.S,M35=V.sub.P,t2-V.sub.Y,t2=-2V.sub.DD<|-
V.sub.tp0|. At t=t2, because both the first transistor M34 and the
second transistor M35 are off, the second-stage charge transfer
unit 32 has no charge transfer function. [0053] (c) the output unit
33 [0054] The fifth transistor Me is off because
V.sub.SG,Me=V.sub.P,t2-V.sub.Q,t2=(-2V.sub.DD)-(V.sub.P0-V.sub.DD+|V.sub.-
tp0|)=-|V.sub.tp0|-V.sub.P0-V.sub.DD<|V.sub.tp0|. The sixth
transistor Mf is on because
V.sub.SG,Mf=V.sub.Q,t2-V.sub.P,t2=(V.sub.P0-V.sub.DD+|V.sub.tp0|)-(-2V.su-
b.DD)=V.sub.DD+|V.sub.tp0|+V.sub.P0>|V.sub.tp0|. The voltage
level of the seventh node NW3 is equal to that of the sixth node Q
(i.e., V.sub.NW3=V.sub.P0-V.sub.DD+|V.sub.tp0|). The seventh
transistor M39 is on because
V.sub.SG,M39=V.sub.Q,t2-V.sub.P,t2=(V.sub.P0-V.sub.DD+|V.sub.tp0|)-(-2V.s-
ub.DD)=V.sub.DD+|V.sub.tp0|+V.sub.P0>|V.sub.tp0|. The eighth
transistor M38 is on because
V.sub.GS,M38=V.sub.Q,t2-V.sub.P,t2=V.sub.DD+|V.sub.tp0|+V.sub.P0>V.sub-
.tN. Therefore, a current flows from the output node Nout to the
third node P, and charges are transferred from the load capacitor
Cout to the first capacitor C2. Before t3 (t=t3_, the voltage level
of the output node Nout of the charge pump device 30 will gradually
decrease from the V.sub.OUT,t2=V.sub.P0-V.sub.DD to be steadily
held at -2V.sub.DD, i.e., V.sub.OUT3.sub.--=-2V.sub.DD,
V.sub.Pt3.sub.--=-2V.sub.DD,
V.sub.Qt3.sub.--=-2V.sub.DD+|V.sub.tp0|.
[0055] (5) t=t3 (the second mode) [0056] At time t3, the first
clock signal A drops from the high level to the low level, while
the second clock signal B rises from the low level to the high
level. The decrease of the voltage level of the first clock signal
A is V.sub.DD. Through the coupling effect of the first capacitor
C1, the voltage level of the second node Y of the first-stage
charge transfer unit 31 is also decreased by V.sub.DD, i.e.,
V.sub.Y,t3=V.sub.Y,t3.sub.---V.sub.DD=0-V.sub.DD. Similarly,
through the coupling effect of the second capacitor C3, the voltage
level of the sixth node Q of the output unit 33 is also decreased
by V.sub.DD, i.e.,
V.sub.Q,t3=V.sub.Q,t3.sub.---V.sub.DD=(-2V.sub.DD+|V.sub.tp0|)-V.sub.DD=--
3V.sub.DD+|V.sub.tp0|. The increase of the voltage level of the
second clock signal B is V.sub.DD. Through the coupling effect of
the first capacitor C2, the voltage level of the second node Y' of
the second-stage charge transfer unit 32 is also increased by
V.sub.DD, i.e.,
V.sub.P,t3=V.sub.P,t3.sub.--+V.sub.DD=(-2V.sub.DD)+V.sub.DD=-V.sub.DD.
[0057] (a) the first-stage charge transfer unit 31 [0058] The ninth
transistor Ma is on because
V.sub.SG,Ma=V.sub.X,t3-V.sub.Y,t3=0-(-V.sub.DD)=V.sub.DD>|V.sub.tp0|.
The tenth transistor Mb is off because
V.sub.SG,Mb=V.sub.Y,t3-V.sub.X,t3=(-V.sub.DD)-0<|V.sub.tp0|.
Therefore, the voltage level of the eighth node NW1 is equal to
that of the first node X (i.e., V.sub.NW1=0V). The first transistor
M30 is off because
V.sub.SG,M30=V.sub.Y,t3-V.sub.X,t3=-V.sub.DD<|V.sub.tp0|. The
third transistor M32 is on because
V.sub.SG,M32=V.sub.X,t3-V.sub.Y,t3=0-(-V.sub.DD)=V.sub.DD>|V.sub.tp0|.
The fourth transistor M33 is off because
V.sub.GS,M33=V.sub.Y,t3-V.sub.P,t3=(-V.sub.DD)-V.sub.P0<V.sub.tN.
The second transistor M31 is off because the voltage level of the
gate thereof is equal to that of the first node X (0V) and the
relative potential between the source and gate thereof is lower
than the threshold voltage of PMOS transistor |V.sub.tp0| (i.e.,
V.sub.SG,M31=V.sub.Y,t3-V.sub.X,t3=-V.sub.DD<|V.sub.tp0|). At
t=t3, because both the first transistor M30 and the second
transistor M31 are off, the first-stage charge transfer unit 31 has
no charge transfer function. [0059] (b) the second-stage charge
transfer unit 32 [0060] V.sub.Y,t3=V.sub.P,t3=0V, meaning the
second node Y' changes with the second clock signal B between
-V.sub.DD and -2V.sub.DD to completely transfer charges from the
output unit 33. [0061] (c) the output unit 33 [0062] The fifth
transistor Me is on because
V.sub.SG,Me=V.sub.P,t3-V.sub.Q,t3=-V.sub.DD-(-3V.sub.DD+|V.sub.tp0|)=2V.s-
ub.DD-|V.sub.tp0|>|V.sub.tp0|. The sixth transistor Mf is off
because
V.sub.SG,Mf=V.sub.Q,t3-V.sub.P,t3=(-3V.sub.DD+|V.sub.tp0|)-(-V.sub.DD)=|V-
.sub.tp0|-2V.sub.DD<|V.sub.tp0|. The voltage level of the
seventh node NW3 is equal to that of the third node P (i.e.,
V.sub.NW3=V.sub.P,t3=-V.sub.DD). The seventh transistor M39 is off
because
V.sub.SG,M39=V.sub.Q,t3-V.sub.P,t3=(-3V.sub.DD+|V.sub.tp0|)-(-V.s-
ub.DD)=|V.sub.tp0|-2V.sub.DD<|V.sub.tp0|. The eighth transistor
M38 is off because
V.sub.GS,M38=V.sub.Q,t3-V.sub.P,t3=(-3V.sub.DD+|V.sub.tp0|)-(-V.sub.DD)=|-
V.sub.tp0|-2V.sub.DD<V.sub.tN. Therefore, the output unit 33 has
no charge transfer function, and
V.sub.OUT4.sub.---V.sub.OUT3.sub.--=-2V.sub.DD,
V.sub.Qt4.sub.--=V.sub.Q,t3=-3V.sub.DD+|V.sub.tp0|.
[0063] (6) t=t4 (the first mode) [0064] At time t4, the first clock
signal A rises from the low level to the high level, while the
second clock signal B drops from the high level to the low level.
The increase of the voltage level of the first clock signal A is
V.sub.DD. Through the coupling effect of the first capacitor C1,
the voltage level of the second node Y of the first-stage charge
transfer unit 31 is also increased by V.sub.DD, i.e.,
V.sub.Y,t4=V.sub.Yt4.sub.--+V.sub.DD=-V.sub.DD+V.sub.DD=0V
Similarly, through the coupling effect of the second capacitor C3,
the voltage level of the sixth node Q of the output unit 33 is also
increased by V.sub.DD, i.e.,
V.sub.Q,t4=V.sub.Qt4.sub.--+V.sub.DD=(-3V.sub.DD+|V.sub.tp0|)+V.sub-
.DD=-2V.sub.DD+|V.sub.tp0|. The decrease of the voltage level of
the second clock signal B is V.sub.DD. Through the coupling effect
of the first capacitor C2, the voltage level of the second node Y'
of the second-stage charge transfer unit 32 is also decreased by
V.sub.DD, i.e.,
V.sub.P,t4=V.sub.P,t4.sub.---V.sub.DD=-V.sub.DD-V.sub.DD=-2V.sub.DD.
[0065] (a) the first-stage charge transfer unit 31 [0066]
V.sub.Y,t4=V.sub.X,t4=0V, meaning the second node Y of the
first-stage charge transfer unit 31 changes between 0V and
-V.sub.DD to completely transfer charges from the second-stage
charge transfer unit 32. [0067] (b) the second-stage charge
transfer unit 32 [0068] The ninth transistor Mc is on because
V.sub.SG,Mc=V.sub.Y,t4-V.sub.P,t4=0-(-2V.sub.DD)=2V.sub.DD>|V.sub.tp0|-
. The tenth transistor Md is off because
V.sub.SG,Md=V.sub.P,t4-V.sub.Y,t4=-2V.sub.DD<|V.sub.tp0|. The
voltage level of the eighth node NW2 is therefore equal to that of
the first node X', i.e., V.sub.NW2=0V. The first transistor M34 is
off because
V.sub.SG,M34=V.sub.P,t4-V.sub.Y,t4=-2V.sub.DD<|V.sub.tp0|. The
third transistor M36 is on because
V.sub.SG,M36=V.sub.Y,t4-V.sub.P,t4=0-(-2V.sub.DD)=2V.sub.DD>|V.sub.tp0-
|. The fourth transistor M37 is off because
V.sub.GS,M37=V.sub.P,t4-V.sub.Q,t4=(-2V.sub.DD)-(-2V.sub.DD+|V.sub.tp0|)=-
-|V.sub.tp0|<V.sub.tN. The second transistor M35 is off because
V.sub.SG,M35=V.sub.P,t4-V.sub.S,M35=V.sub.P,t4-V.sub.Y,t4=-2V.sub.DD<|-
V.sub.tp0|. At t=t4, because both the first transistor M34 and the
second transistor M35 are off, the second-stage charge transfer
unit 32 has no charge transfer function. [0069] (c) the output unit
33 [0070] V.sub.OUT,t4=V.sub.P,t4=-2V.sub.DD, meaning the voltage
level of the output node Nout is kept at -2V.sub.DD to completely
transfer charges from the load capacitor Cout.
[0071] In the above first mode, the first-stage
(odd-numbered-stage) charge transfer unit 31 and the output unit 33
are enabled, while the second-stage (even-numbered-stage) charge
transfer unit 32 is disabled. Thereby, the first-stage
(odd-numbered-stage) charge transfer unit 31 completely transfers
charges from the second-stage (even-numbered-stage) charge transfer
unit 32, the output unit 33 completely transfers charges from the
output node Nout, but the second-stage charge transfer unit 32 has
no charge transfer function. In the above second mode, the
second-stage (even-numbered-stage) charge transfer unit 32 is
enabled, while the first-stage (odd-numbered-stage) charge transfer
unit 31 and the output unit 33 are disabled. Thereby, the
second-stage charge transfer unit 32 completely transfers charges
from the output unit 33, and the output unit 33 has no charge
transfer function. Therefore, by repetitively switching the charge
transfer units 31 and 32 and the output unit 33 between the first
mode and the second mode, an output voltage can be finally
generated at the output node Nout, i.e., V.sub.OUT=-2V.sub.DD. If a
voltage level of -N.times.V.sub.DD is desired, it is only necessary
to cascade N stages of charge transfer units and an output unit.
The voltage level of each node and operational status of each
transistor at different times are summarized in Table 1 below.
TABLE-US-00001 TABLE 1 Node t = 0 t = t0 t = t1.sub.-- t = t1 t =
t2.sub.-- t = t2 t = t3.sub.-- t = t3 t = t4.sub.-- t = t4 t =
t5.sub.-- Y V.sub.Y0 V.sub.Y0 + V.sub.DD 0 -V.sub.DD -V.sub.DD 0 0
-V.sub.DD -V.sub.DD 0 -V.sub.DD P V.sub.P0 V.sub.P0 - V.sub.DD
V.sub.P0 - V.sub.DD V.sub.P0 -V.sub.DD -2V.sub.DD -2V.sub.DD
-V.sub.DD -V.sub.DD -2V.sub.DD -2V.sub.DD Q V.sub.Q0 V.sub.Q0 +
V.sub.DD V.sub.P0 - V.sub.DD + V.sub.P0 - V.sub.P0 - V.sub.P0 -
V.sub.DD + -2V.sub.DD + -3V.sub.DD + -3V.sub.DD + -2V.sub.DD +
-2V.sub.DD + |V.sub.tp0| 2V.sub.DD + 2V.sub.DD + |V.sub.tp0|
|V.sub.tp0| |V.sub.tp0| |V.sub.tp0| |V.sub.tp0| |V.sub.tp0|
|V.sub.tp0| |V.sub.tp0| OUT V.sub.OUT0 V.sub.OUT0 V.sub.P0 -
V.sub.DD V.sub.P0 - V.sub.DD V.sub.P0 - V.sub.DD V.sub.P0 -
V.sub.DD -2V.sub.DD -2V.sub.DD -2V.sub.DD -2V.sub.DD -2V.sub.DD
First-stage -- ON ON X X ON ON X X ON ON charge transfer unit 31
Second-stage -- X X ON ON X X ON ON X X charge transfer unit 32
Output unit -- ON ON X X ON ON X X ON ON 33
[0072] FIG. 4(a) is a diagram of a charge pump device according to
a second embodiment of the present invention. Please also refer to
FIG. 4(b). A charge pump device 40 is composed of two stages of
charge transfer units 41 and 42 and an output unit 43 that are
cascaded between an input node Nin and an output node Nout. The
charge transfer unit 41 (42) includes a first circuit 44 (45) and a
first capacitor C1 (C2). The output unit 43 has a second circuit
46. The second circuit 46 has a second well bias circuit 47
therein. In order to get a negative voltage, the input node Nin is
grounded. This second embodiment differs from the above first
embodiment in that the first circuits 44 and 45 in the charge
transfer units 31 and 32 have no first well bias circuit that
exists in the first embodiment.
[0073] PMOS transistors in the first-stage charge transfer unit 41
include a first transistor M40, a second transistor M41 and a third
transistor M42. The N-well regions of the first transistor M40, the
second transistor M41 and the third transistor M42 are all biased
at a first node X of the first-stage charge transfer unit 41. PMOS
transistors in the second-stage charge transfer unit 42 include a
first transistor M44, a second transistor M45 and a third
transistor M46. The N-well regions of the first transistor M44, the
second transistor M45 and the third transistor M46 are all biased
at a first node X' of the second-stage charge transfer unit 42.
[0074] Please simultaneously refer to FIG. 4(a), FIG. 4(b) and FIG.
5. When the voltage level of the second node Y' of the second-stage
charge transfer unit 42 is raised through the coupling effect of
the first capacitor C2 to the second clock signal B and the voltage
level of the second node Y of the first-stage charge transfer unit
41 is lowered through the coupling effect of the first capacitor C1
to the first clock signal A, the first capacitor M44 will be on.
Assisted by the conduction of the forward-biased P.sup.+/N-well
junction diode (with reference to FIG. 5), the on-resistance of the
first transistor M44 is reduced, and the on-time thereof is
increased, thereby improving the charge transfer efficiency of the
charge transfer unit 42.
[0075] Although the present invention has been described with
reference to the preferred embodiment thereof, it will be
understood that the invention is not limited to the details
thereof. Various substitutions and modifications have been
suggested in the foregoing description, and others will occur to
those of ordinary skill in the art. Therefore, all such
substitutions and modifications are intended to be embraced within
the scope of the invention as defined in the appended claims.
* * * * *