U.S. patent application number 12/174590 was filed with the patent office on 2009-02-26 for amorphous soft magnetic shielding and keeper for mram devices.
Invention is credited to Michael GUTKIN, Jacques Constant Stefan KOOLS, Ming MAO, Thomas SCHNEIDER, Jinsong WANG.
Application Number | 20090050992 12/174590 |
Document ID | / |
Family ID | 31714874 |
Filed Date | 2009-02-26 |
United States Patent
Application |
20090050992 |
Kind Code |
A1 |
KOOLS; Jacques Constant Stefan ;
et al. |
February 26, 2009 |
AMORPHOUS SOFT MAGNETIC SHIELDING AND KEEPER FOR MRAM DEVICES
Abstract
An amorphous soft magnetic thin film material for forming
shielding and keeper applications in MRAM devices. The amorphous
soft magnetic material may be deposited using Physical Vapor
Deposition (PVD) in the presence of a magnetic field, in order to
form shielding layers and keepers in a multi-layer metallization
process. The soft magnetic material may be an amorphous metallic
alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh.
Inventors: |
KOOLS; Jacques Constant Stefan;
(Sunnyvale, CA) ; MAO; Ming; (Pleasanton, CA)
; SCHNEIDER; Thomas; (Pleasanton, CA) ; WANG;
Jinsong; (Pleasanton, CA) ; GUTKIN; Michael;
(Danville, CA) |
Correspondence
Address: |
DLA PIPER LLP (US )
2000 UNIVERSITY AVENUE
EAST PALO ALTO
CA
94303-2248
US
|
Family ID: |
31714874 |
Appl. No.: |
12/174590 |
Filed: |
July 16, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10943510 |
Sep 15, 2004 |
7405085 |
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12174590 |
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10222089 |
Aug 14, 2002 |
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10943510 |
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Current U.S.
Class: |
257/422 ;
257/E21.001; 257/E29.323; 438/3 |
Current CPC
Class: |
H01L 43/08 20130101;
H01L 27/222 20130101; H01L 43/12 20130101 |
Class at
Publication: |
257/422 ; 438/3;
257/E29.323; 257/E21.001 |
International
Class: |
H01L 29/82 20060101
H01L029/82; H01L 21/00 20060101 H01L021/00 |
Claims
1.-37. (canceled)
38. The keeper of claim 44 wherein the current carrying line
includes a bottom and a pair of side surfaces, and wherein the
material is adjacent to the bottom and pair of side surfaces.
39. (canceled)
40. The keeper of claim 44 wherein the current carrying line
includes a top surface and a pair of side surfaces, and wherein the
material is adjacent to the top and pair of side surfaces.
41. The keeper of claim 44 wherein the amorphous soft magnetic
material is an amorphous metallic alloy of the form CoZrX, where X
is selected from the group consisting of Ta, Nb, Pd and Rh.
42. The keeper of claim 41 wherein the amorphous soft magnetic
material has a thickness in the range of approximately 50 .ANG. to
500 .ANG..
43. A keeper for a magneto-resistance stack device including a bit
region and a current carrying line which magnetically interacts
with the bit region, the keeper comprising: an amorphous soft
magnetic material which is disposed generally around the current
carrying line.
44. The keeper of claim 43 wherein the current carrying line
includes a bottom and a pair of side surfaces, and wherein the
material is adjacent to the bottom and pair of side surfaces.
45. The keeper of claim 44 wherein the material on the bottom and
pair of side surfaces has an aspect ratio in the range of
approximately 1:0.5 to 1:2.
46. The keeper of claim 43 wherein the current carrying line
includes a top surface and a pair of side surfaces, and wherein the
material is adjacent to the top and pair of side surfaces.
47. The keeper of claim 43 wherein the amorphous soft magnetic
material is an amorphous metallic alloy of the form CoZrX, where X
is selected from the group composed of Ta, Nb, Pd and Rh.
48. The keeper of claim 47 wherein the amorphous soft magnetic
material has a thickness in the range of approximately 50 .ANG. to
500 .ANG..
49. The keeper of claim 43 further comprising a lining layer
disposed between the amorphous soft magnetic material and the
current carrying line.
50. The keeper of claim 44 further comprising a lining layer
disposed between the amorphous soft magnetic material and the
current carrying line.
51. A shielding structure for an MRAM device having a bit region
and a current carrying line which magnetically interacts with the
bit region, the shielding structure comprising: an amorphous soft
magnetic material which is disposed adjacent to the MRAM device and
which is effective to block external magnetic fields from affecting
the bit region of the MRAM device.
52. The shielding structure of claim 51 wherein said amorphous soft
magnetic material comprises a first layer which is disposed below
the bit region and current carrying line, and a second layer which
is disposed above the bit region and current carrying line.
53. The shielding structure of claim 51 wherein the amorphous soft
magnetic material is an amorphous metallic alloy of the form CoZrX,
where X may be selected from the group consisting of Ta, Nb, Pd and
Rh.
54. The shielding structure of claim 53 wherein the amorphous soft
magnetic material has a thickness in the range of approximately 0.1
.quadrature.m to 10 .quadrature.m.
55. A method of fabricating a shielding structure for an MRAM
device, the method comprising the steps of: providing an amorphous
soft magnetic material; and forming the shielding structure from
the amorphous soft magnetic material.
56. The method of claim 55 wherein the amorphous soft magnetic
material is an amorphous metallic alloy of the form CoZrX, where X
is selected from the group consisting of Ta, Nb, Pd and Rh.
57. The method of claim 55 wherein the step of forming the
shielding structure includes the following step: depositing a first
layer of the amorphous soft magnetic material adjacent to the MRAM
device.
58. The method of claim 57 wherein the step of forming the
shielding structure further includes the following step: depositing
a second layer of the amorphous soft magnetic material adjacent to
the MRAM device, wherein the first layer is disposed below the MRAM
device and the second layer is disposed above the MRAM device.
59. The method of claim 58 wherein the amorphous soft magnetic
material is deposited in the presence of an external magnetic
field.
60. The method of claim 59 wherein the amorphous soft magnetic
material is deposited by use of a PVD process.
61. The method of claim 55 wherein the MRAM device includes a first
level of cells and a second level of cells, and wherein the step of
forming the shielding structure includes: forming a layer of
amorphous soft magnetic material between the first and second
levels of cells.
62. The method of claim 61 wherein the step of forming the a layer
of the amorphous soft magnetic material between the first and
second levels of cells includes: forming the first level of cells;
depositing a layer of amorphous soft magnetic material on the first
level of cells; and forming the second level of cells above the
layer of amorphous soft magnetic material.
63. The method of claim 62 wherein the layer of amorphous soft
magnetic material is deposited in the presence of a magnetic
field.
64. The method of claim 63 wherein the layer of amorphous soft
magnetic material is deposited by use of a PVD process.
65.-71. (canceled)
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of application Ser. No. 10/943,510,
filed Sep. 15, 2004, published as US2005/0045998 A1, now U.S. Pat.
No. 7,405,085, which is a continuation of application Ser. No.
10/222,089, filed Aug. 14, 2002, published as US2004/0032010 A1,
now abandoned, which are incorporated herein by reference in
entirety.
BACKGROUND
[0002] 1. Field
[0003] The present invention generally relates to magnetic random
access memory (MRAM) devices and more particularly, to an amorphous
soft magnetic layer for application as a shield and keeper in MRAM
devices.
[0004] 2. Description of Related Information
[0005] Magnetic Random Access Memory (MRAM) devices based on
spin-dependent tunnel junctions are being explored as non-volatile
solid state memory devices for embedded and stand alone
applications. MRAM devices utilize magnetic material within memory
cells to store data bits. The data bits are read by
magnetoresistive sensing. MRAM memory cells can be programmed by
magnetizing the magnetic material within the cells. The magnetic
field required to switch the state of a cell (e.g., from "0" to
"1") is typically quite low, e.g., in the range of 10-25 Oersteds
(Oe).
[0006] In its basic concept, an MRAM memory cell typically consists
of a patterned magnetic multi-layer bit region, and two conductive
lines (e.g., the word and bit lines) that are used to read and
write the magnetic state of the multi-layer bit region. In further
refinements, additional magnetic layers have been included within
MRAM memory cells in order to (1) provide magnetic shielding and
(2) improve write efficiency.
[0007] 1. Magnetic Shielding
[0008] In order to successfully incorporate MRAM into portable
electronic devices such as portable phones, personal digital
assistants (PDA's), pagers, and the like, it is necessary to shield
the MRAM devices from stray magnetic fields that may present within
and around such devices. Examples of such disturbances include the
magnetic field generated by a loudspeaker in a telephone, which may
be as large as approximately 800 Oe, and the current in the
overhead lines of a train, which may produce magnetic fields as
large as approximately 50 Oe.
[0009] Efforts have been made to shield MRAM devices from these
types of stray magnetic fields. For example, U.S. Pat. No.
5,902,690 of Tracy et al. ("Tracy et al.") describes the
introduction of a passivation layer encapsulating the chip. Tracy
et al. describes two embodiments of a passivation layer. The first
embodiment uses a ceramic material that includes ferrite particles
to encapsulate the MRAM cell. The second embodiment uses a ferrite
film, which is deposited on top of the MRAM device. U.S. Pat. No.
6,211,090 of Durlam et al. ("Durlam et al.") describes another
method of shielding an MRAM device, namely by forming a metallic,
high permeability shielding layer, such as NiFe, on top of the
completed device.
[0010] 2) Improving Write Efficiency by Use of a Magnetic
Keeper
[0011] Inserting a soft magnetic keeper around the write conductors
of an MRAM device has been found to provide a desirable
modification or concentration of the flux path resulting in an
increase of the write efficiency, which could result in a decreased
power consumption of the device. U.S. Pat. No. 5,956,267 of Hurst
et al. discloses such an arrangement.
[0012] An important aspect of magnetic shielding and keeper layers
is their compatibility with standard integrated circuit (IC)
metallization processing. A state of the art metallization scheme
typically encompasses the use of multilevel copper metallization
layers, separated by dielectric layers such as Plasma Enhanced
Chemical Vapor Deposited (PECVD) SiO.sub.2 or other low k materials
(e.g., in a dual damascene metallization scheme). For a magnetic
layer to be integrated in such a process flow, the following
criteria are desirable: [0013] 1. The permeability .mu. of the
magnetic film should be sufficiently high (e.g., >100). The
efficiency of shielding is proportional to the film thickness "t"
multiplied by .mu.. Having an insufficient value of .mu. results in
an unpractical requirement on the thickness of the magnetic
shielding layer. [0014] 2. The thermal stability of the magnetic
material must be such that the permeability is not reduced
significantly by the thermal budget associated with the process.
The thermal budget of a damascene process is typically governed by
the dielectric deposition. One example of a typical temperature for
such a process may be 450.degree. C. [0015] 3. The preparation
method of the magnetic film should preferably employ standard
semiconductor deposition methods such as Physical Vapor Deposition
(PVD) or Chemical Vapor Deposition (CVD). [0016] 4. The magnetic
material should preferably not contain metals which, when diffusing
in the silicon, would degrade transistor performance. If such
materials are used, the use of a diffusion barrier is required.
[0017] 5. In the case of the keeper layer, the permeability has to
have a high value at frequencies close to and slightly above the
write frequency of the memory (e.g., several hundreds of MHz to low
GHz).
[0018] While above-referenced prior art teachings provide shielding
and keepers for use with MRAM devices, they suffer from some
drawbacks resulting from the materials that are used, which make
them difficult to incorporate into a multi-layer IC metallization
process.
[0019] For example, while the inventions of Tracy et al. and Durlam
et al. are effective to shield MRAM devices from stray magnetic
fields, they suffer from some drawbacks resulting from the types of
materials used for the shielding and passivation layers. For
example, the foregoing references propose using either oxidic
magnetic films (e.g., Mn--Zn-Ferrite or Ni--Zn-Ferrite) or
crystalline metallic films (e.g., NiFe alloys) for shielding.
Crystalline materials (e.g., Ni.sub.80Fe.sub.20,
Ni.sub.45Fe.sub.55, FeTaN) generally display some degree of
recrystallization during high temperature processes which leads to
a degradation of magnetic properties. Therefore, these materials
may be unsuited for multi-layer IC fabrications in which a device
undergoes one or more high temperature processes after the
deposition of a shielding or passivation layer.
[0020] In Hurst et al., NiFe, CoNiFe and CoFe are suggested as
materials for keeper fabrication. One drawback associated with the
materials used for the keeper of Hurst et al. is that they require
the use of a diffusion barrier such as TiW, TaN, or the like. The
inclusion of this additional diffusion layer undesirably
complicates and increases the cost of the fabrication process.
Furthermore, it has been found that the permeability of such
materials drops typically in the frequency range of tens to
hundreds of MHz, due to eddy current losses and ferromagnetic
resonance. This adversely affects the operation and effectiveness
of the keeper layers at frequencies relatively close to the write
frequency of typical MRAM devices (e.g., several hundreds of MHz to
low GHz).
[0021] There is therefore a need for a new and improved material
for magnetic shielding and keeper applications in MRAM devices,
which is adapted for integration with a multi-layer fabrication
process.
SUMMARY OF THE INVENTION
[0022] Generally, the present invention provides a soft magnetic
material with improved properties for use in both shield and keeper
applications in MRAM devices.
[0023] One non-limiting advantage of the invention is that it uses
films of amorphous soft magnetic alloys, such as CoZrTa, for
magnetic shielding and keeper applications. These amorphous soft
magnetic alloys have several unique advantages to allow for
integration with a dual damascene Copper/SiO.sub.2 (or low-k)
metallization process. Some non-limiting examples include: [0024]
(i) excellent thermal stability (e.g., crystallization
temperature>450.degree. C.), making this material compatible
with standard CMOS backend processing; [0025] (ii) significant
permeability up to the write frequencies required in high speed
memory devices (several GHz); and [0026] (iii) for the case of
CoZrTa, the possibility to eliminate the barrier layer.
[0027] Another non-limiting advantage of the present invention is
that it provides a soft magnetic shielding layer that may be
introduced between subsequent layers of a multilevel metallization.
This allows for the transport of large currents through
metallization layers located on one side of the magnetic layer,
without affecting the magnetic state of MRAM cells located on the
other side of the magnetic layer.
[0028] Another non-limiting advantage of the present invention is
that it provides an amorphous, soft magnetic material that can be
interposed between different layers of spin-dependent tunnel
junctions.
[0029] According to a first aspect of the present invention, a
keeper is provided for an MRAM device including a bit region and a
current carrying line which magnetically interacts with the bit
region. The keeper comprises an amorphous soft magnetic material
which is disposed generally around the current carrying line.
[0030] According to a second aspect of the present invention, a
shielding structure is provided for an MRAM device having a bit
region and a current carrying line which magnetically interacts
with the bit region. The shielding structure includes an amorphous
soft magnetic material which is disposed adjacent to the MRAM
device and which is effective to block external magnetic fields
from affecting the bit region of the MRAM device.
[0031] According to a third aspect of the present invention, a
method of fabricating a keeper for an MRAM device having a bit
region and a current carrying line is provided.
[0032] The method includes the steps of: providing an amorphous
soft magnetic material; and forming the keeper from the amorphous
soft magnetic material.
[0033] According to a fourth aspect of the present invention, a
method of fabricating a shielding structure for an MRAM device is
provided. The method includes the steps of: providing an amorphous
soft magnetic material; and forming the shielding structure from
the amorphous soft magnetic material.
[0034] According to a fifth aspect of the present invention, a
method of fabricating an MRAM device is provided. The method
includes the steps of: providing a substrate; depositing a
dielectric layer on the substrate; forming a trench in the
dielectric layer for forming a first current carrying line;
depositing an amorphous soft magnetic material in the trench;
depositing a conductor into the trench, thereby forming the first
current carrying line, wherein the amorphous soft magnetic material
forms a first keeper around the first current carrying line;
forming a bit region over the current carrying line;
[0035] forming a second current carrying line above the bit region;
and depositing an amorphous soft magnetic material above the second
current carrying line, thereby forming a second keeper around the
second current carrying line.
[0036] These and other features, advantages, and objects of the
invention will become apparent by reference to the following
specification and by reference to the following drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0037] FIGS. 1A-1G depict an exemplary process flow for fabricating
an MRAM device having keepers, according to the present
invention.
[0038] FIG. 2 is side sectional view of an MRAM device including
layers for shielding against external magnetic fields.
[0039] FIG. 3 is a side sectional view of an MRAM device including
shielding between memory cells on different levels.
[0040] FIG. 4 depicts a pair of tables showing exemplary process
variables that may be used in a PVD tool to deposit an amorphous
soft magnetic alloy, according to one embodiment of the present
invention, and optimized responses for the deposition process.
[0041] FIG. 5 is a table illustrating exemplary process conditions
that may be used to deposit a keeper layer of amorphous soft
magnetic material in an MRAM fabrication process, according to one
embodiment of the invention.
[0042] FIG. 6 is a magnetization loop for a 2000 .ANG. CoZrTa
film.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0043] The present invention will now be described in detail with
reference to the drawings, which are provided as illustrative
examples of the invention so as to enable those skilled in the art
to practice the invention. The preferred embodiment of the soft
magnetic shield and keeper and the method for forming the same are
described in relation to a multi-layer MRAM fabrication procedure.
However, it will be appreciated by those skilled in the art that
the present invention is equally applicable to other types of
fabrication procedures.
[0044] Generally, soft magnetic thin film materials can be
classified in three main classes including: (1) crystalline
metallic films such as Permalloy (NiFe alloys around the
composition Ni.sub.80Fe.sub.20), FeXN (where X may be a metal such
as Ta, Al, Ti, etc.), and the like; (2) Oxidic metallic films such
as Manganese Zinc Ferrite or Nickel Zinc Ferrite; and (3) amorphous
metallic films such as CoNbZr, CoTaZr or CoPdZr. While prior art
MRAM fabrication procedures have included the use of class (1) and
(2) materials for shielding and keeper applications, none of the
prior art have contemplated the use of class (3) materials.
[0045] The present invention provides MRAM devices that utilize
amorphous, soft magnetic thin film materials (e.g., class (3)
materials) for shielding and keeper applications, and a process for
forming such devices. In the preferred embodiment, the family of
amorphous metallic alloys of the form CoZrX, where X may be Nb, Ta,
Pd and/or Rh for example, are used for integrated magnetic
shielding and keeper layers in an MRAM device fabrication
procedure.
[0046] FIGS. 1A-1H depict an exemplary embodiment of a process
flow, which may be utilized for fabricating an MRAM apparatus,
according to the present invention. FIG. 1A depicts a side
sectional view of a conventional substrate 100, and a dielectric
(e.g., SiO.sub.2 or other low k material) layer 102, which is
deposited on top of substrate 100 in a conventional manner. In the
first step of the process flow, a word or bit line trench 104 is
formed (e.g., etched) into the dielectric layer 102 in a known
manner.
[0047] FIG. 1B illustrates a second step in the process flow. In
this second step, a keeper layer 106 is deposited on top of the
dielectric layer 102. The keeper layer 106 is formed from an
amorphous, soft magnetic material. Particularly, in the preferred
embodiment, the keeper layer 106 is formed from an amorphous
metallic alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh.
Any suitable ratios of Co, Zr, Ta, Nb, Pd, and Rh may be used in
the alloy, and those skilled in the art will appreciate how to
select ratios for certain alloys to provide the amorphous and soft
magnetic properties, and to ensure that the material best suits a
particular application. For example, in one embodiment, the Co
concentration should be in the range of approximately 80-90% to
ensure a high saturation magnetization. Furthermore, the
proportions of the elements may be adjusted to achieve a desired
the magnetostriction constant .lamda. of the material. One of
ordinary skill in the art will appreciate how to make such
adjustments. For example, K. Hayashi et al., J. Appl. Phys., Vol.
61, p. 2983 (1987) teach a variety of compositions in the ternary
phase diagram, suitable for this application. The particular
composition can be chosen based on specific requirements for
crystallization temperature and saturation magnetization.
[0048] In one embodiment, the aspect ratio of the sidewall coverage
in the trench 104 may be in the range of approximately 1:0.5 to
1:2. For example, in one embodiment, the thickness of the keeper
106 on the bottom of the trench 104 may be approximately 100 .ANG.,
and the thickness on the side of the trench may be approximately 50
.ANG.. In the preferred embodiment, the thickness "d" of the keeper
106 may be in the range of 50 to 500 .ANG..
[0049] In one embodiment the keeper layer 106 may be formed or
deposited by use of a Physical Vapor Deposition (PVD) or sputtering
process, which may be performed in a conventional PVD cluster tool
in the presence of a magnetic field. Other techniques that may be
used include Ion Beam Deposition (IBD), evaporation, ionized PVD
(I-PVD), ion-metal plasma (IMP), Cathodic Arc deposition, atomic
layer deposition (ALD), Chemical Vapor Deposition (CVD) or
Electroplating. However, PVD is preferred since it is
well-established that PVD allows to deposit films with the
appropriate magnetic properties. The application of a magnetic
field during deposition leads to better-defined soft magnetic
properties. Some examples of process variables that may be used in
a PVD tool (with no collimation, physical collimation and natural
collimation) to deposit a particular amorphous soft magnetic alloy
(i.e., CoZrNb) are illustrated in table 400 of FIG. 4, and
optimized responses for the process are shown in table 410 of FIG.
4.
[0050] In the step illustrated in FIG. 1B, a lining layer 108 may
also be deposited on top of the keeper layer 106. In one
embodiment, the lining layer 108 may comprise TaN. In other
embodiments, the lining layer 108 may be deposited first (e.g., on
top of the dielectric layer 102), followed by the keeper layer 106
(e.g., on top of the lining layer 108). The lining layer 108 may
serve as a diffusion barrier and adhesion layer.
[0051] In the next step of the process flow, illustrated in FIG.
1C, a conductive material (e.g., Cu or Al) is deposited within the
trench 104, thereby forming a current carrying line 110 (e.g., a
word or bit line). In the preferred embodiment, the current
carrying line 110 is formed by depositing conductive material over
the entire surface of the device by use of a conventional
electroplating process. Next, a chemical mechanical polish is
performed over the surface of the device, effective to remove
excess portions of the conductive material, keeper, and liner,
thereby forming the structure shown in FIG. 1C. As shown in FIG.
1C, keeper 106 is formed or disposed generally around current
carrying line 110 (e.g., in relative close proximity and/or
adjacent to the bottom and side walls of the current carrying line
110). In other embodiments, keeper 106 may have a different shape,
and in one example, keeper 106 may be adjacent only to the bottom
of line 110.
[0052] In the next step of the process flow, illustrated in FIG.
1D, a tunnel-magneto-resistance (TMR) stack 112 is deposited across
the surface of the device in a conventional manner. The TMR stack
may include a plurality of layers 112a-112d. In one embodiment,
layer 112a may be an anti-ferromagnetic layer (e.g., 200 .ANG.
IrMn); layer 112b may be a "pinned" layer (e.g., 25 .ANG. CoFe/8
.ANG. Ru/20 .ANG. CoFe); layer 112c may be a tunnel barrier (e.g.,
15 .ANG. Al.sub.2O.sub.3), and layer 112d may be a "free" layer
(e.g., 10 .ANG. CoFel 30 .ANG. NiFe). Portions of the TMR stack 112
are then removed (e.g., etched) in a conventional manner (e.g.,
using an Ion Beam Etch (IBE)), effective to form the structure
shown in FIG. 1E, wherein the remaining portion of the TMR stack
112 forms the bit region of an MRAM memory cell.
[0053] In the next step of the process flow, illustrated in FIG.
1F, an encapsulation layer 114, which may comprise a dielectric
material (e.g., SiO.sub.2), is deposited over the entire surface of
the device in a conventional manner. After the layer 114 is
deposited, a chemical mechanical polish may be performed to provide
the resulting structure illustrated in FIG. 1F.
[0054] In the next step of the process flow, illustrated in FIG.
1G, a conductive material (e.g., Cu or Al) is deposited over the
surface of the device, and is subsequently etched, to form a
current carrying line 116 (e.g., a word or bit line), which is
disposed in a substantially perpendicular relationship with line
110. Line 116 is formed over bit region 112, which is located
between line 110 and line 116. Line 116 may have generally the same
shape as line 110 (e.g., line 116 may have a rectangular cross
section).
[0055] In the next step of the process flow, illustrated in FIG.
1H, a top keeper layer 118 is deposited on top of the conductor
116, thereby forming MRAM device 120. The keeper layer 118 is
formed from an amorphous, soft magnetic material, which may be
substantially identical to the material that forms keeper layer
106. Particularly, in the preferred embodiment, the keeper layer
118 may be formed from an amorphous metallic alloy, such as CoZrX,
where X may be Ta, Nb, Pd and/or Rh. The keeper layer 118 may also
be formed by use of a PVD tool, in a process substantially similar
to the process used to form keeper 106, including the application
of a magnetic field during deposition. Keeper 118 is formed or
disposed generally around current carrying line 116 (e.g., in
relative close proximity to and/or adjacent to the top and side
walls of the current carrying line 116). In other embodiments,
keeper 118 may have a different shape, and in one example, keeper
118 may be adjacent only to the bottom of line 116. In the
preferred embodiment, the thickness "d" of the keeper 118 may be in
the range of 50 to 500 .ANG..
[0056] It should be appreciated that while a single MRAM device 120
is illustrated in FIGS. 1A-1H, the foregoing process may be used to
create multiple MRAM devices 120.
[0057] The use of amorphous soft magnetic alloys in the forgoing
fabrication process provides significant advantages over prior
materials and processes. Particularly, the amorphous soft magnetic
alloys have several unique advantages that support integration in a
multi-layer (e.g., dual damascene Copper/SiO.sub.2 or low-k)
metallization process, including: (i) excellent thermal stability
(e.g., crystallization temperature>450.degree. C.), making the
materials compatible with standard CMOS backend processing; (ii)
significant permeability up to the write frequencies required in
high speed memory devices (several GHz); and (iii) for some
amorphous soft magnetic allows, such as CoZrTa, the possibility to
eliminate or reduce the diffusion barrier layer.
[0058] In one embodiment of the present invention, one or more
shielding layers may be formed around the MRAM device to provide
shielding from external fields. FIG. 2 illustrates one non-limiting
embodiment of an MRAM device 200 including top and bottom shielding
layers 130, 134, respectively, which are formed from amorphous soft
magnetic materials. As shown in FIG. 2, shielding layers 130, 134
are disposed in relative close proximity to and/or adjacent to the
top and bottom of the MRAM device 200. Particularly, shielding
layer 130 is disposed above current carrying line 116, and
shielding layer 134 is disposed below current carrying line 116.
MRAM device 200 includes many of the same elements as MRAM device
120, as indicated by those elements having identical reference
numerals. MRAM device 200 may be formed by continuing the process
flow from FIG. 1H, and depositing the top and bottom shielding
layers on device 120 in any order. In the preferred embodiment, a
dielectric layer 132 (e.g., SiO.sub.2) is deposited on top of
keeper 118, and the top shielding layer 130 is deposited on top of
dielectric layer 132. The bottom shielding layer 134 may be
deposited directly below substrate 100.
[0059] The shielding layers 130, 134 may be formed by use of a
Physical Vapor Deposition (PVD) or sputtering process, which may be
performed in a conventional PVD cluster tool in the presence of a
magnetic field. In the preferred embodiment, the thickness "d" of
the shielding layers may be in the range of 0.1.mu.m to 10 .mu.m.
In one embodiment, the thickness "d" of the shielding layers is
approximately 1 .mu.m. One example of process conditions that may
be used in a known PVD tool to deposit a particular amorphous soft
magnetic alloy (i.e., Co.sub.91.5Zr.sub.4Ta.sub.4.5) are
illustrated in table 500 of FIG. 5.
[0060] The amorphous soft magnetic shielding layers 130, 134 will
prevent stray flux from reaching and/or affecting the bit region
112 of the MRAM cell.
[0061] In another embodiment of the present invention, one or more
shielding layers may be formed between MRAM cells at different
levels of a multilevel MRAM device. FIG. 3 illustrates one
non-limiting embodiment of a multilevel MRAM device 300 including a
top level 120a and a bottom level 120b, which are separated by a
shielding layer 140, which is formed from an amorphous soft
magnetic material. MRAM device 300 includes many of the same
elements as MRAM device 120, as indicated by those elements having
identical reference numerals with the addition of an "a" or "b"
character to differentiate between top level device 120a and bottom
level device 120b. MRAM devices 120a, 120b may be formed in a
substantially similar manner as MRAM device 120. In the preferred
embodiment, bottom level device 120b is formed first. After the
bottom level device 120b is formed, a dielectric layer 142 (e.g.,
SiO.sub.2) is deposited on top of keeper 118b. The shielding layer
140 is deposited on top of dielectric layer 142.
[0062] The shielding layer 140 may be formed by use of a Physical
Vapor Deposition (PVD) or sputtering process, which may be
performed in a conventional PVD cluster tool in the presence of a
magnetic field. In the preferred embodiment, the thickness of the
shielding layer 140 may be in the range of 0.1 .mu.m to 10 .mu.m.
In one embodiment, the thickness "d" of the shielding layer 140 is
approximately 1 .mu.m. The process conditions that may be used in a
PVD tool to deposit the shielding layer 140 may be substantially
identical to those used to deposit shielding layers 130, 134.
[0063] After shielding layer 140 is formed, a dielectric layer 144
(e.g., SiO.sub.2) may be deposited on top of layer 140. Top level
device 120a may then be formed on top of dielectric layer 144. The
soft magnetic shielding layer(s) 140 will substantially prevent all
magnetic fields generated during the writing of one level from
affecting the state of the other level(s), thereby avoiding
erroneous reading and writing.
[0064] It has been shown that amorphous soft magnetic films, such
as CoZrTa films, deposited by conventional Physical Vapor
Deposition (PVD) could be integrated in a standard multilevel
metallization flow, without loss of permeability. For example,
CoZrTa films have been found to have a high permeability (e.g.,
.mu..about.1000) up to the GHz frequency range. Since the typical
write pulses of an MRAM cell is on the order of 2 ns, this type of
soft magnetic layer will act as such for this kind of pulse
width.
[0065] It has further been found that such films can be made by
conventional DC-magnetron Physical Vapor Deposition (PVD) in the
presence of an external magnetic field. For example, from a
Co.sub.91.5Zr.sub.4Ta.sub.4.5 target at 3500 W power density, 5
mTorr of Ar pressure and 5 Amperes of current in the electromagnet
gave a deposition rate of 36 .ANG./s, sufficient for industrial
application in a high throughput manufacturing environment. These
films are found to be amorphous and display excellent soft magnetic
properties, as illustrated by the magnetization loop of FIG. 6.
Particularly, FIG. 6 illustrates a magnetization loop for a 2000
.ANG. CoZrTa film.
[0066] Hence, the use of amorphous soft magnetic materials for
shielding and keeper applications in MRAM devices provides
significant advantages over class (1) and class (2) materials. For
example, the amorphous soft magnetic materials display a much
higher crystallization temperature and are thus better suited for a
multi-layer MRAM fabrication process. The amorphous soft magnetic
materials also have significant permeability up to the write
frequencies required in high speed memory devices (several GHz).
Moreover, some amorphous soft magnetic alloys, such as CoZrTa,
allow for the elimination or reduction of a diffusion barrier
layer.
[0067] It should be understood that the inventions described herein
are provided by way of example only and that numerous changes,
alterations, modifications, and substitutions may be made without
departing from the spirit and scope of the inventions as delineated
within the following claims.
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