U.S. patent application number 12/174329 was filed with the patent office on 2009-02-26 for iii-nitride device.
Invention is credited to Michael A. Briere.
Application Number | 20090050939 12/174329 |
Document ID | / |
Family ID | 40259939 |
Filed Date | 2009-02-26 |
United States Patent
Application |
20090050939 |
Kind Code |
A1 |
Briere; Michael A. |
February 26, 2009 |
III-NITRIDE DEVICE
Abstract
A III-nitride device that includes a silicon body having formed
therein an integrated circuit and a III-nitride device formed over
a surface of the silicon body.
Inventors: |
Briere; Michael A.;
(Woonsocket, RI) |
Correspondence
Address: |
OSTROLENK FABER GERB & SOFFEN
1180 AVENUE OF THE AMERICAS
NEW YORK
NY
100368403
US
|
Family ID: |
40259939 |
Appl. No.: |
12/174329 |
Filed: |
July 16, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60950261 |
Jul 17, 2007 |
|
|
|
60990142 |
Nov 26, 2007 |
|
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Current U.S.
Class: |
257/201 ;
257/E29.091 |
Current CPC
Class: |
H01L 29/7786 20130101;
H01L 29/42316 20130101; H01L 21/8258 20130101; H01L 29/4175
20130101; H01L 29/2003 20130101; H01L 27/0617 20130101; H01L
29/66462 20130101; H01L 27/0688 20130101; H01L 29/045 20130101 |
Class at
Publication: |
257/201 ;
257/E29.091 |
International
Class: |
H01L 29/205 20060101
H01L029/205 |
Claims
1. A semiconductor device, comprising: a support substrate that
includes a silicon body having an integrated circuit formed
therein; and a III-nitride body comprising a III-nitride
semiconductor device formed over a surface of said silicon
body.
2. The device of claim 1, wherein said III-nitride body includes a
III-nitride heterojunction comprised of a first III-nitride layer
of one band gap and a second III-nitride layer of another band gap
formed over said first III-nitride layer.
3. The device of claim 2, wherein said III-nitride body includes a
buffer layer interposed between said III-nitride heterojunction and
said silicon body.
4. The device of claim 1, further comprising another silicon body
and an insulation body interposed between said silicon body and
said another silicon body.
5. The device of claim 4, wherein said silicon body is comprised of
(111) silicon.
6. The device of claim 4, wherein said another silicon body is
comprised of (111) silicon.
7. The device of claim 4, wherein said another silicon body is
comprised of (100) silicon.
8. The device of claim 4, wherein said insulation body is comprised
of silicon dioxide.
9. The device of claim 4, wherein said insulation body is between
0.1 to 2 microns thick.
10. The device of claim 4, wherein said insulation body is about
0.5 microns thick.
11. The device of claim 4, wherein said insulation body binds said
first silicon body to said second silicon body.
12. The device of claim 4, wherein said silicon body is N++
doped.
13. The device of claim 4, wherein said silicon body is P++
doped.
14. The device of claim 1, wherein said silicon body includes an
epitaxially formed portion.
15. The device of claim 1, wherein said III-nitride body includes a
power semiconductor device and said integrated circuit formed in
said silicon body comprises logic devices for operating said power
semiconductor device.
16. The device of claim 15, further comprising a via through said
III-nitride body reaching said silicon body, and a conductor
disposed within said via connecting an electrode of said power
semiconductor device to said another silicon body.
17. The device of claim 1, further comprising an insulation body
formed over said silicon body and said III-nitride body, said
insulation body including a via, said via including a conductive
body connecting said IC to said III-nitride body.
Description
RELATED APPLICATION
[0001] This application is based on and claims priority to U.S.
Provisional Application Ser. No. 60/950,261, filed on Jul. 17,
2007, entitled Monolithic Si IC and GaN FET Using Vias, and U.S.
Provisional Application Ser. No. 60/990,142, filed on Nov. 26,
2007, entitled III-Nitride Wafer and Devices Formed in a
III-Nitride Wafer, to which claims of priority are hereby made and
the disclosures of which are incorporated by reference.
DEFINITION
[0002] III-nitride as used herein refers to a semiconductor alloy
from the InAlGaN system that includes nitrogen and at least one
element from Group III such as, but not limited to, GaN, AlGaN,
InN, AlN, InGaN, InAlGaN and the like.
BACKGROUND AND SUMMARY OF THE INVENTION
[0003] The present invention relates to III-nitride device
technology.
[0004] III-nitride, because of its high bandgap, is suitable for
high voltage power applications. According to a known design, a
III-nitride power device may be fabricated by forming a III-nitride
heterojunction over a silicon substrate.
[0005] It is also known that integrated circuits for driving power
devices such as III-nitride power devices can be formed in silicon
using, for example, CMOS technology.
[0006] Given the desire to lower power consumption and/or increase
switching speed by reducing interconnection inductance and
resistance, it is desirable to position, for example, an integrated
driver circuit (IC) close to a power device.
[0007] In a device according to present invention an IC is formed
in a silicon body a surface of which also serves as a substrate for
a III-nitride device, such as a III-nitride power device. The IC
and the power device can be then operatively coupled, whereby an
integrated device may be obtained.
[0008] Other features and advantages of the present invention will
become apparent from the following description of the invention
which refers to the accompanying drawings.
BRIEF DESCRIPTION OF THE FIGURES
[0009] FIG. 1 illustrates a cross-sectional view of a first
embodiment of the present invention.
[0010] FIG. 2 illustrates a cross-sectional view of a semiconductor
wafer for the fabrication of a device according to other
embodiments of the present invention.
[0011] FIG. 3 illustrates a cross-sectional view of another
III-nitride device according to the second embodiment of the
present invention.
[0012] FIG. 4 illustrates a cross-sectional view of a third
embodiment of a device according to the present invention.
[0013] FIG. 5 illustrates a cross-sectional view of a fourth
embodiment of a device according to the present invention.
DETAILED DESCRIPTION OF THE FIGURES
[0014] An integrated device according to the present invention
includes a silicon body in which one or more IC logic devices are
formed and a III-nitride power semiconductor device formed over a
surface of the silicon substrate and preferably operatively coupled
to at least one of the IC logic devices.
[0015] Referring to FIG. 1, an integrated semiconductor device
according to a first embodiment of the present invention includes
an IC semiconductor logic device 32 formed in a silicon body 16,
and a III-nitride power semiconductor device 12 formed over a major
surface of silicon body 16. Note that IC device 32 is preferably
positioned laterally to the III-nitride power device 12. In the
preferred embodiment, III-nitride semiconductor device 12 may be a
heterojunction power device having a schottky or an insulated gate
such as a HEMT (high electron mobility transistor) examples of
which are disclosed in U.S. Patent Application Publication No.
2006/0060871 and U.S. Pat. No. 5,192,987 or a III-nitride FET. IC
semiconductor logic device 32 may be a silicon based driver or the
like integrated circuit for driving III-nitride device 12.
[0016] According to an aspect of the present invention, an
insulation body 40 (e.g., an oxide body such as SiO.sub.2) is
formed over IC semiconductor logic device 32 as well as III-nitride
device 12. One or more vias 42 are opened in insulation body 40,
each via 42 including a conductive (e.g. metal) filler 44 leading
from an electrode of IC semiconductor logic device 32 to at least
one electrode of III-nitride device 12. Thus, for example, a via 42
may lead from the gate electrode of III-nitride device 12 to an
electrode of IC device 32 that supplies drive signals to the gate
electrode.
[0017] To fabricate a device according to the present invention,
first a semiconductor body 16 is prepared to serve as a substrate
for III-nitride device 12. Thereafter, a III-nitride body 20 (e.g.
AlN) is formed over silicon body 16 using any desired technique.
III-nitride body 20 may serve as a buffer layer or a transition
layer.
[0018] Next, IC semiconductor logic device 32 is formed in silicon
body 16 on a different plane lateral to III-nitride body 20, and
then the rest of III-nitride device 12 is formed on III-nitride
body 20 on silicon body 16. Thus, for example, a III-nitride
heterojunction device such as a high electron mobility transistor
may be formed by growing an active body 21 that includes an active
III-nitride heterojunction over buffer layer 20. Alternatively, a
III-nitride FET may be formed over III-nitride body 20.
[0019] Thereafter, insulation body 40 is formed and then planarized
using, for example, CMP. Vias 42 are next opened in body 40 using
any desired method and filled with conductors 44 to connect IC 32
and III-nitride device 12 to complete a device according to the
present invention. Vias 42 may be 1-5 .mu.m wide.
[0020] Note that the present invention is not limited to one
III-nitride body 20, but multiple III-nitride bodies 20 each for at
least one III-nitride device 12 can be provided without departing
from the scope and spirit of the present invention.
[0021] Referring to FIG. 2, a semiconductor wafer used for
fabrication of a device according to the second embodiment of the
present invention includes a support substrate 10 and a III-nitride
semiconductor body 12 formed over support substrate 10.
[0022] According to an aspect of the present invention, support
substrate 10 includes a first silicon body 14, a second silicon
body 15 and an insulation body 18 interposed between first silicon
body 14 and second silicon body 18. In one embodiment, first
silicon body 14 may be a <111> single crystal silicon, second
silicon body may be <111> single crystal silicon, and
insulation body 18 may be silicon dioxide. In another embodiment,
first silicon body 14 may be <100> silicon, second silicon
body 15 may be <111> silicon, and insulation body 18 may be
silicon dioxide.
[0023] In both embodiments, an SOI (silicon on insulator) substrate
is suitable. Such substrates include two silicon substrates bonded
to one another by a silicon dioxide layer. The first embodiment can
also be realized by a SiMox process whereby implantation of oxygen
into a <111> silicon substrate followed by an annealing step
forms an insulation body 18 made of silicon dioxide between a first
<111> silicon body 14 and a second <111> silicon body
15. Note that second silicon body 15 may optionally include an
epitaxially grown layer thereon. Furthermore, note that other than
SiMox, or silicon bonded to silicon, other methods can be used to
realize a device according to the present invention.
[0024] III-nitride semiconductor device 12 includes, in one
preferred embodiment, a III-nitride buffer layer 20 (e.g. AlN),
over second silicon body 15, and a III-nitride heterojunction
formed over III-nitride buffer layer 20, that includes a first
III-nitride layer 22 having one band gap (e.g. GaN) and a second
III-nitride layer 24 having another band gap (e.g. AlGaN, InAlGaN,
InGaN, etc.) formed over first layer 22. The composition and/or the
thickness of first and second III-nitride layers 22 and 24 are
selected to result in the formation of a carrier rich region
referred to as a two-dimensional electron gas (2-DEG) near the
heterojunction thereof.
[0025] According to one aspect of the present invention, the
III-nitride heterojunction can be used as the current carrying
region of a III-nitride power semiconductor device (e.g. a high
electron mobility transistor).
[0026] Referring to FIG. 3, a III-nitride high electron mobility
transistor may include first and second power electrodes 26, 28
(e.g. source and drain electrodes) coupled to the 2-DEG through
second III-nitride layer 24 and gate arrangements 30 each disposed
between a respective first power electrode 26 and second power
electrode 28. A gate arrangement may include an insulated gate
electrode or a gate electrode that makes Schottky contact to second
III-nitride layer 24.
[0027] In a device according to the first embodiment, active body
21 residing on buffer layer 20 may include a III-nitride
heterojunction formed over III-nitride buffer layer 20, that
includes a first III-nitride layer 22 having one band gap (e.g.
GaN) and a second III-nitride layer 24 having another band gap
(e.g. AlGaN, InAlGaN, InGaN, etc.) formed over first layer 22. The
composition and/or the thickness of first and second III-nitride
layers 22 and 24 are selected to result in the formation of a
carrier rich region referred to as a two-dimensional electron gas
(2-DEG) near the heterojunction thereof. Furthermore, body 21 may
include first and second power electrodes 26, 28 (e.g. source and
drain electrodes) coupled to the 2-DEG through second III-nitride
layer 24 and gate arrangements 30 each disposed between a
respective first power electrode 26 and second power electrode 28.
A gate arrangement may include an insulated gate electrode or a
gate electrode that makes Schottky contact to second III-nitride
layer 24. Thus, a III-nitride device 12 in the first embodiment may
include features similar to those in the second embodiment.
[0028] In a device according to the second embodiment,
semiconductor devices 32 may be formed in second silicon body 15.
In one preferred embodiment, semiconductor devices 32 may be logic
devices formed using CMOS technology for the purpose of operating
the III-nitride device 12. For example, semiconductor devices 32
may be part of a driver circuit for driving III-nitride device 12.
Note that in the second embodiment semiconductor devices 32 are
disposed directly below III-nitride power device 12.
[0029] Referring now to FIG. 4, according to the third embodiment,
a via 34 that extends from the top of second III-nitride layer 24
to, for example, first silicon body 14 may be provided to allow for
electrical communication between one of the power electrodes 28
(e.g. source or drain) and first silicon body 14. Via 34 may
include an insulation body 36 on the walls thereof, and an
electrically conductive body 38 (e.g. a metallic body or conductive
semiconductor body such as polysilicon) connecting electrode 28 to
first silicon body 14.
[0030] Referring now to FIG. 5, in which like numerals identify
like feature, in a device according to the fourth embodiment of the
present invention, a portion of the III-nitride body 12 is removed
to expose an area of second silicon body 15. Semiconductor devices
32 are formed in the exposed area of second silicon body 15 lateral
to the III-nitride power device 12, rather than being disposed
directly below the III-nitride power semiconductor device 12.
[0031] A wafer used in a device according to the present invention
can be used to devise power devices for high voltage applications
because of the presence of insulation body 18, which reduces
leakage current into the substrate and improves the breakdown
voltage of the device. For example, when insulation body 18 is
silicon dioxide, its thickness can be 0.1 to 2 microns to increase
the breakdown voltage of the device. In one embodiment, for
instance, silicon body 18 may be about 0.5 microns thick for a
700-1000 volt III-nitride power device.
[0032] Note further that silicon body 14 and/or silicon body 15 may
be doped with N-type dopants or P-type dopants. Thus, silicon
bodies 14, 16 may be N++ doped or P++ doped. N++ doped or P++ doped
first silicon body can improve the breakdown capability of the
device by taking advantage of the resurf effect.
[0033] Although the present invention has been described in
relation to particular embodiments thereof, many other variations
and modifications and other uses will become apparent to those
skilled in the art. It is preferred, therefore, that the present
invention be limited not by the specific disclosure herein, but
only by the appended claims.
* * * * *