U.S. patent application number 12/176099 was filed with the patent office on 2009-01-22 for structures of and methods for forming vertically aligned si wire arrays.
Invention is credited to Harry A. Atwater, Michael A. Filler, Brendan M. KAYES, Nathan S. Lewis.
Application Number | 20090020853 12/176099 |
Document ID | / |
Family ID | 40260402 |
Filed Date | 2009-01-22 |
United States Patent
Application |
20090020853 |
Kind Code |
A1 |
KAYES; Brendan M. ; et
al. |
January 22, 2009 |
STRUCTURES OF AND METHODS FOR FORMING VERTICALLY ALIGNED Si WIRE
ARRAYS
Abstract
A structure consisting of vertically aligned wire arrays on a Si
substrate and a method for producing such wire arrays. The wire
arrays are fabricated and positioned on a substrate with an
orientation and density particularly adapted for conversion of
received light to energy. A patterned oxide layer is used to
provide for wire arrays that exhibit narrow diameter and length
distribution and provide for controlled wire position.
Inventors: |
KAYES; Brendan M.; (Los
Angeles, CA) ; Filler; Michael A.; (Pasadena, CA)
; Lewis; Nathan S.; (La Canada, CA) ; Atwater;
Harry A.; (South Pasadena, CA) |
Correspondence
Address: |
Steinfl & Bruno
301 N Lake Ave Ste 810
Pasadena
CA
91101
US
|
Family ID: |
40260402 |
Appl. No.: |
12/176099 |
Filed: |
July 18, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60961170 |
Jul 19, 2007 |
|
|
|
60961169 |
Jul 19, 2007 |
|
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Current U.S.
Class: |
257/618 ;
257/E21.09; 257/E29.005; 438/478 |
Current CPC
Class: |
H01L 21/02381 20130101;
H01L 31/04 20130101; H01L 21/02603 20130101; H01L 31/1804 20130101;
B82Y 30/00 20130101; Y02E 10/547 20130101; H01L 21/0262 20130101;
H01L 21/02532 20130101; H01L 31/035272 20130101; Y02P 70/50
20151101; H01L 21/02645 20130101; H01L 21/02639 20130101; H01L
21/02653 20130101; Y02P 70/521 20151101; H01L 27/1446 20130101 |
Class at
Publication: |
257/618 ;
438/478; 257/E29.005; 257/E21.09 |
International
Class: |
H01L 21/20 20060101
H01L021/20; H01L 29/06 20060101 H01L029/06 |
Goverment Interests
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
[0002] The U.S. Government has certain rights in this invention
pursuant to Grant No. DE-FG02-03ER15483 awarded by DOE.
Claims
1. A structure comprising: an ordered array of crystalline Si
wires, wherein Si wires in a plurality of the crystalline Si wires
have diameter dimensions generally orthogonal to length dimensions
and wherein radii of the plurality of Si wires in the diameter
dimensions are roughly equal to the minority carrier diffusion
length of material comprising the Si wires.
2. The structure according to claim 1, wherein the plurality of Si
wires are generally oriented with a similar orientation in a
direction for reception of light energy.
3. The structure according to claim 2, further comprising a
substrate and wherein the plurality of Si wires contact the
substrate at first ends of the Si wires and second ends of the Si
wires are disposed to provide an orientation of vertical or near
vertical of the Si wires with respect to the substrate.
4. The structure according to claim 3, wherein the ordered array of
crystalline Si wires are distributed over an area on the substrate
greater that 1 cm.sup.2.
5. The structure according to claim 2, wherein the plurality of Si
wires have diameters greater than 1 .mu.m and lengths greater than
30 .mu.m.
6. The structure according to claim 2, wherein the plurality of Si
wires are disposed at spacings selected for optimal conversion of
received light to energy.
7. A method for fabricating vertically aligned Si wire arrays
comprising: forming a templating layer on a Si substrate;
patterning the templating layer with a plurality of holes extending
to the Si substrate; depositing a catalyst into one or more of the
holes in the templating layer; and growing wires on the substrate
at a temperature between 950.degree. C. to 1100.degree. C. and
applying a growth gas comprising SiCl.sub.4.
8. The method according to claim 7, wherein the temperature during
the wire growth is between about 1000.degree. C. to about
1050.degree. C.
9. The method according to claim 7, wherein the templating layer
has a thickness between about 285 nm to about 300 nm.
10. The method according to claim 7, wherein the templating layer
comprises an oxide layer and patterning the templating layer with a
plurality of holes comprises: applying a photoresist layer to the
oxide layer; patterning the photoresist layer with a desired
pattern of holes; and etching the oxide layer based on the desired
pattern of holes in the photoresist layer to form the plurality of
holes in the oxide layer.
11. The method according to claim 10, wherein depositing a catalyst
into the holes in the oxide layer comprises: thermally evaporating
the catalyst onto the photoresist layer and into the holes in the
oxide layer; and lifting-off the photoresist layer.
12. The method according to claim 7, wherein depositing a catalyst
comprises depositing a catalyst layer with a thickness to grow
wires with lengths and diameters selected for light to electricity
conversion.
13. The method according to claim 7, wherein the templating layer
is patterned with a square array of holes that are about 3 .mu.m in
diameter and are spaced apart by about 7 .mu.m center to
center.
14. The method according to claim 7, wherein forming a templating
layer comprises thermally growing an oxide layer on the Si
substrate.
15. The method according to claim 7 wherein the catalyst comprises
gold, copper, or nickel.
16. A method for fabricating semiconductor structures comprising:
forming a templating layer on a Si substrate; patterning the
templating layer with an array of holes extending to the Si
substrate; forming catalyst islands within one or more holes in the
array of holes; and growing semiconductor structures on the Si
substrate at a temperature between about 950.degree. C. to about
1050.degree. C. and applying a growth gas comprising
SiCl.sub.4.
17. The method according to claim 16, wherein the templating layer
comprises an oxide layer and the oxide layer has a thickness
between about 285 nm to about 300 nm.
18. The method according to claim 16, wherein the catalyst islands
comprise gold, copper, or nickel.
19. The method according to claim 16, wherein templating layer is
patterned with holes to produce wire arrays, wherein wires in the
wire arrays have diameters of about 1.5 .mu.m and the catalyst
islands comprise catalyst having a height of approximately 500
nm.
20. The method according to claim 16, further comprising removing
the templating layer after the semiconductor structures are grown
and removing residual catalyst left at the top of one or more of
the semiconductor structures.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application is related to and claims the benefit
of copending and commonly assigned U.S. Patent Application No.
60/961,170, titled "Fabrication of Wire Array Samples and
Controls," filed on Jul. 19, 2007, the entire contents of which are
incorporated herein by reference, and is related to and claims the
benefit of copending and commonly assigned U.S. Patent Application
No. 60/961,169, titled "Growth of Vertically Aligned Si Wire Arrays
Over Large Areas (>1 cm.sup.2) with Au and Cu Catalysts," filed
on Jul. 19, 2007, the entire contents of which are incorporated
herein by reference.
BACKGROUND
[0003] 1. Field
[0004] This disclosure relates to Si wire arrays. More
specifically, the present disclosure describes structures of
vertically oriented Si wire arrays and methods for forming such
arrays.
[0005] 2. Description of Related Art
[0006] Well-defined wire arrays have been produced using
lithographic patterning followed by anisotropic etching, but such
methods typically require large areas of high-quality substrate
materials. See, for example, Z. Huang, H. Feng, and J. Zhu, Adv.
Mater. (Weinheim, Ger.) 19, 744 (2007).
[0007] Wires of various materials have also been grown `bottom up`
by the vapor-liquid-solid (VLS) process. See, for example, R. S.
Wagner and W. C. Ellis, Appl. Phys. Lett. 4, 89 (1964). Control of
the size and position of VLS-grown wires has been demonstrated,
particularly in the case of Si, by patterning of a surface oxide.
See, for example, E. I. Givargizov, Highly Anisotropic crystals (D.
Reidel, Dordrecht, Holland, 1987), p. 169; T. Martensson, M.
Borgstrom, W. Seifert, B. J. Ohlsson, and L. Samuelson,
Nanotechnology 14, 1255 (2003); J. Westwater, D. P. Gosain, and S.
Usui, Jpn. J. Appl. Phys., Part 1 36, 6204 (1997); T. Kawano, Y.
Kato, M. Futagawa, H. Takao, K. Sawada, and M. Ishida, Sens.
Actuators, A 97, 709 (2002); B. M. Kayes, J. M. Spurgeon, T. C.
Sadler, N. S. Lewis, and H. A. Atwater, Proceedings of the Fourth
IEEE WCPEC, 2006, Vol. 1, p. 221. Wire array growth, typically, has
only been achieved over relatively small areas, unless a template
is used. See, for example, T. Shimizu, T. Zie, J. Nishikawa, S.
Shingybara, S. Senz, and U. Gosele, Adv. Mater. (Weinheim, Ger.)
19, 917 (2007). Wire array growth by some methods may result in a
random distribution of wires on a substrate and/or where the wires
have random orientations with respect to each other. Such wire
arrays may have an appearance that may be characterized as similar
to felt or felt-like.
SUMMARY
[0008] Embodiments of the present invention comprise relatively
dense arrays of Si wires with dimensions particularly adapted for
reception and conversion of light to energy. Preferred embodiments
are arrays of crystalline Si wires of a length long enough to
absorb sunlight fully, where the wires have radii matched to their
diffusion length, and are regularly spaced and oriented
predominantly vertically. Embodiments of the present invention also
provide that such arrays may be fabricated preferably over large
areas.
[0009] According to embodiments of the present invention,
vertically aligned wire arrays may be formed by patterning a
templating layer with an array of holes on a substrate. The
templating layer serves as a diffusion barrier for a growth
catalyst and provides a template for structures to be grown. A
growth catalyst, such as gold, copper or nickel, is deposited into
the holes. Growth of wires on the substrate is accomplished by
heating the substrate and applying a growth gas, such as
SiCl.sub.4. Wires will grow from the substrate under the catalyst
that is deposited in the holes. Use of a templating layer, such as
a patterned oxide layer, produces nearly defect-free arrays that
exhibit an extremely narrow diameter and length distribution, and
highly controlled wire position.
[0010] One embodiment of the present invention is a structure
comprising: an ordered array of crystalline Si wires, where the Si
wires in a plurality of the crystalline Si wires have diameter
dimensions generally orthogonal to length dimensions and where
radii of the plurality of Si wires in the diameter dimension are
roughly equal to the minority carrier diffusion length of the
material comprising the Si wires. Preferably, the Si wires are
oriented in a direction for the reception of light energy and have
spacings that are optimal for the reception of light energy.
[0011] Another embodiment of the present invention is a method for
fabricating vertically aligned Si wire arrays, where the method
comprises: forming a templating layer on a Si substrate; patterning
the templating layer with a plurality of holes extending to the Si
substrate; depositing a catalyst into one or more of the holes in
the oxide layer; and growing wires on the substrate at a
temperature between 850.degree. C. to 1100.degree. C. and applying
a growth gas comprising SiCl.sub.4.
[0012] Still another embodiment is a method for fabricating
semiconductor structures, where the method comprises: forming a
templating layer on a Si substrate; patterning the templating layer
with an array of holes extending to the Si substrate; forming
catalyst islands within one or more holes in the array of holes;
and growing semiconductor structures on the Si substrate at a
temperature between about 950.degree. C. to about 1050.degree. C.
and applying a growth gas comprising SiCl.sub.4.
[0013] Still another embodiment of the present invention is a
method for fabricating vertically aligned wire arrays for solar
energy conversion, where the method comprises: forming a templating
layer on a Si substrate; patterning the templating layer with a
plurality of holes extending to the substrate; depositing a
catalyst into one or more of the holes in the templating layer;
growing wires on the substrate at a temperature between 850.degree.
C. to 1100.degree. C. and applying a growth gas comprising
SiCl.sub.4, where a plurality of the grown wires have aspect ratios
providing optimal or near optimal conversion of solar energy to
electricity.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS
[0014] FIGS. 1A-1I show a method for fabricating wire arrays.
[0015] FIGS. 2A-2C show scanning electron microscopy view of an
Au-catalyzed Si wire array.
[0016] FIG. 3 shows a transmission electron microscopy picture of
an Au-catalyzed Si wire.
[0017] FIG. 4 shows a tilted SEM view of a Cu-catalyzed Si wire
array.
[0018] FIG. 5 shows representative tilted SEM images of regions
near each of the four corners of a Cu-catalyzed Si wire array.
[0019] FIG. 6 shows the effect of a high temperature anneal on Au
arrays with and without a 300 nm oxide buffer layer.
[0020] FIGS. 7A and 7B show top-down and tilted SEM views of
Au-catalyzed Si wire growth at higher temperatures.
[0021] FIG. 8 shows an I-V measurement for an individually
contacted nanowire using a four-point probe technique.
DETAILED DESCRIPTION
[0022] Within this description, the terms "wires," "rods,"
"whiskers," and "pillars" and other similar terms may be used
synonymously, except as otherwise indicated. Generally, these terms
refer to elongate structures which have lengths and widths, where
the length is defined by the longest axis of the structure and the
width is defined by the axis generally normal to the longest axis
of the structure. The term `aspect ratio` refers to the ratio of a
structure's length to its width. Hence, the aspect ratios of the
elongate structures will greater than one. The terms "ball,"
"spheroid," "blob" and other similar terms may also be used
synonymously, except as otherwise indicated. Generally, these terms
refer to structures with the width defined by the longest axis of
the structure and the length defined by the axis generally normal
to the width. Hence, the aspect ratio of such structures will
generally be unity or less than unity. Further the term "vertical"
with reference to wires, rods, whiskers, pillars, etc., generally
refers to structures that have a length direction that is elevated
somewhat from horizontal. The term "vertical alignment" generally
refers to an alignment or orientation of a structure or structures
that is elevated from horizontal. The structure or structures do
not have to be completely normal to horizontal to be considered to
have a vertical alignment. The term "array" generally refers to
multiple numbers of structures distributed within an area and
spaced apart, unless otherwise indicated. Structures within an
array all do not have to have the same orientation. The terms
"vertically aligned array" or "vertically oriented array" generally
refer to arrays of structures where the structures have
orientations elevated from a horizontal orientation up to
orientations completely normal to a horizontal orientation, but the
structures within the array may or may not have all the same
orientations with respect to horizontal. The terms "ordered" or
"well-defined" generally refer to the placement of elements in a
specified or predetermined pattern where the elements have distinct
spatial relationships to one another. Hence, the terms "ordered
array" or "well-defined" generally refer to structures distributed
within an area with distinct, specified or predetermined spatial
relationships to one another. For example, the spatial
relationships within an ordered array may be such that the
structures are spaced apart from one another by generally equal
distances. Other ordered arrays may use varying, but specified or
predetermined, spacings. The structures within "ordered" or
"well-defined" arrays may also have similar orientations with
respect to each other.
[0023] Within this description, the term "semiconductor" is
generally used to refer to elements, structures, or devices, etc.
comprising materials that have semiconductive properties, unless
otherwise indicated. Such materials include, but are not limited
to: elements from Group IV of the periodic table: materials
including elements from Group IV of the period table; materials
including elements from Group III and Group V of the periodic
table; materials including elements from Group II and Group VI of
the periodic table; materials including elements from Group I and
Group VII of the periodic table; materials including elements from
Group IV and Group VI of the periodic table; materials including
elements from Group V and Group VI of the periodic table; and
materials including elements from Group II and Group V of the
periodic table. Other materials with semiconductive properties may
include: layered semiconductors; metallic alloys; miscellaneous
oxides; some organic materials, and some magnetic materials. The
term "semiconductor structure" refers to a structure consisting of,
at least in part, semiconductor material. A semiconductor structure
may comprise either doped or undoped material.
[0024] Embodiments of the present invention comprise wire arrays or
other semiconductor structures with control of the size, position,
and uniformity of the fabricated wire arrays or structures over a
relatively wide area. Such wire arrays or structures comprise
crystalline Si wires of a length long enough to absorb sunlight
fully, each wire with a radius matched to its diffusion length, and
the wires being regularly spaced, and oriented predominantly
vertically, preferably over large areas. Embodiments of the present
invention may comprise growing the wire arrays or structures
through VLS processes. As shown in FIGS. 1A-1I and described in
additional detail below, a templating layer is first patterned with
openings (e.g., an array of holes) in which the wires or structures
are to be grown. The templating layer comprises a diffusion barrier
for a deposited catalyst. The diffusion barrier may comprise a
patterned oxide layer, a patterned insulating layer, such as a
layer comprising silicon nitride, a patterned metal layer, or
combinations of these materials or other materials or processes
that facilitate the deposition of the catalyst for semiconductor
structure growth. The catalyst is then deposited in the openings.
Wires or structures are then grown on the substrate by heating the
substrate and applying a growth gas.
[0025] According to an embodiment of the present invention, a Si
<111> wafer is used as the material from which the wire
arrays are grown. Other materials may also be used to support wire
growth, such as a thin Si layer disposed on glass, or other such Si
substrates. All or portions of the wafer may be doped. For example,
some embodiments may use a degenerately doped n-type Si wafer. As
shown in FIG. 1A, a surface oxide layer 20 is thermally gown on the
wafer 10. In one embodiment, the surface oxide layer is grown to a
thickness of 285 nm. In another embodiment, the surface oxide layer
20 is grown to a thickness of 300 nm. Other embodiments may
comprise oxide layers at other thicknesses. Still other embodiments
have the oxide layer 20 deposited via chemical vapor deposition
(CVD) or other methods known in the art.
[0026] As shown in FIG. 1B, a photoresist layer 30 is applied. The
photoresist layer is applied to support the development of a
patterned template as discussed below. However, other materials and
techniques for creating a patterned template may be used, such as a
latex layer, or stamping or soft lithography. The photoresist layer
may comprise S1813 photoresist from MicroChem Corp. (Newton, Mass.,
USA) or other photoresist material. The photoresist layer 30 is
then exposed to a desired array pattern and developed with a
developer to form a desired pattern of holes 35 in the resist layer
30 as shown in FIG. 1C. The developer may comprise MF-319 or other
developers known in the art. The patterned resist layer 30 is then
used to etch the oxide layer 20 on the Si wafer 10 as shown in FIG.
1D. Etching of the oxide layer may be achieved by using
hydrofluoric acid compositions such as buffered HF (9% HF, 32%
NH.sub.4F) from Transene Company, Inc. (Danvers, Mass., USA). Other
etching techniques known in the art may also be used to etch the
oxide layer 20. The result of the etching will be a pattern of
holes 37 in the oxide layer as shown in FIG. 1D. A preferred
pattern of holes may be a square array of 3 .mu.m diameter holes
that are 7 .mu.m center to center.
[0027] A growth catalyst 50 is then thermally evaporated onto the
resist layer 30 and into the holes 37 in the oxide layer 20 as
shown in FIG. 1E. Other methods of depositing the catalyst may be
used, such as electrodeposition. Preferred catalysts comprise gold,
copper, or nickel, but other metals known in the art as Si V-L-S
catalysts may be used, such as platinum or aluminum. For example,
500 nm of gold may be thermally evaporated onto the resist layer 30
and into the holes 37. Lift-off of the photoresist layer 30 is then
performed, leaving catalyst islands 57 separated by the oxide in
the oxide layer 20 as shown in FIG. 1F.
[0028] The wafer 10 with the patterned oxide layer 20 and the
deposited catalyst may then be annealed. Preferably, the annealing
is performed in a tube furnace at a temperature between 900 to
1000.degree. C. or at a temperature of about 1050.degree. C. for 20
minutes with the application of 1 atm of H.sub.2 at a flow rate of
1000 sccm (where SCCM denotes cubic centimeters per minute at STP).
Growth of wires on the wafer 10 is then performed. FIG. 1G shows
the growth of wires 40 in a wire array through the application of a
growth gas. Preferably, the wires 40 are grown in a mixture of
H.sub.2 (1000 sccm) and SiCl.sub.4 (20 sccm) at about 1 atm. In one
embodiment, the wires 40 may be grown for between 20 to 30 minutes
at temperatures between 850.degree. C. to 1100.degree. C. Other
embodiments may use different growth times, pressures, and or flow
rates. However, optimal growth temperatures are between
1000.degree. C. and 1050.degree. C. Growth for these times and at
these temperatures may produce wires from 10 .mu.m to 30 .mu.m in
length or longer.
[0029] Following the growth of the wires 40, the oxide layer 20 may
be removed, as shown in FIG. 1H. The oxide layer 20 may be removed
by etching the wafer 10 for 10 seconds in 10% HF (aq) or other
methods known in the art may be used to remove the oxide layer. As
shown in FIG. 1H, catalyst particles 51 may remain at the top of
each grown wire 40, which may impact the functionality of the
resulting wire array. Therefore, it may be advantageous to remove
the catalyst particles. For example, if the catalyst comprises Au,
the gold particles may be removed by soaking the wafer 10 for 10
min in a TFA solution from Transene Company, Inc., which contains
I.sup.-/I.sub.3.sup.-. Other methods known in the art may also be
used to remove catalyst particles. FIG. 1I shows the wires 40 with
the catalyst particles 51 removed.
[0030] The method described above has been shown to produce nearly
defect-free arrays that exhibited an extremely narrow diameter and
length distribution, and highly controlled wire position. FIG. 2A
shows an edge-on scanning electron microscopy (SEM) view of an
Au-catalyzed Si wire array produced using the method described
above. FIG. 2B shows a tilted view of the same array and FIG. 2C
shows a top-down view. The 100 .mu.m scale bar shown in FIG. 2C
also applies to FIGS. 2A and 2B. FIGS. 2A-2C also contain an inset
showing a magnified portion of the corresponding figure. The scale
bar in each inset is 10 .mu.m. As shown in FIGS. 2A-2C, the wire
growth was very uniform over areas >1 cm.sup.2. The growth
uniformity typically declined within several hundred microns of the
edges of the wafer (not shown in FIGS. 2A-2C), most likely due to
differences in temperature and/or gas flow at such locations.
[0031] FIG. 3 shows a transmission electron microscopy picture of
an Au-catalyzed Si wire that indicates that wires generated
according to the method described above are single crystalline and
grow along the <111> direction. The vertical lines in FIG. 3
are lattice fringes, and the horizontal bands are due to the curved
surface of the wire causing interference fringes. No crystal
defects were observed by TEM in the wires. From the image of FIG.
3, a lattice spacing of 0.307.+-.0.004 nm can be inferred,
consistent with growth in the <111> direction. This lattice
spacing, combined with the fact that the wires grew as single
crystals normal to a Si(111) wafer, is consistent with the growth
being in the <111> direction (the Si (111) lattice parameter
is .about.0.314 nm).
[0032] As discussed above, other catalysts may be used to
facilitate the growth of the Si wires in the wire array. Nominally
identical wire arrays may be obtained when Cu, Ni, Pt, or Al (or
other Si catalyst metals) are used as the VLS catalyst instead of
Au. FIG. 4 shows a tilted SEM view of a Cu-catalyzed Si wire array
produced using the method described above where the array has
nearly 100% fidelity over a large >1 cm.sup.2 area. The scale
bar in the inset in FIG. 4 is 10 .mu.m. FIG. 5 shows representative
tilted SEM images of regions near each of the four corners of a
0.5.times.1 cm sample grown at 1000.degree. C. with Cu catalyst,
illustrating the uniformity over large areas. The scale bar in FIG.
5 applies to all panels.
[0033] Use of the oxide layer 20 is particularly important to some
embodiments of the present invention. Attempts to grow Si wire
arrays did not yield high pattern fidelity when the catalyst was
not confined using the patterned oxide layer as described above.
Wires were grown by photolithographically patterning photoresist on
a clean Si <111> wafer, then exposing it for 5 s to buffered
HF (aqueous), followed by evaporation of 500 nm of Au and lift-off
of the resist. This was used to produce a square array of 3 .mu.m
diameter Au islands with a center-to-center pitch of 7 .mu.m.
Samples were then annealed in a tube furnace at 900-1000.degree. C.
for 20 min under 1 atm of H.sub.2 at a flow rate of 1000 SCCM,
followed by wire growth under 1 atm of H.sub.2 and SiCl.sub.4, at
flow rates of 1000 and 20 SCCM, respectively. This produced arrays
of low fidelity, with no control over the wire diameter or wire
position. Examination of the samples after a 20 min H.sub.2 anneal
only revealed that this behavior was due to substantial
agglomeration of the catalyst. FIG. 6 shows the effect of a 20 min
anneal in H.sub.2, at 1000.degree. C. and atmospheric pressure, on
Au arrays with and without a 300 nm oxide buffer layer,
demonstrating the importance of the buffer oxide in maintaining the
pattern fidelity. The scale bars in the insets are 10 .mu.m.
[0034] The growth of Si nanowires at 800-900.degree. C. with
SiCl.sub.4/H.sub.2 has been described in A. I. Hochbaum, R. Fan, R.
He, and P. Yang, Nano Lett. 5, 457 (2005) and I. Lombardi, A. I.
Hochbaum, P. Yang, C. Carraro, and R. Maboudian, Chem. Mater. 18,
988 (2006). In embodiments of the present invention, the thickness
of catalyst is proportional to the diameter of the wires being
grown, so 500 nm of catalyst material produced .about.1.5 .mu.m
diameter Si wires. This relatively thick catalyst layer, and/or the
higher growth temperatures, led to a significant problem with
catalyst migration if a buffer oxide was not present on the
surface, in contrast to the Hochbaum and Lombardi references in
which much thinner catalyst layers were used.
[0035] The growth of Si microwires according to embodiments of the
present invention have optimal growth temperatures of
1000-1050.degree. C. At 950.degree. C. and below, the wires either
did not grow straight, grew intermittently straight with kinks, or
grew straight but not aligned normal to the substrate. At
1075.degree. C. and above, the wires grew straight and normal to
the substrate, but significant destruction of the surface oxide was
observed during the growth process, leading to a loss of the
pattern fidelity. See, for example, FIGS. 7A and 7B. FIG. 7A shows
a top-down and (inset) tilted SEM views of the Au-catalyzed Si wire
growth at 1075.degree. C. FIG. 7B shows a top-down and (inset)
titled SEM view of Au-catalyzed Si wire growth at 1100.degree. C.
The 100 .mu.m scale bar applies to both FIGS. 7A and 7B, and the
scale bars in the insets are 10 .mu.m. Both FIGS. 7A and 7B show
showing the breakdown in pattern fidelity due to the destruction of
surface oxide.
[0036] To characterize the electrical properties of the Si wires
produced according to an embodiment of the present invention,
four-point probe and field-effect measurements were performed on
individual wires in the arrays. For these measurements, the
as-grown wires were removed from the growth substrate by sonication
in isopropanol and were then deposited on a degenerately doped
silicon wafer that had been coated with 100 nm of Si.sub.3N.sub.4.
The four-probe electrodes were fabricated using photolithography,
followed by evaporation of 300 nm of Al and 900 nm of Ag, and
finally by lift-off of the resist. Annealed Al was observed to make
suitable ohmic contacts to the wires. Back-gated measurements
indicated that the as-grown wires were n type, with a resistivity
of 0.1-0.6 .OMEGA.cm, corresponding to dopant densities of
8.times.10.sup.15-5.times.10.sup.16 cm.sup.-3, assuming that the
carrier mobility in these wires is the same as that in bulk Si.
FIG. 8 shows an I-V measurement for an individually contacted
nanowire using the four-point probe technique. The wire resistance
for this sample was 50 k.OMEGA., corresponding to a doping level of
2.9.times.10.sup.16 cm.sup.-3. The inset in FIG. 8 is a SEM image
of the four-probe measurement device, viewed at 45.degree.. The
scale bar is 6 .mu.m.
[0037] A particular application for wire arrays fabricated
according to embodiments of the present invention is for the use of
such wire arrays in photo cells. Device analysis has shown that
photovoltaic efficiency is maximized in wire arrays when the mean
radius of the wires is comparable to the minority carrier diffusion
length. This is because of a trade-off between increased current
collection and the loss of open-circuit voltage due to the
increased junction and surface area. Diffusion of gold into bulk
silicon at the growth temperatures of 1000-1050.degree. C. leads to
carrier lifetimes of >1 ns, which combined with carrier
mobilities expected for the observed dopant densities, indicates
minority carrier diffusion lengths of .gtoreq.1 .mu.m. However, as
described above, embodiments of the present invention provide the
ability to grow relatively long wire arrays (greater than 30 .mu.m)
while maintaining a radius comparable to the minority diffusion
length (on the order of 1.5 .mu.m). Hence, embodiments of the
present invention provide wire arrays with aspect ratios
particularly suitable for use in solar cell apparatus. Further,
embodiments of the present invention provide for the ability to
have relatively dense arrays of wires, further improving the
ability of devices using such arrays to convert light to electrical
energy.
[0038] According to an embodiments of the present invention,
photolithography is a suitable method for enabling uniform arrays
of wires of diameters of .gtoreq.1 .mu.m to be grown over large
areas. In cost sensitive applications such as photovoltaics, it may
be desirable to employ lower-cost lithographic methods, and
embodiments of the present invention are readily extendable to
alternative patterning techniques such as nanoimprint
lithography.
[0039] Cost also motivates the use of non-Au catalysts for
embodiments according to the present invention. As indicated above,
Cu, Ni, Pt, or Al may be used as a catalyst for Si wire growth. Cu
is, unlike Au, an inexpensive, earth-abundant material, and,
therefore, of particular interest for such embodiments. Although Cu
is more soluble in Si than Au and is also a deep trap, Si solar
cells may be more tolerant of Cu contamination than of Au, and thus
diffusion lengths of at least microns even in the case of Cu
catalyzed growth can be expected.
[0040] As discussed above, embodiments of the present invention may
be used for the fabrication of photovoltaic or photoelectrochemical
cells. Other embodiments of the present invention may provide for
the fabrication of wire arrays for photonic crystals or other
devices or structures. Also, methods according to embodiments of
the present invention techniques may provide for making wire arrays
of materials that cannot currently be fabricated with top-down
methods. Embodiments of the present invention may also provide for
the fabrication of wire arrays or other structures for batteries,
solar cells, 3-D circuits, capacitors, or other devices and
apparatus where the highly regular vertically ordered and oriented
nature of wire arrays and other structures provided by these
embodiments are desired.
[0041] The foregoing Detailed Description of exemplary and
preferred embodiments is presented for purposes of illustration and
disclosure in accordance with the requirements of the law. It is
not intended to be exhaustive nor to limit the invention to the
precise form or forms described, but only to enable others skilled
in the art to understand how the invention may be suited for a
particular use or implementation. The possibility of modifications
and variations will be apparent to practitioners skilled in the
art. No limitation is intended by the description of exemplary
embodiments which may have included tolerances, feature dimensions,
specific operating conditions, engineering specifications, or the
like, and which may vary between implementations or with changes to
the state of the art, and no limitation should be implied
therefrom. This disclosure has been made with respect to the
current state of the art, but also contemplates advancements and
that adaptations in the future may take into consideration of those
advancements, namely in accordance with the then current state of
the art. It is intended that the scope of the invention be defined
by the Claims as written and equivalents as applicable. Reference
to a claim element in the singular is not intended to mean "one and
only one" unless explicitly so stated. Moreover, no element,
component, nor method or process step in this disclosure is
intended to be dedicated to the public regardless of whether the
element, component, or step is explicitly recited in the Claims. No
claim element herein is to be construed under the provisions of 35
U.S.C. Sec. 112, sixth paragraph, unless the element is expressly
recited using the phrase "means for . . . " and no method or
process step herein is to be construed under those provisions
unless the step, or steps, are expressly recited using the phrase
"comprising step(s) for . . . ."
* * * * *