U.S. patent application number 11/775086 was filed with the patent office on 2009-01-15 for semiconductor device with reduced capacitance tolerance value.
Invention is credited to Peter Baumgartner, Thomas Benetik, Philipp Riess.
Application Number | 20090014832 11/775086 |
Document ID | / |
Family ID | 40121665 |
Filed Date | 2009-01-15 |
United States Patent
Application |
20090014832 |
Kind Code |
A1 |
Baumgartner; Peter ; et
al. |
January 15, 2009 |
Semiconductor Device with Reduced Capacitance Tolerance Value
Abstract
A semiconductor device includes a capacitance, the numerical
value of which is relevant for a device function. The capacitance
is formed from a parallel connection of at least a first and a
second capacitor element, wherein the first and second capacitor
elements are formed in respective manufacturing steps that exhibit
uncorrelated process fluctuations.
Inventors: |
Baumgartner; Peter;
(Muenchen, DE) ; Riess; Philipp; (Muenchen,
DE) ; Benetik; Thomas; (Muenchen, DE) |
Correspondence
Address: |
SLATER & MATSIL LLP
17950 PRESTON ROAD, SUITE 1000
DALLAS
TX
75252
US
|
Family ID: |
40121665 |
Appl. No.: |
11/775086 |
Filed: |
July 9, 2007 |
Current U.S.
Class: |
257/532 ;
257/299; 257/E29.345 |
Current CPC
Class: |
H01L 27/0805 20130101;
H01L 23/5223 20130101; H01L 2924/0002 20130101; H01L 27/0688
20130101; H01L 2924/0002 20130101; H01L 2924/00 20130101 |
Class at
Publication: |
257/532 ;
257/299; 257/E29.345 |
International
Class: |
H01L 29/94 20060101
H01L029/94; H01L 29/00 20060101 H01L029/00 |
Claims
1. A semiconductor device, comprising a capacitance, the numerical
value of which is relevant for a device function, wherein the
capacitance comprises a parallel connection of at least a first
capacitor element and a second capacitor element, wherein the first
and second capacitor elements are formed in respective
manufacturing steps that exhibit uncorrelated process
fluctuations.
2. The semiconductor device of claim 1, wherein the capacitance
comprises a parallel connection of more than two capacitor
elements, wherein the capacitor elements are formed in respective
manufacturing steps that exhibit uncorrelated process
fluctuations.
3. The semiconductor device of claim 1, wherein a first capacitance
value of the first capacitor element and a second capacitance value
of the second capacitor element, to obtain a predetermined total
capacitance value, are selected such that a process tolerance of
the capacitance is minimized.
4. The semiconductor device of claim 3, wherein, if a first process
tolerance value is equal to a second process tolerance value, the
first capacitance value is selected equal to the second capacitance
value.
5. The semiconductor device of claim 2, wherein respective
capacitance values of the capacitor elements connected in parallel
and each having a respective capacitance tolerance value are, to
obtain a predetermined total capacitance value, selected such that
a tolerance value of a resulting capacitance is minimized.
6. The semiconductor device of claim 1, wherein the first capacitor
element comprises an MIM capacitor element and the second capacitor
element comprises a BEOL capacitor element.
7. The semiconductor device of claim 1, wherein the first capacitor
element comprises an MIM capacitor element and the second capacitor
element comprises an MOS capacitor element.
8. The semiconductor device of claim 1, wherein the first capacitor
element comprises an MIM capacitor element containing a first type
of dielectric layer and the second capacitor element comprises an
MIM capacitor element containing a second type of dielectric
layer.
9. The semiconductor device of claim 1, wherein the first capacitor
element comprises a sandwich-type BEOL capacitor element and the
second capacitor element comprises a GRID-type BEOL capacitor
element.
10. The semiconductor device of claim 1, wherein the first
capacitor element comprises a sandwich-type BEOL capacitor element
and the second capacitor element comprises a VPP-type BEOL
capacitor element.
11. The semiconductor device of claim 1, wherein the first
capacitor element comprises a GRID-type BEOL capacitor element and
the second capacitor element comprises a VPP-type BEOL capacitor
element.
12. The semiconductor device of claim 1, wherein the first
capacitor element comprises an MOS capacitor element containing a
first type of oxide layer and the second capacitor element
comprises an MOS capacitor element containing a second type of
oxide layer.
13. The semiconductor device of claim 2, wherein the first
capacitor element comprises an MIM capacitor element, the second
capacitor element comprises a BEOL capacitor element, and a third
capacitor element comprises an MOS capacitor element.
14. The semiconductor device of claim 2, wherein the respective
capacitor elements are MIM capacitor elements containing different
types of dielectric layers.
15. The semiconductor device of claim 2, wherein the respective
capacitor elements comprise different types of BEOL capacitor
elements selected from the group consisting of sandwich capacitor
elements, GRID capacitor elements, and VPP capacitor elements.
16. The semiconductor device of claim 2, wherein the respective
capacitor elements comprise MOS capacitor elements containing
different types of oxide layers.
17. The semiconductor device of claim 2, wherein the capacitance
comprises a parallel connection of at least two sandwich capacitor
elements, produced in different process steps, and at least two VPP
capacitor elements, produced in different process steps, of a BEOL
stack.
18. The semiconductor device of claim 2, wherein the capacitance
comprises a parallel connection of at least two BEOL capacitor
elements of different type and at least one MOS capacitor
element.
19. The semiconductor device of claim 2, wherein the capacitance
comprises a parallel connection of at least one BEOL capacitor
element and at least two MOS capacitor elements, the MOS capacitor
elements containing different types of oxide layers.
20. The semiconductor device of claim 6, wherein the first
capacitor element comprises at least one aluminum or copper layer
and at least one layer of a material selected from the group
consisting of TiN, TaN, ONO, SiO.sub.2, Ta.sub.2O.sub.5,
Al.sub.2O.sub.3, and HfO.
21. The semiconductor device of claim 7, wherein the first
capacitor element comprises a first aluminum layer forming a top
capacitor plate and a second aluminum layer forming a bottom
capacitor plate, the first capacitor further comprising at least
one layer of a material selected from the group consisting of TiN,
TaN, ONO, SiO.sub.2, Ta.sub.2O.sub.5, Al.sub.2O.sub.3, and HfO.
22. The semiconductor device of claim 6, wherein the second
capacitor element comprises a stack of sandwich metal layers.
23. The semiconductor device of claim 9, wherein the second
capacitor element comprises a stack of sandwich metal layers.
24. The semiconductor device of claim 11, wherein the second
capacitor element comprises a stack of sandwich metal layers.
25. The semiconductor device of claim 1, comprising a voltage
controlled oscillator wherein the numerical value of the
capacitance determines an oscillator frequency.
26. The semiconductor device of claim 1, comprising an
analog/digital converter wherein the numerical value of the
capacitance determines conversion characteristics.
27. The semiconductor device of claim 1, comprising a filter
portion wherein the numerical value of the capacitance determines a
filter characteristic.
28. A semiconductor voltage controlled oscillator, comprising a
capacitance the numerical value of which determines an oscillator
frequency, wherein the capacitance comprises a parallel connection
of at least a first and a second capacitor element, wherein the
first and second capacitor elements are formed in respective
manufacturing steps that exhibit uncorrelated process fluctuations,
and wherein a first capacitance value of the first capacitor
element and a second capacitance value of the second capacitor
element, to obtain a predetermined total capacitance value, are
selected such that a process tolerance of the capacitance is
minimized.
29. The semiconductor voltage controlled oscillator of claim 28,
wherein the first capacitor element comprises an MIM capacitor
element and the second capacitor element comprises a BEOL capacitor
element.
30. An analog/digital semiconductor converter, comprising a
capacitance the numerical value of which determines a converting
characteristic, wherein the capacitance comprises a parallel
connection of at least a first and a second capacitor element,
wherein the first and second capacitor elements are formed in
respective manufacturing steps that exhibit uncorrelated process
fluctuations, and wherein a first capacitance value of the first
capacitor element and a second capacitance value of the second
capacitor element, to obtain a predetermined total capacitance
value, are selected such that a process tolerance of the
capacitance is minimized.
31. The analog/digital semiconductor converter of claim 30, wherein
the first capacitor element comprises an MIM capacitor element and
the second capacitor element comprises a BEOL capacitor
element.
32. A semiconductor filter device, comprising a capacitance the
numerical value of which determines a filter characteristic,
wherein the capacitance comprises a parallel connection of at least
a first and a second capacitor element, wherein the first and
second capacitor elements are formed in respective manufacturing
steps which exhibit uncorrelated process fluctuations, and wherein
a first capacitance value of the first capacitor element and a
second capacitance value of the second capacitor element, to obtain
a predetermined total capacitance value, are selected such that a
process tolerance of the capacitance is minimized.
33. The semiconductor filter device of claim 32, wherein the first
capacitor element comprises an MIM capacitor element and the second
capacitor element comprises a BEOL capacitor element.
34. An MOS type semiconductor device, comprising a capacitance the
numerical value of that affects a device function, wherein the
capacitance comprises a parallel connection of at least a first and
second capacitor element, wherein the first capacitor element
comprises an MOS capacitor element and the second capacitor element
is formed in a manufacturing step that exhibits process
fluctuations that are uncorrelated to the process fluctuations of
MOS manufacturing steps, and wherein a first capacitance value of
the first capacitor element and a second capacitance value of the
second capacitor element, to obtain a predetermined total
capacitance value, are selected such that a process tolerance of
the capacitance is minimized.
35. The MOS type semiconductor device of claim 34, wherein the
second capacitor element comprises an MIM capacitor element.
36. The MOS type semiconductor device of claim 34, wherein the
second capacitor element comprises a BEOL capacitor element.
37. The MOS type semiconductor device of claim 34, wherein the
capacitance comprises a parallel connection of more than two
capacitor elements, wherein a first capacitor element is an MOS
capacitor element and the further capacitor elements are formed in
respective manufacturing steps that exhibit uncorrelated process
fluctuations with the MOS manufacturing steps.
38. The MOS type semiconductor device of claim 37, wherein a second
capacitor element comprises a BEOL capacitor element and a third
capacitor element comprises an MIM capacitor element.
39. An MOS type semiconductor device, comprising a capacitance the
numerical value of which is relevant for a device function, wherein
the capacitance comprises a parallel connection of at least a first
and second capacitor element, wherein the first capacitor element
comprises an MOS capacitor element containing an oxide layer of a
first type or thickness, respectively, and the second capacitor
element contains an oxide layer of a second type or thickness,
respectively, and wherein a first capacitance value of the first
capacitor element and a second capacitance value of the second
capacitor element, to obtain a predetermined total capacitance
value, are selected such that a process tolerance of the
capacitance is minimized.
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor device that
includes a capacitance, such as an analog/digital converter device
or filter device, a device function of which is significantly
influenced by a numerical value of the capacitance.
BACKGROUND
[0002] The device functions of semiconductor devices are
significantly influenced by the numerical value of inherent
capacitive elements, which numerical values are influenced by
process parameters of respective manufacturing steps of the
semiconductor device that result in the formation of those
capacitive elements. Therefore, in such semiconductor devices, the
device function may significantly depend on process parameter
fluctuations that are difficult to control in a sufficiently
precise manner.
[0003] A first type of capacitor element that may be relevant is a
MOS capacitor element originating from the formation of a MOS
(metal-oxide-semiconductor) structure in the manufacture of an
MOS-type semiconductor element. In particular, the exact thickness
of an oxide layer arranged on a semiconductor substrate and
underlying a subsequently deposited metal layer significantly
determines the capacitance value of a capacitor element of this
type.
[0004] A second relevant type of capacitor element is a so-called
MIM capacitor element, which is a specifically designed capacitor
element, formed from a dedicated dielectric layer and metal layer.
These layers are formed in the so-called BEOL (back-end-off-line)
process for electrically connecting the respective transistor and
resistor elements that beforehand were produced in the so-called
FEOL (front-and-off-line) process.
[0005] A third type of relevant capacitor element is formed by
using existing wiring layers, e.g., VPP structures, GRID structures
or sandwich structures.
[0006] For all of these above mentioned capacitor elements, the
respective process steps result in a typical fluctuation of the
capacitance value of not less than 15%. However, for semiconductor
elements the function of which is significantly determined by the
capacitance value of such capacitor elements, a fluctuation value
of the linear capacitance should be as low as about 10%.
SUMMARY OF THE INVENTION
[0007] In one aspect the present invention provides a semiconductor
device that includes a functionally significant capacitance,
wherein the process-determined tolerance (fluctuation) of the
capacitance value is reduced, to result in an improved device
function or device reliability, respectively, achieved at low
cost.
[0008] In an embodiment of the invention, the relevant capacitance
of the semiconductor device comprises a parallel connection of at
least a first and a second capacitor element, wherein the first and
second capacitor elements are formed in respective manufacturing
steps that exhibit uncorrelated process fluctuations. In
particular, more than two capacitor elements may be connected in
parallel, each of the more than two capacitor elements having a
respective capacitance value that selected such that a total
tolerance value of the resulting function-determining capacitance
is minimized.
[0009] In a further embodiment, a first capacitance value of the
first capacitor element and a second capacitance value of the
second capacitor element, to obtain a predetermined total
capacitance value, are selected such that a process tolerance of
the capacitance is minimized. In particular, if the first process
tolerance value is equal to the second process tolerance value, the
first capacitance value is selected equal to the second capacitance
value.
[0010] In an embodiment of the invention, the respective first and
second and, if provided, further capacitor elements, are of
different types, in so far as they result from different
manufacturing steps, i.e., an FEOL step on the one hand and a BEOL
step on the other. In particular, one of the capacitor elements may
be a MOS element, whereas another one is a BEOL capacitor element
of the VPP or GRID, or sandwich type. Further, in particular the
first capacitor element may be a MIM capacitor element, whereas
another capacitor element is of the VPP or GRID, or sandwich type,
i.e., of a type which is derived from the usual wiring structure of
the semiconductor device, not specifically dedicated to provide a
capacitance for an analog or mixed signal or radio frequency
processing purpose.
[0011] In a further embodiment, the capacitor elements contributing
to the total capacitance of the device may be basically of the same
type but, contain different types of dielectric layers. For
example, all or part of them may be MIM capacitor elements
containing several types of dielectric layers.
[0012] In a further embodiment, all of the capacitor elements may
be provided at the BEOL but, be of the GRID type on the one hand
and the VPP type on the other.
[0013] In a further embodiment, all or at least part of the several
capacitor elements forming the total capacitance may be MOS
capacitor elements but, contain different types of oxide
layers.
[0014] Furthermore, in an embodiment of the invention the above
mentioned combinations of capacitor elements being formed in
different process steps or capacitor elements being formed
basically at the same process stage but, with different dielectric
materials or oxides, respectively, may be combined with each other
in sophisticated multi-capacitor semiconductor devices with
essentially reduced total capacitance value fluctuation.
[0015] In a further embodiment of the invention, the semiconductor
device comprising a voltage controlled oscillator wherein, the
numerical value of the capacitance determines the oscillator
frequency. In a further embodiment, the device comprises an
analog/digital converter wherein, the numerical value of the
capacitance determines the convertal characteristics. Furthermore,
another semiconductor device of an embodiment of the invention
comprises a filter portion wherein, the numerical value of the
capacitance determines a filter characteristic. In all these
devices and further semiconductor devices for analog or
mixed-signal processing or radio frequency devices may, in
accordance with the respective manufacturing process steps, the
above embodiments be applied, to adequately connect several
capacitor elements with the purpose to reduce the process tolerance
of the total capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Embodiments of the present invention will now be described
by way of example with reference to the accompanying drawings.
[0017] FIG. 1 shows a graph illustrating the advantageous effect of
the invention;
[0018] FIGS. 2A to 2E show several cross-sections of a BEOL
metallization structure of a semiconductor device according to a
first embodiment of the invention, and FIG. 2F is a schematic
circuit diagram of the resulting total capacitance;
[0019] FIG. 3A shows a schematic cross-sectional illustration of a
semiconductor device according to a further embodiment of the
invention; and
[0020] FIG. 3B is a schematic circuit diagram of the resulting
total capacitance.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0021] FIG. 1 shows three graphs 1, 2, and 3 illustrating the
respective total variation of corresponding total capacitances that
are formed by means of connecting uncorrelated capacitors (Cap) A
and B in parallel, wherein three different assumptions are made for
the variation (process tolerance) of capacitor B, as indicated near
the top of the figure. For evaluating these graphs, it is assumed
that the overall fluctuation may be evaluated according to a
Gaussian distribution, i.e., by summing-up the squared variations
of the partial capacitance values.
[0022] It is to be seen that the total variation can be improved,
as compared to the variation of the "better" (first) capacitor A,
even if the variation of the second capacitor B is higher than that
of the first capacitor. Furthermore, it becomes clear that the
total variation depends on the ratio of the value of the single
capacitors, wherein the optimum capacitance ratio is dependent on
the variation values of both capacitors (partial capacitances), A
and B.
[0023] In this regard, for exhausting the advantages that may be
achieved by the invention, it is of importance to estimate the
variations or process-dependent fluctuations, respectively, of the
several capacitor elements that are to be connected in parallel to
form the total capacitance with an improved precision. If the
assumption holds that in most of the relevant FEOL and BEOL process
steps that may be used to form partial capacitances of the
respective process tolerance estimates are comparable (e.g., around
15 percent), the capacitance values of all contributing capacitors
connected in parallel may preferably be approximately identical
(neglecting any further factors that may be significant for
dimensioning the total capacitance).
[0024] FIGS. 2A to 2E show several vertical cross-sections of the
metallization layer structure (VPP capacitors and MIM capacitors)
of a semiconductor device, not showing those layers that belong to
the so-called FEOL. In all of these figures, only the respective
metal (e.g., aluminum) layers and vias of the VPP structure are
shown, whereas any for the MIM capacitor the dielectric layer is
shown (see the description below).
[0025] The BEOL structure of the semiconductor element is shown in
FIG. 2A in a first vertical cross-sectional view and in FIG. 2B to
2E in further vertical cross-sectional views, in several sectional
planes orthogonal to the sectional plane of FIG. 2A. The several
metal layers are connected to form a parallel connection of a first
capacitor C1 (MIM capacitor) and a second capacitor C2 (VPP
capacitor), see especially FIGS. 2A and 2F. It is a design option
of the specific layout, to adequately determine the numerical
values of C1 and C2 such as to achieve the best possible reduction
of the capacitance variation, i.e., the most precise total
capacitance that may be realized under the given process step
fluctuations of the BEOL steps.
[0026] The BEOL metallization structure comprises a basically
conventional VPP capacitor structure C2 comprising alternating
columns 4 or 5, respectively, of horizontally arranged and
vertically stacked strip-shaped metal layers being electrically
connected by comprising vias. A metal top layer 6, which is
connected to the respective columns 4, in this example. On the
other hand, columns 5 are connected to each other and to a
superimposed second metal top layer 11 by means of an external wire
connection 12 (FIG. 2A). Thus, as can best be seen in FIG. 2A, the
VPP capacitor is of a basically comb-like structure of alternating,
vertically aligned capacitor "plates" formed by the respective
metal strip/via columns 4 and 5.
[0027] On the surface of the lower top metal layer 6, a first
conductive layer is arranged, which serves as a bottom electrode 7
of the MIM capacitor C1. In one example, the top metal layer 6 is
aluminum, while the conductive layer is TiN. On this lower MIM
capacitor plate 7 an insulating layer 8 is provided, and thereon a
second conductive layer 9 serving as a second (top) electrode of
the MIM capacitor C1, is arranged. This top capacitor electrode 9
is connected to the top metal layer 11 by vias 10. Continuing with
the example, the conductive layer 9 can be TiN, while the metal
layer 11 and vias 10 are Al.
[0028] The details (including dimensions) of such structure, as
well as the process steps for making the same are basically
conventional, and therefore detailed description thereof is left
out.
[0029] FIG. 3A schematically shows the layer structure of a second
embodiment of the invention, in accordance with the schematic
circuit diagram of FIG. 3B. This latter figure shows a parallel
connection of a first capacitor C1', a second capacitor C2', and a
third, and fourth capacitor C3.1 and C3.2, together forming an
overall capacitance C as a function-determining capacitance C of a
semiconductor device (not shown). Deviating from FIGS. 2A to 2E,
FIG. 3A shows a surface portion of a semiconductor substrate 13, as
well as an MOS structure provided thereon, i.e., a structure formed
in a FEOL process, in addition to a BEOL structure provided
thereon.
[0030] A P well 14 is provided in the surface of the semiconductor
substrate 13, p.sup.+ doped regions 15.1, 15.2 are provided with a
predetermined distance from each other within the P well 14. On the
main surface of the semiconductor substrate 13, bridging the
distance between the p.sup.+ regions 15.1, 15.2, an oxide layer 16
comprising side wall spacers 16.1, 16.2 is provided. A first
conductive layer 17 is arranged on the oxide layer 16. This
conductive layer 17 forms, with the oxide layer 16 as a dielectric
layer, a first and second MOS capacitor C3.1 and C3.2 with the
p.sup.+ regions 15.1 and 15.2, respectively.
[0031] By means of vias 18, the MOS layer 17 is connected to a
further metal layer 19 provided thereon, with an interposed
dielectric layer (not specifically designated) arranged
therebetween. On the other hand, a further via 18 extends from the
p.sup.+ region 15.2 to a further metal layer (strip) 20 provided at
the same level as the metal layer 19, but electrically insulated
therefrom.
[0032] In a similar manner as with the comb-like structure of the
first embodiment (but with horizontally alternating "teeth" of the
comb), a sandwich capacitor C2' is built by stacking a
predetermined number of adequately configured metallization layers
(not specifically designated). On a top metallization layer 21 of
the stack, similarly to the first embodiment, an MIM capacitor C1'
is formed by providing a first (bottom) TiN layer 22, followed by a
dielectric layer 23, and a second (top) TiN layer 24, and connected
with a top metal (aluminum) layer 25 by respective vias 26.
[0033] Like the first embodiment, the formation of the respective
capacitor elements, including the sandwich capacitor C2' and the
MOS capacitors C3.1 and C3.2, is basically conventional and,
therefore no detailed description in this regard is necessary.
However, an adequate connection is essential between the several
structures or capacitor elements, respectively, by means of
specifically arranged vias, to provide for the intended parallel
connection of the various partial capacitances C1', C2', C3.1, and
C3.2 of the total capacitance C.
* * * * *