U.S. patent application number 12/213918 was filed with the patent office on 2009-01-08 for semiconductor device and method for manufacturing same.
This patent application is currently assigned to Kabushiki Kaisha Toshiba. Invention is credited to Yukie Nishikawa, Tatsuo Shimizu, Takeshi Yamaguchi.
Application Number | 20090011537 12/213918 |
Document ID | / |
Family ID | 34697685 |
Filed Date | 2009-01-08 |
United States Patent
Application |
20090011537 |
Kind Code |
A1 |
Shimizu; Tatsuo ; et
al. |
January 8, 2009 |
Semiconductor device and method for manufacturing same
Abstract
The present invention is to obtain an MIS transistor which
allows considerable reduction in threshold fluctuation for each
transistor and has a low threshold voltage. First gate electrode
material for nMIS and second gate electrode material for pMIS can
be mutually converted to each other, so that a process can be
simplified. Such a fact that a dependency of a work function on a
doping amount is small is first disclosed, so that fluctuation in
threshold voltage for each transistor hardly occurs.
Inventors: |
Shimizu; Tatsuo; (Tokyo,
JP) ; Yamaguchi; Takeshi; (Kanagawa-Ken, JP) ;
Nishikawa; Yukie; (Kanagawa-Ken, JP) |
Correspondence
Address: |
FINNEGAN, HENDERSON, FARABOW, GARRETT & DUNNER;LLP
901 NEW YORK AVENUE, NW
WASHINGTON
DC
20001-4413
US
|
Assignee: |
Kabushiki Kaisha Toshiba
Tokyo
JP
|
Family ID: |
34697685 |
Appl. No.: |
12/213918 |
Filed: |
June 26, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11020275 |
Dec 27, 2004 |
7405451 |
|
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12213918 |
|
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Current U.S.
Class: |
438/104 ;
257/E21.444; 257/E21.621; 257/E21.637; 438/154 |
Current CPC
Class: |
H01L 21/28202 20130101;
H01L 29/517 20130101; H01L 29/66545 20130101; H01L 21/28194
20130101; H01L 29/518 20130101; H01L 21/823842 20130101 |
Class at
Publication: |
438/104 ;
438/154; 257/E21.621 |
International
Class: |
H01L 21/8234 20060101
H01L021/8234 |
Foreign Application Data
Date |
Code |
Application Number |
Dec 26, 2003 |
JP |
2003-432199 |
Claims
1.-5. (canceled)
6. A method for manufacturing a semiconductor device comprising:
forming first electrode material films with a first conductivity
type on first and second regions on a semiconductor substrate;
introducing material that transform the first conductivity type to
a second conductivity type into the first electrode material film
on the second region to reform the first electrode material film on
the second region to a second electrode material film with the
second conductivity type; and patterning the first and second
electrode material films to form a first gate electrode on the
first region and form a second gate electrode on the second
region.
7. The method for manufacturing a semiconductor device according to
claim 6, further comprising, after the first electrode material
film is formed and before reforming to the second electrode
material film is performed, causing the semiconductor substrate and
the first electrode material film to react with each other to form
a gate insulating film between the semiconductor substrate and the
first electrode material by performing anneal in predetermined
atmosphere.
8. The method for manufacturing a semiconductor device according to
claim 6, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film where a work
function (eV) is in a range of 3.65.ltoreq..PHI.m.ltoreq.4.45, and
the other of the first and second gate electrodes includes a second
electrically conductive oxide film where a work function (eV) is in
a range of 4.77.ltoreq..PHI.m.ltoreq.5.57.
9. The method for manufacturing a semiconductor device according to
claim 8, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
Perovskite structure type oxide represented by ABO.sub.3 or a
Perovskite structure type oxynitride represented by ABON, where A
is at least one element selected from an A1 or A2 group, and B is
at least one element selected from a B1 or B2 group, and the A1
group being alkaline earth metals and rare earth metals, the A2
group being La and Y, the B1 group is constituted of Ti, Zr, Hf,
and Ce, and the B2 group is being Ta, Nb, and V, and the first
electrically conductive oxide film including at least one element
selected from the A2 group or the B2 group, and wherein the other
of the first and second gate electrodes includes a second
electrically conductive oxide film comprising a Perovskite
structure type oxide represented by CDO.sub.3 or a Perovskite
structure type oxynitride represented by CDON, where C is at least
one element selected from a C1 or C2 group, and D is at least one
element selected from a D1 or D2 group, the C1 group being alkaline
earth metals and rare earth metals, the C2 group being La and Y,
the D1 group being Ti, Zr, Hf, and Ce, and the D2 group being W,
Mo, Cr, Re, Tc, Mn, Os, Ru, Fe, Ir, Rh, Co, Pt, Pd, and Ni.
10. The method for manufacturing a semiconductor device according
to claim 6, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
rutile structure type oxide represented by AO.sub.2 or a rutile
structure type oxynitride represented by AON, and the where A
includes at least one element selected from an A1 group and at
least one element selected from an A2 group, the A1 group being Ti,
Zr, Hf, and Ce, and the A2 group is constituted of Ta, Nb, and V,
and wherein the other of the first and second gate electrodes
includes a second conductive oxide film comprising a rutile
structure type oxide represented by XO.sub.2 or a rutile structure
type oxynitride represented by XON, where X includes at least one
element selected from an X1 or X2 group, the X1 group being of Ti,
Zr, Hf, and Ce, and the X2 group being W, Mo, Cr, Re, Tc, Mn, Os,
Ru, Fe, Ir, Rh, Co, Pt, Pd, and Ni.
11. A method for manufacturing a semiconductor device comprising:
stacking a dummy insulating film and a dummy electrode material
film on a first region and a second region of a semiconductor
substrate, respectively; patterning the dummy electrode material
film and the dummy insulating film to a dummy gate electrode and a
dummy insulating film on the first and second regions; forming
insulating films on side portions of the dummy gate electrode and
dummy gate insulating film on the first and the second regions;
removing the dummy gate electrode and dummy gate insulating film to
form first and second gate grooves on the first and the second
regions; forming gate insulating films on at least bottom faces of
the first and second gate grooves; embedding first electrode
material films with a first conductivity type in the first and
second gate grooves to form first gate electrodes covering the gate
insulating films; and introducing material that transform the first
conductivity type to a second conductivity type into the first gate
electrode on the second region to reform the first gate electrode
on the second region to a second gate electrode with the second
conductivity type.
12. The method for manufacturing a semiconductor device according
to claim 11, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film where a work
function (eV) is in a range of 3.65.ltoreq..PHI.m.ltoreq.4.45, and
the other of the first and second gate electrodes includes a second
electrically conductive oxide film where a work function (eV) is in
a range of 4.77.ltoreq..PHI.m.ltoreq.5.57.
13. The method for manufacturing a semiconductor device according
to claim 11, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
Perovskite structure type oxide represented by ABO.sub.3 or a
Perovskite structure type oxynitride represented by ABOn, where A
is at least one element selected from an A1 or A2 group, and B is
least one element selected from a B1 or B2 group, the A1 group
being alkaline earth metals and rare earth metals, the A2 group
being La and Y, the B1 group being Ti, Zr, Hf, and Ce, and the B2
group being Ta, Nb, and V, and the first electrically conductive
oxide film including at least one element selected from the A2
group or the B2 group, and wherein the other of the first and
second gate electrodes includes a second electrically conductive
oxide film comprising a Perovskite structure type oxide represented
by CDO.sub.3, or a Perovskite structure type oxynitride represented
by CDON, where C is at least one element selected from a C1 or C2
group, and D is at least one element selected from a D1 or D2
group, the C1 group being alkaline earth metals and rare earth
metals, the C2 group being La and Y, the D1 group being Ti, Zr, Hf,
and Ce, and the D2 group being W, Mo, Cr, Re, Tc, Mn, Os, Ru, Fe,
Ir, Rh, Co, Pt, Pd, and Ni.
14. The method for manufacturing a semiconductor device according
to claim 11, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
rutile structure type oxide represented by AO.sub.2 or a rutile
structure type oxynitride represented by AON, where A includes at
least one element selected from an A1 group and at least one
element selected from an A2 group, the A1 group being Ti, Zr, Hf,
and Ce, and the A2 group is constituted of being Ta, Nb, and V, and
wherein the other of the first and second gate electrodes includes
a second electrically conductive oxide film comprising a rutile
structure type oxide represented by XO.sub.2 or a rutile structure
type oxynitride represented by XON, where X includes at least one
element selected from an X1 or X2 group, the X1 group being Ti, Zr,
Hf, and Ce, and the X2 group being W, Mo, Cr, Re, Tc, Mn, Os, Ru,
Fe, Ir, Rh, Co, Pt, Pd, and Ni.
15. A method for manufacturing a semiconductor device comprising:
stacking a dummy insulating film and a dummy electrode material
film on a first region and a second region of a semiconductor
substrate, respectively; patterning the dummy electrode material
film and the dummy insulating film to a dummy gate electrode and a
dummy insulating film on the first and second regions; forming
insulating films on side portions of the dummy gate electrode and
dummy gate insulating film on the first and the second regions;
removing the dummy gate electrode and dummy gate insulating film to
form first and second gate grooves on the first and the second
regions; embedding first electrode material films with a first
conductivity type in the first and second gate grooves to form
first gate electrodes; causing the semiconductor substrate and the
first gate electrodes to react with each other to form a gate
insulating films between the semiconductor substrate and the first
gate electrodes by performing anneal in predetermined atmosphere;
and introducing material that transform the first conductivity type
to a second conductivity type into the first gate electrode on the
second region to reform the first gate electrode on the second
region to a second gate electrode with the second conductivity
type.
16. The method for manufacturing a semiconductor device according
to claim 15, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film where a work
function (eV) is in a range of 3.65.ltoreq..PHI.m.ltoreq.4.45, and
the other of the first and second gate electrodes includes a second
electrically conductive oxide film where a work function (eV) is in
a range of 4.77.ltoreq..PHI.m.ltoreq.5.57.
17. The method for manufacturing a semiconductor device according
to claim 15, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
Perovskite structure type oxide represented by ABO.sub.3 or a
Perovskite structure type oxynitride represented by ABON, where A
is at least one element selected from an A1 or A2 group, and B is
at least one element selected from a B1 or a B2 group, the A1 group
being alkaline earth metals and rare earth metals, the A2 group
being La and Y, the B1 group being Ti, Zr, Hf, and Ce, and the B2
group being Ta, Nb, and V, and the first electrically conductive
oxide film including at least one element selected from the A2
group or the B2 group, and wherein the other of the first and
second gate electrodes includes a second electrically conductive
oxide film comprising a Perovskite structure type oxide represented
by CDO.sub.3 or a Perovskite structure type oxynitride represented
by CDON, where C is at least one element selected a C1 or C2 group,
D is at least one element selected from a D1 or D2 group, the C1
group being alkaline earth metals and rare earth metals, the C2
group being La and Y, the D1 group being Ti, Zr, Hf, and Ce, and
the D2 group being W, Mo, Cr, Re, Tc, Mn, Os, Ru, Fe, Ir, Rh, Co,
Pt, Pd, and Ni.
18. The method for manufacturing a semiconductor device according
to claim 15, wherein one of the first and second gate electrodes
includes a first electrically conductive oxide film comprising a
rutile structure type oxide represented by AO.sub.2 or a rutile
structure type oxynitride represented by AON, where A includes at
least one element selected from an A1 group and at least one
element selected from an A2 group, the A1 group being Ti, Zr, Hf,
and Ce, and the A2 group being Ta, Nb, and V, and wherein the other
of the first and second gate electrodes includes a second
electrically conductive oxide film comprising a rutile structure
type oxide represented by XO.sub.2 or a rutile structure type
oxynitride represented by XON, where X includes at least one
element selected from an X1 or X2 group, the X1 group being Ti, Zr,
Hf, and Ce, and the X2 group being W, Mo, Cr, Re, Tc, Mn, Os, Ru,
Fe, Ir, Rh, Co, Pt, Pd, and Ni.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is based upon and claims the benefit of
priority from prior Japanese Patent Application No. 2003-432199
filed on Dec. 26, 2003 in Japan, the entire contents of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a semiconductor device and
a method for manufacturing the same, and in particular to a gate
electrode using electrically conductive oxide, of an n-type MIS
transistor and a p-type MIS transistor.
[0004] 2. Related Art
[0005] A gate electrode a conventional MISFET (Metal Insulator
Semiconductor Field Effect Transistor)(hereinafter, called "MIS
transistor") is formed of polycrystal silicon. Because of demand
for reducing power consumption, it is common to employ a dual gate
structure where n-type polycrystal silicon is used for a gate
electrode of an n-type MIS transistor (hereinafter, called "nMIS
transistor") and p-type polycrystal silicon is used for a gate
electrode of a p-type MIS transistor (hereinafter, called "pMIS
transistor").
[0006] In the dual gate structure, there is a problem about "boron
punch through" where boron contained in the p-type polycrysal
silicon diffuses into a silicon substrate through a gate insulating
film. Further, since the polycrystal silicon produces a depletion
layer in an interface between the same and the gate insulating
film, a film thickness of the gate insulating film equivalent to an
SiO.sub.2 film becomes thicker in an amount of about 0.5 nm. In
current situation where development is directed for achieving the
SiO.sub.2 equivalent film thickness of the gate insulating film of
1 nm or less for fineness of a device by such a scheme as advance
of film thinning of the gate insulating film or use of a high-k
dielectric film in some cases, increase of the above equivalent
film thickness causes a much significant problem.
[0007] As a method for solving the problem occurring when such
polycrystal silicon is used for the gate electrode, it is
considered that high melting point metal is used as material for
the gate electrode. Since it is unnecessary to introduce boron into
the metal gate electrode, the problem about the "boron punch
through" does not occur. Since a depletion layer itself is not
produced, such a problem that the conversion film thickness becomes
larger at an electrode portion is also solved. It is considered
that a problem about shift of flat band potential Vfb causing a
problem in high-k dielectric HfSiON or the like can be solved by
using the metal gate electrode. This is because one of serious
causes of shift of the Vfb fluctuated is solved, since a charge
trap due to boron disappears.
[0008] On the other hand, when gate electrodes for the pMIS and the
nMIS are formed in a usual manner using the same metal gate
electrode material, there occurs such a problem that a threshold
voltage is increased as compared with that of the polycrystal
silicon gate electrode. For example, when promising titanium
nitride is used as the gate electrode material, it is difficult to
lower the threshold voltage down to 0.4V or less, even if an
impurity distribution in a surface of the silicon substrate is
adjusted. The reason is why, since the work function of titanium
nitride is about 4.7 eV and the value is positioned in the vicinity
of an central portion of the forbidden band of silicon, a different
in work function between the titanium nitride and the pMIS
transistor reaches about 0.47 eV and a difference in work function
between the titanium nitride and the nMIS transistor reaches about
0.65 eV.
[0009] In view of these circumstances, first, such a thought is
proposed that the gate electrode of the pMIS transistor and the
gate electrode of the nMIS transistor are formed from different
kinds of metal materials. For example, this is a thought that
iridium or the like which is positioned near an upper limit in the
valence band of silicon and whose work function is about 5.2 eV is
used as the gate electrode of the pMIS transistor, and zirconium or
the like which is positioned near a lower limit of the conduction
band of the silicon substrate and whose work function is about 4.1
eV is used as the gate electrode of the nMIS transistor.
[0010] 1) However, many metals and conductive nitrides themselves
are oxidized by bringing them in contact with the gate insulating
film which is oxide and an interface property is deteriorated,
which causes leakage current. For example, TaN deteriorates at its
interface with an insulator in a step conducted at a temperature of
800.degree. C. or higher, which results in increase in leakage
current simultaneously with production of oxide. Some oxides
develop an insulating property due to material therefor, which
results in increase in thickness of the insulating film. For
example, in case of Zr, it changes to insulating ZrO.sub.2.
[0011] 2) The metal electrode includes much material with strong
catalyst activity. Therefore, there may occur such a serious
problem that, when such material, for example, Pt or Ir is used,
film peeling-off occurs at another portion (for example, MIM (Metal
Insulator Metal) capacitor or the like) in LSI during forming
anneal using hydrogen atmosphere.
[0012] 3) Further, there is a case that a simple metal diffuses in
an insulating film or a substrate to distribute unevenly. It is
considered that such a metal constitutes a source for destroying
insulating property of a gate insulating film. It is to be noted
that, when the metal diffuses into the insulating film so as to
form metal silicate thereby increasing dielectric constant,
properties for an insulating film are improved in some cases.
Simultaneously, however, since there is such an indication that
electron barrier or hole barrier lowers, the lowering results in
slight deterioration in leakage property.
[0013] 4) Though metal (Ru, Pt, Ir or the like) whose oxide
develops electric conductivity is used, the problems described in
the above item 2) and 3) still remain. Further, an example where
electrically conductive oxide is used for a gate electrode of an
nMIS transistor has been known (for example, refer to Japanese
Patent Application Laid-open No. 2002-289844 (JP-A)). As described
in the next item 5), however, though it is required to select an
optimal work function, a combination of these electrically
conductive oxides which has work functions suitable for both the
nMIS transistor and the pMIS transistor does not exist yet. For
example, since the work function of Ru is 4.7 eV and that of
RuO.sub.2 is in a range of 4.9 to 5.1 eV, an Ru electrode can not
be used for the nMIS transistor.
[0014] 5) Finally, since the work functions must be optimized to
the nMIS transistor and pMIS transistor, control based upon
nitriding has been tried until now. For example, the work functions
of Ti and TiN are respectively 4.1 eV and 4.7 eV, but the work
function of TiN is not optimal for the pMIS transistor (for
example, refer to Claflin, B; Mater. Res. Soc. Ultrathin SiO.sub.2
and High-k Materials for ULSI gate dielectrics 603 (1999)).
Further, it is considered that metal post-nitrided is used (Mo,
Mo.sub.2N or the like). In the case, however, there is an
indication about a problem that nitrogen can not be present
sufficiently stably, and nitrogen is gone out in a heat
treatment.
[0015] Thus, there is the present situation that a combination of
metals or nitrided metals which have optimal work functions as a
combination of the nMIS transistor and the pMIS transistor can not
be found. There is a trial based upon alloying. For example,
regarding a case of using alloy of Ti--Ni, there is a report that a
work function thereof can be controlled from 3.9 eV to 5.3 eV (for
example, refer to Polishchuk, I; Mater. Res. Soc. Gate Stack and
Silicide Issues in Silicon Processing II Symposium PPK511-6
(2002)). In this case, the problems about metals described in the
above items 1), 2), and 3) are not solved to remain as they
are.
SUMMARY OF THE INVENTION
[0016] The present invention has been made in view of the above
circumstances, and an object thereof is to provide a semiconductor
device provided with a MIS transistor with a low threshold voltage
and a method for manufacturing the same.
[0017] A semiconductor device according to a first aspect of the
present invention includes: an nMIS transistor including a first
gate insulating film which is formed on a semiconductor substrate,
a first gate electrode which is formed on the first gate insulating
film and includes a first electrically conductive oxide film where
a work function .PHI.m (eV) is in a range of
3.65.ltoreq..PHI.m.ltoreq.4.45, and first source-drain regions
which are formed on the semiconductor substrate on both sides of
the first gate electrode; and a pMIS transistor including a second
gate insulating film which is formed on the semiconductor
substrate, a second gate electrode which is formed on the second
gate insulating film and includes a second electrically conductive
oxide film where a work function .PHI.m (eV) is in a range of
4.77.ltoreq..PHI.m.ltoreq.5.57, and second source-drain regions
which are formed on the semiconductor substrate on both sides of
the second gate electrode.
[0018] A semiconductor device according to a second aspect of the
present invention includes: an nMIS transistor, the nMIS transistor
comprising a gate insulating film which is formed on a
semiconductor substrate, a gate electrode which is formed on the
gate insulating film, and source-drain regions which are formed on
the semiconductor substrate on both sides of the gate electrode,
wherein
[0019] the gate electrode includes a film formed from Perovskite
structure type oxide or oxynitrides of ABO.sub.3, the A is
constituted of at least one element selected from A1 group and A2
group, the B is constituted of at least one element selected from
B1 group and B2 group, and wherein
[0020] when the A1 group is constituted of alkaline earth metal and
rare earth metal, the A2 group is constituted of La and Y, the B1
group is constituted of Ti, Zr, Hf, and Ce, and the B2 group is
constituted of Ta, Nb, and V,
[0021] the film formed from the Perovskite structure oxide or
oxynitrides includes at least one element selected from the A2
group and the B2 group.
[0022] A semiconductor device according to a third aspect of the
present invention includes: an nMIS transistor, the nMIS transistor
comprising a gate insulating film which is formed on a
semiconductor substrate, a gate electrode which is formed on the
gate insulating film, and source-drain regions which are formed on
the semiconductor substrate on both sides of the gate electrode,
wherein
[0023] the gate electrode includes a film formed from a rutile
structure type oxide or oxynitrides of AO.sub.2, and the A includes
at least one element selected from A1 group and at least one
element selected from A2 group, and wherein
[0024] the A1 group is constituted of Ti, Zr, Hf, and Ce, the A2
group is constituted of Ta, Nb, and V.
[0025] A semiconductor device according to a fourth aspect of the
present invention includes: a pMIS transistor, the pMIS transistor
comprising a gate insulating film which is formed on a
semiconductor substrate, a gate electrode which is formed on the
gate insulating film, and source-drain regions which are formed on
the semiconductor substrate on both sides of the gate electrode,
wherein
[0026] the gate electrode includes a film formed from Perovskite
structure type oxide or oxynitrides of ABO.sub.3, the A is
constituted of at least one element selected from A1 group and A2
group, the B is constituted of at least one element selected from
B1 group and B2 group, and wherein
[0027] when the A1 group is constituted of alkaline earth metal and
rare earth metal, the A2 group is constituted of La and Y, the B1
group is constituted of Ti, Zr, Hf, and Ce, and the B2 group is
constituted of W, Mo, Cr, Re, Tc, Mn, Os, Ru, Fe, Ir, Rh, Co, Pt,
Pd, and Ni,
[0028] the film formed from the Perovskite structure type oxide or
oxynitrides includes at least one element selected from the B2
group.
[0029] A semiconductor device according to a fifth aspect of the
present invention includes: a pMIS transistor, the pMIS transistor
comprising a gate insulating film which is formed on a
semiconductor substrate, a gate electrode which is formed on the
gate insulating film, and source-drain regions which are formed on
the semiconductor substrate on both sides of the gate electrode,
wherein
[0030] the gate electrode includes a film formed from a rutile
structure type oxide or oxynitrides of AO.sub.2, and the A is
constituted of at least one element selected from A1 group and A2
group, and wherein
[0031] when the A1 group is constituted of Ti, Zr, Hf, and Ce, and
the A2 group is constituted of W, Mo, Cr, Re, Tc, Mn, Os, Ru, Fe,
Ir, Rh, Co, Pt, Pd, and Ni,
[0032] the film formed from the rutile structure type oxide and
oxynitrides of the AO.sub.2 includes at least one element selected
from the A2 group.
[0033] A method for manufacturing a semiconductor device according
to a sixth aspect of the present invention includes: forming first
electrode material films on first and second regions on a
semiconductor substrate; introducing predetermined material into
the first electrode material film on the second region to reform
the same to a second electrode material film; and patterning the
first and second electrode material films to form a first gate
electrode on the first region and form a second gate electrode on
the second region.
[0034] A method for manufacturing a semiconductor device according
to a seventh aspect of the present invention includes: stacking a
dummy insulating film and a dummy electrode material film on a
first region and a second region of a semiconductor substrate,
respectively; patterning the dummy electrode material film and the
dummy insulating film to a dummy gate electrode and a dummy
insulating film on the first and second regions; forming insulating
films on side portions of the dummy gate electrode and dummy gate
insulating film on the first and the second regions; removing the
dummy gate electrode and dummy gate insulating film on the first
and the second regions; embedding first electrode material films
via first electrode material films in places from which the dummy
gate electrode and the dummy gate insulating film have been removed
to form first gate electrodes; and introducing predetermined
material into the first gate electrode on the second region to
reform the first gate electrode to a second gate electrode.
[0035] A method for manufacturing a semiconductor device according
to a eighth aspect of the present invention includes: stacking a
dummy insulating film and a dummy electrode material film on a
first region and a second region of a semiconductor substrate,
respectively; patterning the dummy electrode material film and the
dummy insulating film to a dummy gate electrode and a dummy
insulating film on the first and second regions; forming insulating
films on side portions of the dummy gate electrode and dummy gate
insulating film on the first and the second regions; removing the
dummy gate electrode and dummy gate insulating film on the first
and the second regions; embedding first electrode material films
via first electrode material films in places from which the dummy
gate electrode and the dummy gate insulating film have been removed
to form first gate electrodes; causing the semiconductor substrate
and the first gate electrode to react with each other to form a
gate insulating film between the semiconductor substrate and the
first gate electrode by conducting anneal in predetermined
atmosphere; and introducing predetermined material into the first
gate electrode on the second region to reform the first gate
electrode to a second gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
[0036] FIG. 1 is a diagram showing ranges of preferable work
functions suitable for an nMIS transistor and a pMIS transistor
according to a semiconductor device according to a first embodiment
of the present invention;
[0037] FIG. 2 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to a
second embodiment of the present invention;
[0038] FIG. 3 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
second embodiment of the present invention;
[0039] FIG. 4 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
second embodiment of the present invention;
[0040] FIG. 5 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
second embodiment of the present invention;
[0041] FIG. 6 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
second embodiment of the present invention;
[0042] FIG. 7 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to a
third embodiment of the present invention;
[0043] FIG. 8 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0044] FIG. 9 is a sectional view showing a manufacturing step in a
method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0045] FIG. 10 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0046] FIG. 11 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0047] FIG. 12 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0048] FIG. 13 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention;
[0049] FIG. 14 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention; and
[0050] FIG. 15 is a sectional view showing a manufacturing step in
a method for manufacturing a semiconductor device according to the
third embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0051] Embodiments of the present invention will be explained
below.
First Embodiment
[0052] A semiconductor device according to a first embodiment of
the present invention has an nMIS transistor and a pMIS transistor
formed on a silicon substrate. The nMIS transistor is provided with
a gate insulating film formed on the silicon substrate, a gate
electrode formed on the gate insulating film, and source-drain
regions formed on the silicon substrate at both sides of the gate
electrode. Similarly, the pMIS transistor is also provided with a
gate insulating film formed on the silicon substrate, a gate
electrode formed on the gate insulating film, and source-drain
regions formed on the silicon substrate at both sides of the gate
electrodes.
[0053] As shown in FIG. 1, the gate electrode of the nMIS
transistor includes a first electrically conductive oxide film
whose work function .PHI.m (eV) is in a range 1 of
3.65.ltoreq..PHI.m.ltoreq.4.45. As shown in FIG. 1, the gate
electrode of the pMIS transistor includes a second electrically
conductive oxide film whose work function .PHI.m (eV) is in a range
2 of 4.77.ltoreq..PHI.m.ltoreq.5.57. FIG. 1 is a diagram showing an
energy band of silicon, where the lower limit value of the
conduction band of silicon is 4.05 eV and the upper limit value of
the valence band thereof is 5.17 eV.
[0054] Now, the upper limit value and the lower limit value of the
work function are conditions for allowing the threshold voltage to
be lowered to at least 0.4 V or less. When the conditions can not
be satisfied, a transistor operating with a low threshold can not
be obtained. Such a numeral as 0.4V which is the threshold voltage
will be allowable maximum value to integrated circuits which will
be developed in the future in a sense of power consumption and in a
sense of device performance. In the future, the threshold voltage
will advance to be lower than the above value.
[0055] Accordingly, when the MIS transistor is constituted in the
above manner, fluctuation in threshold for respective transistors
becomes very small and a MIS transistor with a low threshold
voltage can be obtained.
[0056] Incidentally, it is made possible to shift the optimal value
of the work function slightly toward a midgap direction of the
energy band by using a counterdoping technique. However, since
there is a limitation even in this technique, it is very effective
for future integrate circuit development to develop a material
group which allows arbitrary control on the work function in the
above range.
[0057] According to the constitution, it is possible to form an
nMIS transistor with a low threshold and a pMIS transistor with a
low threshold.
(Gate Electrode Material)
[0058] Next, gate electrode materials having the work function in
the above range will be explained.
[0059] First, optimization of gate electrode materials for the nMIS
transistor and the pMIS transistor is performed. Briefly speaking,
problems to be solved are as follows:
[0060] 1) Roughness of interface between the gate insulating film
and the gate electrode due to oxidation of the gate electrode and
characteristic deterioration of a gate insulating film due to
insulating of the gate electrode are avoided.
[0061] 2) Materials with strong catalytic property are not selected
as materials for the gate electrode.
[0062] 3) Since there is a high possibility that simple metal
diffuses into a gate insulating film, material constitution which
can suppress diffusion is selected.
[0063] 4) The work function is 4.05 eV or so for the nMIS
transistor. An absolutely necessary condition for securely
realizing a threshold voltage of 0.4 eV or less is that the work
function .PHI.m (eV) satisfies 3.65.ltoreq..PHI.m.ltoreq.4.45. The
work function is 5.17 eV or so for the pMIS transistor. An
absolutely necessary condition for securely realizing a threshold
voltage of 0.4 eV or less is that the work function .PHI.m (eV)
satisfies 4.77.ltoreq..PHI.m.ltoreq.5.57.
[0064] In order to satisfy the above conditions, such a fact has
been first found by the present inventors that electrically
conductive oxide may be used for the gate electrode. The reason why
there is not any example where electrically conductive oxides are
used as materials for the gate electrodes to both the nMIS
transistor and the pMIS transistor is because a desired work
function can not be achieved. That is, this is because the method
for adjusting a work function of electrically conductive oxide
invented by the present inventors did not exist.
[0065] As the existing example, there is a literature describing
the electrically conductive oxides without defining the work
functions (for example, refer to JP-A-2002-289844). The Patent
Literature describes that electrically conductive oxides are used
in a gate electrode in an nMIS transistor. However, according to
the inventors' examination result, it has been found that the
electrically conductive oxides described in the Patent Literature
are unsuitable for the nMIS transistor but suitable for the pMIS
transistor. This will be because consideration for the work
function has not been made in the Patent Literature. That is,
according to the inventors' consideration, it has been found that
Sr (Ru.sub.1-xTi.sub.x)O.sub.3 or La.sub.1-xSr.sub.xCoO.sub.3 which
is mainly used as the electrically conductive oxide in the Patent
Literature is one of the electrically conductive oxides which can
be used for the pMIS transistor but it is an electrically
conductive oxide which is never used in the nMIS transistor in view
of the work function. When such oxide is used in the nMIS
transistor, an extremely high threshold voltage is required, so
that the nMIS transistor can not be used for an LSI.
[0066] In a sense of the known examples of the electrically
conductive oxide, electrically conductive oxides such as RuO.sub.2
(whose work function is 4.9 eV) are indicated in many school
textbooks. However, since the electrically conductive oxides are
gate electrode materials which can be used in only one MIS
transistor such as the pMIS transistor, these oxides can not be
used for producing a CMOS structure.
[0067] Since the electrically conductive oxide is the same oxide as
the gate insulating film, it has an excellent affinity with the
gate insulating film, which allows an excellent interface between
the dielectric and the electrode. Therefore, there does not occur
the problem explained in the item 1).
[0068] Since the electrically conductive oxide is material obtained
as the result that it has been considerably stabilized as oxide, it
may be considered that the electrically conductive oxide hardly has
catalytic action as compared with metals or the like. As regards a
catalytic property of the oxide, a problem arises when the oxide
has oxygen defects on a surface thereof coming in contact with
vacuum. However, since a structure where a gate electrode is
exposed is not employed in an ordinary MIS transistor and covering
on a surface of the gate electrode is conducted, the problem about
the oxygen defects does not occur at all. Therefore, there does not
occur the problem explained in the item 2).
[0069] Since oxides are stabilized, there is a possibility that
diffusion may occur in an interface between oxides in a form of
in-plane evenness depending on a combination of the oxides.
However, it is not that a simple metal reaches in a substrate.
Therefore, there does not occur the problem explained in the item
3).
[0070] As described below, the problem about the work function
explained in the item 4) is solved by using the electrically
conductive oxide, because the work function can be controlled
considerably freely. Incidentally, the work function can be
measured based upon photoelectric effect. It is made possible to
manufacture an ideal gate insulating film and an ideal gate
electrode interface by producing an nMIS structure and a pMIS
structure by utilizing the manufacturing method explained in detail
in this text. In that case, it is made possible to conduct inverse
operation of the work function by measuring thresholds for
operations of the nMIS transistor and the pMIS transistor.
(Gate Electrode Material for nMIS Transistor)
[0071] Next, the gate electrode material for the nMIS transistor
will be explained.
[0072] Regarding the work function of the electrically conductive
oxide, consideration is made from electron state. First, the
electrically conductive oxides for the nMIS transistor will be
examined. For the examination, an important hint is provided from
electronic physical properties of an insulating oxide such as
Perovskite type SrTiO.sub.3 or rutile type TiO.sub.2. The electron
affinity of each of these materials is about 4.1 eV. The conduction
band of the material comes from Ti.
[0073] In case of the Perovskite type SrTiO.sub.3, when La or Y
with electrons of the number more by one is introduced into an Sr
site, the band structure of the conduction band hardly changes, and
electron injection is made possible. At that time, the work
function in each material can be controlled in a range of 4.1 eV
(in case of Sr of 99.9%) to 4.0 eV (in case of Sr of 0%) according
to the amount of La or Y. Since the resistivity of the material, or
La or Y, becomes lower according to lowering of an Sr ratio, it is
unnecessary to consider the constitution ratio thereof to Sr.
Therefore, in view of easiness of production and such a fact that
resistivity is very low, promising material includes LaTiO.sub.3
(the work function is 4.0 eV and the resistivity is
5.times.10.sup.-5 .OMEGA.cm) and YTiO.sub.3 (the work function is
4.0 eV and the resistivity is 5.times.10-5 .OMEGA.cm).
[0074] In case of the same Perovskite type SrTiO.sub.3, an
electrically conductive oxide for the nMIS transistor can be
obtained by introducing Ta, Nb or V with electrons of the number
more by one into the Ti site. At that time, a bottom of the
conduction band has another band structure formed by interaction
between Ti and material substituted for Ti. The positions of the
bottom of the newly produced band for Ta, Nb, and V correspond to
the positions of 4.2 eV, 4.3 eV, and 4.4 eV from the vacuum level.
Therefore, the work functions can be respectively controlled in a
very small range of 4.2 eV (when Ti is 99% and Ta is 1%) to 4.1 eV
(when Ti is 0% and Ta is 100%), of 4.3 eV (when Ti is 99% and Nb is
1%) to 4.2 eV (when Ti is 0% and Nb is 100%), and of 4.4 eV(when Ti
is 99% and V is 1%) to 4.3 eV (when Ti is 0% and V is 100%)
according to constitution ratios of Ti to Ta, Nb, and V. The
material is reduced in resistivity according to reduction in ratio
of Ti. Therefore, in view of easiness of production and such a fact
that resistivity is very low, promising material includes
SrTaO.sub.3 (the work function is 4.1 eV and the resistivity is
5.times.10.sup.-5 .OMEGA.cm), SrNbO.sub.3 (the work function is 4.2
eV and the resistivity is 5.times.10.sup.-5 .OMEGA.cm), and
SrVO.sub.3 (the work function is 4.3 eV and the resistivity is
5.times.10.sup.-5 .OMEGA.cm).
[0075] The above discussion about the Perovskite type is not
limited to a case that the base material is SrTiO.sub.3. The A site
is not required to be Sr, but it may be alkaline earth metal (Ca,
Sr, Ba) or rare earth metal. A case that Zr, Hf, Ce, or the like is
introduced into the B site containing Ti can be discussed in the
substantially same manner as the above. Incidentally, since Zr, Hf,
or Ce to Ti serves to raise the bottom of the conduction band, when
Zr, Hf, or Ce to Ti is suppressed to 20% or less, the entirely same
discussion as the case of SrTiO.sub.3 can be made. When
introduction of Zr, Hf, or Ce is conducted in an amount of about
20%, such partial change occurs that the electron affinities of the
respective materials rise to 4.0 eV, 4.0 eV, and 3.9 eV (the
magnitude is reduced).
[0076] Therefore, in the substitution in the A site, the work
functions are respectively shifted by 0.1 eV, 0.1 eV, and 0.2 eV.
For example, regarding LaTiO.sub.3 (the work function is 4.0 eV and
the resistivity is 5.times.10.sup.-5 .OMEGA.cm), La (Ti, Zr)
O.sub.3 (the work function is 3.9 eV and the resistivity is
7.times.10.sup.-5 .OMEGA.cm), La (Ti, Hf) O.sub.3 (the work
function is 3.9 eV and the resistivity is 1.times.10.sup.-4
.OMEGA.cm), and La (Ti, Ce) O.sub.3 (the work function is 3.8 eV
and the resistivity is 2.times.10.sup.-4 .OMEGA.cm) are
obtained.
[0077] Regarding the B site substitution, the material subjected to
20% substitution only raises the bottom of the conduction band and
a large change does not appear in the work function. Since the
interactions of Zr, Hf, and Ce with the material used for
substitution, Ta, Nb, and V gradually decreases in the order of Zr,
Hf, and Ce, as compared with Ti, it is to be noted that gradual
deterioration occurs in a sense of electric resistivity. Since
reduction resistivity is increased by introduction of Zr, Hf, or
Ce, introduction of these materials can be conducted, as necessary,
together with operation of the work function.
[0078] On the other hand, since the electron affinity decreases to
about 3.1 eV or less in SrZrO.sub.3, SrHfO.sub.3, or SrCeO.sub.3,
which does not include Ti, a gate electrode for the nMIS transistor
can not be obtained by introduction of La or Y. In this case, it is
possible to obtain an electrically conductive electrode for an nMIS
transistor by introduction of Zr, Hf, or Ce like the case of
Ti.
[0079] Here, regarding the whole invention, the following point is
to be noted. Since similar characteristics are obtained in any film
of a film of a polycrystal state, a film of amorphous state, and a
film obtained by epitaxial growth including an orientation film,
the discussion of the invention in this text does not depend on the
state.
[0080] Such a case will occur that A site material and B site
material have been mixed with each other. For example, in (La,
Sr)(Ti, Nb)O.sub.3, it is thought that the B site material
determines the bottom position of the conduction band to which
electron injection takes place from La. In LaNbO.sub.3 which is an
extreme example, the work function is 4.05 eV and the resistivity
is 5.times.10.sup.-6 .OMEGA.cm. By employing such a constitution,
the number of electrons contributing to conduction can be
increased, so that the electric resistivity can be lowered one or
more digits.
[0081] In the above description, the A site materials and the B
site materials of the Perovskite structure suitable for the nMIS
transistor have been referred to. However, adjustment of the work
function can be made finely by ratio change of these materials, of
course.
[0082] Further, there may be a structure where the A site material
is excessively included. Such a structure is regarded as extension
to a layered Perovskite structure. Therefore, it is made possible
to increase the electron injection amount and lower the electric
resistivity. For example, in excessive introduction of La into
LaTiO.sub.3, when only a LaO component is introduced excessively,
material, La.sub.2TiO.sub.4 is produced. The work function of the
material is smaller than that of the LaTiO.sub.3 (4.0 eV-->3.9
eV) and the electric resistivity thereof is remarkably lowered. In
measurement of an actual film, it was possible to achieve lowering
of about one digit.
[0083] It is also confirmed that, even if the amount of La is not
increased up to the above amount, the electric resistivity can be
lowered by increasing the ratio of La and Ti to more than 1. Of
course, it is possible to employ a structure in which a further
large amount of LaO layer has been introduced. However, in view of
the problem about stability of the layered Perovskite structure, it
is preferable that the amount to be excessively introduced
satisfies La/Ti.ltoreq.3.0. When the amount exceeds this range,
such a possibility occurs that LaO segregates and the work function
changes urgently, which results in difficulty in control.
[0084] Even in the rutile type TiO.sub.2, similar discussion will
be made. The discussion about only the B site portion in the
Perovskite structure may be applied to the rutile type TiO.sub.2 as
it is. For example, (Ti, Nb) O.sub.2 or the like can be used for
the nMIS transistor.
[0085] Next, materials with another structure will be explained
briefly.
(NaCl type (Rocksalt Structure))
[0086] Such material as TiO (the work function of 4.1 eV and the
electric resistivity of 3.times.10.sup.-4 .OMEGA.cm), VO (the work
function of 4.3 eV and the electric resistivity of
2.times.10.sup.-3 .OMEGA.cm), and NbO (the work function of 4.2 eV
and the electric resistivity of 1.5.times.10.sup.-5 .OMEGA.cm) are
proposed. However, since such a possibility is high that each of
the materials loses its electric conductivity due to advance of
oxidation, further research must be conducted in order to use the
material.
(Corundum Type)
[0087] Oxidation advances in Ti.sub.2O.sub.3 like the above.
V.sub.2O.sub.3 has a work function of 4.4 eV and an electric
resistivity of 1.times.10.sup.-3 .OMEGA.cm, and is electrically
conductive oxide. However, since such a possibility is high that
the material loses its electric conductivity due to advance of
oxidation, further research must be conducted in order to use the
material.
(Gate Electrode Material for pMIS Transistor)
[0088] Next, electrically conductive oxides used as gate electrode
material for the pMIS transistor will be examined. For the
examination, an important hint is provided from electronic physical
properties of an insulating oxide such as Perovskite type
SrTiO.sub.3 or rutile type TiO.sub.2 like the above. The electron
affinity of each of these materials is about 4.1 eV. The conduction
band of the material comes from Ti.
[0089] In case of the Perovskite type SrTiO.sub.3, electrically
conductive oxide for the pMIS transistor can be obtained by
introducing material with electrodes of the number more by two or
more into the Ti site. At that time, the conduction band is
constituted with material introduced newly. The position of the
work function obtained from the newly produced band depends on the
material. Such a fact is collectively shown below. In the
following, the work function and the electric resistivity are shown
in parentheses.
[0090] SrWO.sub.3 (4.77 eV and 5.times.10.sup.-3 .OMEGA.cm);
SrMoO.sub.3 (4.82 eV and 4.times.10.sup.-4 .OMEGA.cm); SrCrO.sub.3
(4.9 eV and 5.times.10.sup.-4 .OMEGA.cm); SrReO.sub.3 (4.79 eV and
1.times.10.sup.-4 .OMEGA.cm); SrTcO.sub.3 (4.89 eV and
1.times.10.sup.-4 .OMEGA.cm); SrMnO.sub.3 (4.99 eV and
1.times.10.sup.-4 .OMEGA.cm); SrOsO.sub.3 (5.1 eV and
6.times.10.sup.-5 .OMEGA.cm); SrRuO.sub.3 (5.1 eV and
3.times.10.sup.-5 .OMEGA.cm); SrFeO.sub.3 (5.2 eV and
5.times.10.sup.-5 .OMEGA.cm); SrIrO.sub.3 (5.05 eV and
5.times.10.sup.-5 .OMEGA.cm); SrRhO.sub.3 (5.15 eV and
7.times.10.sup.-5 .OMEGA.cm); SrCoO.sub.3 (5.25 eV and
5.times.10.sup.-5 .OMEGA.cm); SrPtO.sub.3 (5.1 eV and
5.times.10.sup.-4 .OMEGA.cm); SrPdO.sub.3 (5.2 eV and
5.times.10.sup.-4 .OMEGA.cm); and SrNiO.sub.3 (5.3 eV and
5.times.10.sup.-4 .OMEGA.cm).
[0091] Here, it has been found that the value of the work function
hardly depends on the amount of material introduced newly. This is
because a band width changes according to the amount of material
introduced into the B site but the position of Fermi level hardly
changes. Since the number of participating electrons is rapidly
increased, the electric resistivity largely depends on the amount
of material. Basically it is preferable that the number of
electrons is increased. More specifically, for example, Sr(Ti,
Ru)O.sub.3 does not depend on the amount of Ru (several % up to
100%), where the work function becomes 5.1 eV. Incidentally, Sr(Ti,
Ru)O.sub.3 does not develop excellent conductivity unless the
amount of Ru is 50% or more. When the amount of Ru is 50% or more,
Sr(Ti, Ru)O.sub.3 develops excellent conductivity in a range of the
amount up to 100%.
[0092] In the Perovskite structure, the conductivity can be
controlled even by an A site defect. As promising materials, there
are SrxPeO.sub.3, SrxWO.sub.3, SrxMoO.sub.3 and SrxNbO.sub.3.
Incidentally, SrxNbO.sub.3 has a work function for the nMIS
transistor. At that time, the electric resistivity becomes
10.sup.-5 .OMEGA.cm or less, so that oxide with very low
resistivity can be obtained. Here, the A site is not required to be
Sr, but it may be alkaline earth metal or rare earth metal.
[0093] Next, the rutile structure will be examined. There are many
electrically conductive oxides suitable for the pMIS transistor.
The discussion about only the B site portion in the Perovskite
structure may be applied to the rutile structure as it is.
Especially, since the following electrically conductive materials
are effective since their electric resistivities are low.
[0094] WO.sub.2 (4.77 eV, 5.times.10-3 .OMEGA.cm); MoO.sub.2 (4.82
eV, 4.times.10.sup.-4 .OMEGA.cm); CrO.sub.2 (4.9 eV,
5.times.10.sup.-4 .OMEGA.cm); ReO.sub.2 (4.79 eV, 1.times.10.sup.-4
.OMEGA.cm); TcO.sub.2 (4.89eV, 1.times.10.sup.-4 .OMEGA.cm);
MnO.sub.2 (4.99 eV, 1.times.10.sup.-4 .OMEGA.cm); OsO.sub.2 (5.1
eV, 6.times.10.sub.-5 .OMEGA.cm); RuO.sub.2 (5.1 eV,
3.times.10.sup.-5 .OMEGA.cm); FeO.sub.2 (5.2 eV, 5.times.10.sup.-5
.OMEGA.cm); IrO.sub.2 (5.05 eV, 5.times.10.sup.-5 .OMEGA.cm);
RhO.sub.2 (5.15 eV, 7.times.10.sup.-5 .OMEGA.cm); CoO.sub.2 (5.25
eV, 5.times.10.sup.-5 .OMEGA.cm); PtO.sub.2 (5.1 eV,
5.times.10.sup.-4 .OMEGA.cm); PdO.sub.2 (5.2 eV, 5.times.10.sup.-4
.OMEGA.cm); and NiO.sub.2 (5.3 eV, 5.times.10.sup.-4 .OMEGA.cm)
[0095] In the above, the work function and the electric resistivity
are shown in parentheses.
[0096] In the above, the electrically conductive oxides suitable
for the nMIS transistor and the pMIS transistor have been
described.
[0097] Next, an actual film forming method will be described. When
the gate electrodes for the nMIS transistor and the pMIS transistor
are produced independently of each other, it is only required to
select proper electrically conductive oxides from the above to
perform film forming, where any problem does not occur when
optimization of material has been achieved. However, when a film is
desired to be formed as simply as possible, for example, a method
is considered which produces an electrically conductive electrode
for an nMIS transistor and introduces other material into only a
portion for a pMIS transistor by ion implantation or thermal
diffusion to reform the portion for the pMIS transistor. For
example, a method is considered which first produces a (Sr.sub.1-y,
La.sub.y) TiO.sub.3 film (0.ltoreq.y.ltoreq.1) where a work
function is about 4.1 eV to introduce Ru into a pMIS portion by
diffusion. At that time, a (Sr, La).sub.x(Ti, Ru)O.sub.3 film
(0.ltoreq..times..ltoreq.1) is formed on a pMIS transistor portion,
where the work function is about 5.1 eV. Here, post-introduction of
the B site material with the Perovskite structure is carried out,
which serves to reduce a ratio of the A site material to the B site
material. Reforming for the pMIS transistor can be achieved as the
result of Ru introduction itself, and the electric resistivity can
be further reduced by introduction of the A site defect.
[0098] Here, such a fact is understood that the value of the work
function be rapidly changed by introduction of Ru in a certain
amount or more so that it is changed to a value suitable for the
pMIS transistor in a stepwise manner. The rapid change has a much
significant meaning. That is, the rapid change means that, since
decided values determined depending on the material to be used can
be used in the nMIS transistor or the pMIS transistor region, the
work function does not fluctuate at all for each MIS transistor so
that an excellent MIS which does not cause characteristic
fluctuation can be produced. The Ru amount causing rapid change of
the work function depends on the amount of La. When the Ru amount
to the value of y in the (Sr.sub.1-y, La.sub.y) TiO.sub.3 film is
0.3.times.y or more, the work function jumps to 5.1 eV. In view of
the electric resistivity, however, it is desirable that the Ru
amount to Ti is 0.5 or more (50% or more). Not only Ru but also
material to be introduced into the B side is introduced as much as
possible, because the electric resistivity is made as small as
possible. In this meaning, a method which forms a SrRuO.sub.3 film
on the (Sr.sub.1-y, La.sub.y) TiO.sub.3 for the pMIS transistor
portion to introduce the Ru into the B site utilizing thermal
diffusion will also be effective in the above process.
[0099] As described above, the work function of the electrically
conductive oxide now under consideration changes stepwise, and the
work function takes the same value stably even if the amount of
introduction changes finely. This means that threshold fluctuation
does not occur for each transistor, which is significantly
important. In the present situation, a problem about fluctuation of
the work function arises, especially, in nitride or the like.
Effectiveness of the present invention can be found in the
problem.
[0100] In view of the electric conductivity, it is advantageous
that the B site material is moved to a defect side of the B site
material by introduction of the A site material for the nMIS
transistor (this is another expression of the excessive
introduction of the A site material as described above), and it is
also advantageous that the A site material is moved to the defect
side of the A site material by introduction of the B site material
for the pMIS transistor.
[0101] In the above embodiment, the material for the nMIS
transistor is first formed in a film. On the contrary, it is
considered that the material for the pMIS transistor is first
formed in a film and a portion of the film is then reformed for the
nMIS transistor. For example, there is such a case that Sr(Tr,
Ru)O.sub.3 is formed in a film for the pMIS transistor, and
reformation is made for the nMIS transistor by introducing La into
a portion of the film. The work functions are respectively about
5.1 eV for the pMIS transistor and about 4.0 eV for the nMIS
transistor.
[0102] It is also possible to first form an insulating film of
SrTiO.sub.3 and then introduce La and Ru into portions of the film
for the nMIS transistor and the pMIS transistor, respectively. In
that case, defects occurs in the B site and the A site,
respectively, thereby allowing formation of a film with a low
electric resistivity.
[0103] In some materials, it is also made possible to perform a
full processing for processes for producing an electrode film and a
thin film with a high-k dielectric constant by causing an electrode
and a dielectric film to react with each other or causing the
electrode and a substrate Si to react with each other during film
forming or during annealing operation after film forming. In the
full processing process, an interface between the dielectric and
the electrode is made considerably stable, because there are many
common portions between components of the dielectric film and
components of the electrode. Materials suitable for this processing
are limited, where it is required that a stable silica film is
produced but a layer with a low-k dielectric constant (SiO.sub.2)
is not produced. However, in case of the gate electrode material
for the pMIS transistor, for example, SrRuO.sub.3, SiO.sub.2
eventually occurs in an interface between Si and an electrode. This
results from such a fact that RuO.sub.2 or the like is more
unstable than SiO.sub.2. It should be avoided to cause the
electrode material for the pMIS transistor to grow directly on Si.
That is, it is understood that it is unsuitable to cause the
electrode material for the pMIS transistor to grow on the Si
substrate to cause a reaction layer to serve as the gate insulating
film. In that case, it is necessary to produce the electrode after
producing the gate insulating film. Since it is the matter of
course to employ very stable material as the oxide for the gate
insulating film, when the oxide electrode described above is
further placed on the gate insulating film, such an advantageous
state occurs that, when oxygen shortage occurs in the dielectric,
oxygen is supplied from the electrode to the dielectric.
[0104] Next, the electrode for the nMIS transistor will be
examined. In that case, it is understood that a large amount of
material which does not cause a low-k dielectric even if the
electrode is formed directly on the Si substrate is contained.
Elements which allow such a phenomenon are very restrictive, as
described below.
[0105] Be, Mg, Ca, Sr, Ba, Al, Sc, Y, La, Ti, Zr, Hf, and Ce. For
example, when direct production on the Si substrate is performed
using (La, Sr) TiO.sub.3 which is an electrode material for an nMIS
transistor, a silicate electrode thin film with a high-k dielectric
mainly containing La silicate is formed thereon. Here, when
nitrogen is introduced in the formation, it is made possible to
restrict diffusion of metal into the silicate film remarkably.
Therefore, even if the formed electrode film is caused to pass
through a process with a high temperature, silicate is present
stably without being crystallized. Since nitrogen also serves to
improve dielectric constant of the silicate film, the nitrogen
introduction is very effective. When the electrode film is formed
on the Si substrate in this manner and the dielectic film is formed
in a process for the electrode film forming, a process performed
after the film forming process, or both the processes, a process
for producing a dielectric material film can be made unnecessary.
Further, since the silicate film is naturally produced in the
process, it is possible to produce an electrode for an nMIS
transistor with very stable and excellent interfaces between the
substrate and the dielectric material and between the dielectric
material and the electrode.
[0106] The dielectric material film on the pMIS transistor region
can be formed in lamp through the process for producing the
electrode for the nMIS transistor, the process for dielectric film
generation, and the process for reforming the gate electrode in the
pMIS transistor region. For example, the dielectric film formation
may be achieved by processes of directly producing (La,
Sr)TiO.sub.3 film on Si, generating silicate film on the interface,
and diffusing SrRuO.sub.3 into the pMIS transistor region.
[0107] Alternatively, the dielectric films on the nMIS transistor
and the pMIS transistor can be formed in lamp through processes of
first producing an insulating film, generating a dielectric film
and reforming gate electrodes on the nMIS transistor region and the
pMIS transistor region. For example, the dielectric film formation
may be achieved by processes of directly producing SrTiO.sub.3 film
on Si, generating a silicate film on an interface, diffusing La (or
Nb) into the nMIS transistor region, and diffusing Ru into the pMIS
transistor region.
[0108] In the present invention, since stability of the electrode
materials is very high, various materials can be used for the gate
insulating film. SiO.sub.2, SiON, silicate, or nitrides of
silicate, metal oxides, or metal nitride can be used for the gate
insulating film. A reaction film obtained by each of the insulating
films and the electrically conductive oxide introduced in the
invention or a stacked film (a stacked film of an non-reacted
portion and the reaction film) may be used as the insulating film.
As described above, it is possible to use, as the insulating film,
the reaction layer produced when the electrically conductive oxide
according to the present invention is formed directly on the Si
substrate. On the other hand, it is not possible to use an ordinary
metal film as the insulating film in such a board range. For
example, this is because ordinary metal enters in the SiON film to
increase current leakage or causes interface roughness to increase
current leakage in some cases.
[0109] As explained above, according to the embodiment, it is made
possible to obtain an n type and p type MISFETs with a low
threshold voltage, where roughness of an interface between a gate
insulating film and a gate electrode due to oxidation or
characteristic lowering of the gate insulating film due to
insulation of the gate electrode does not occur. The gate electrode
does not have catalytic property and a simple metal is prevented
from being diffused in the gate insulating film or in a silicon
substrate unnecessarily. A MIS transistor with remarkably reduced
fluctuation in threshold for each transistor and with a low
threshold voltage can be obtained.
Second Embodiment
[0110] Next, a method for manufacturing a semiconductor device
according to the present invention will be explained with reference
to FIG. 2 to FIG. 6. FIGS. 2 to 6 are sectional views of a
semiconductor device in respective manufacturing steps in the
manufacturing method according to the embodiment.
[0111] As shown in FIG. 2, first, device isolation regions 13 which
separate a formation region for a pMIS transistor and a formation
region for an nMIS transistor on a semiconductor substrate, for
example, a silicon substrate 11. The device isolation regions 13
are formed, for example, by STI (Shallow Trench Isolation). The
device isolation regions 13 can be formed, for example, by LOCOS
(Local Oxidation of Silicon) technique, too. Thereafter, a P well
15 is formed on the formation region for an nMIS transistor, and an
n well 17 is formed on the formation region for a pMIS transistor.
Next, impurities are introduced into the p well 15 and the n well
17 in order to adjust threshold voltages. Formation of the P well
15 and the n well 17 can be carried out, for example, by ion
implantation process using a mask with openings corresponding to
the respective regions.
[0112] Next, a gate insulating film 19 is formed on the silicon
substrate 11. The gate insulating film 19 is formed by depositing
oxynitrided hafnium silicate film with a thickness of 3 nm at a
substrate temperature of 400.degree. C. according to CVD (Chemical
Vapor Deposition) process. Thereafter, an electrode film 21 formed
of (La, Sr) TiO.sub.3 for an nMIS transistor is formed on the gate
insulating film 19 so as to have a thickness of 50 nm according to
CVD process (refer to FIG. 2).
[0113] Next, photoresist is applied on the electrode film 21, and a
resist pattern 25 having an opening corresponding to the formation
region of the pMIS transistor is formed according to lithography
technique (refer to FIG. 3). Ru is introduced in the electrode film
21 on the formation region of the pMIS transistor according to ion
implantation process using the resist pattern 25 as a mask, and an
electrode film 23 formed of (La, Sr) (Ti, Ru)O.sub.3 for the pMIS
transistor is obtained utilizing thermal diffusion. According to
the ion implantation process, ion implantation is performed such
that the Ru concentration in the electrode film 23 formed of (La,
Sr) (Ti, Ru)O.sub.3 for the pMIS transistor becomes 50% at a ratio
of Ru/(Ru+Ti).
[0114] The thermal diffusion is performed, for example, in nitrogen
atmosphere at a processing temperature of 1050.degree. C. for a set
processing time of 30 seconds, after the resist pattern 25 is
removed. As the heat treatment, an optimal method can be selected
from the existing heat treatment methods such as, for example,
spike anneal, laser anneal, and lamp anneal, and the heat treatment
can be performed at a stage of an activating heat treatment for
impurities conducted later.
[0115] In the formation of the electrode film for the pMIS
transistor, the electrode film 23 formed of (La, Sr) (Ti,
Ru)O.sub.3 for the pMIS transistor can be obtained by forming a
SrRuO.sub.3 film on the pMIS transistor region according to CVD
process, instead of the ion implantation process, to perform
thermal diffusion.
[0116] Next, photoresist is applied on the electrode films 21 and
23, the photoresist is patterned according to ordinary lithography
technique, and a resist pattern 27 for forming gate electrodes is
formed (refer to FIG. 4). The electrode films 21 and 23 are
patterned by conducting etching using the resist pattern 27 as a
mask so that respective gate electrodes 21 and 23 are obtained
(refer to FIG. 4).
[0117] Subsequently, after the resist pattern 27 is removed, a
resist pattern (not shown) which covers only the formation region
for the pMIS transistor is formed, and a low concentration n-type
diffusion layer 29 is formed by doping impurities in the formation
region for the nMIS transistor using the gate electrode 21 as a
mask (refer to FIG. 5). After the resist pattern is removed, a
resist pattern (not shown) which covers only the formation region
for the nMIS transistor is formed, and a low concentration p-type
diffuison layer 31 is formed by doping impurities into the
formation region for the pMIS transistor using the gate electrode
23 as a mask (refer to FIG. 5). Thereafter, the resist pattern is
removed.
[0118] Next, as shown in FIG. 6, side walls 33 formed of insulating
material are formed on sides of the gate electrodes 21 and 23 using
a well-known technique. A resist pattern (not shown) which covers
the formation region for the pMIS transistor is formed, and an n
type source-drain diffusion layer 35 is formed by doping impurities
into the formation region for the nMIS transistor using the gate
electrode 21 and the side walls 33 as masks (refer to FIG. 6).
After the resist pattern is removed, a resist pattern (not shown)
which covers the formation region for the nMIS transistor is
formed, and a p type source-drain diffusion layer 37 is formed by
doping impurities into the formation region for the pMIS transistor
using the gate electrode 23 and the side walls 33 as masks (refer
to FIG. 6). Thereafter, as shown in FIG. 6, an nMIS transistor and
a pMIS transistor are completed by removing the resist pattern.
[0119] In the manufacturing method according to this embodiment,
formation of the gate electrode 21 of the nMIS transistor and the
gate electrode 23 of the pMIS transistor is achieved by performing
only one step of forming the electrode film 21, a step of forming
the resist pattern 25 for using a mask for Ru introduction, a step
of forming the resist pattern 27 applied when the gate electrode
portions are cut out, and a step of patterning the gate electrodes.
Therefore, the number of steps in this embodiment is reduced as
compared with a case that the gate electrode 21 of the nMIS
transistor and the gate electrode 23 of the pMIS transistor are
formed separately of each other, which results in easiness of
manufacturing.
[0120] In the manufacturing method according to the embodiment, the
gate electrode 21 of the nMIS transistor is the (La, Sr)TiO.sub.3
film, where the work function is 4.05 eV. On the other hand, the
gate electrode 23 of the pMIS transistor is the (La, Sr)(Ti,
Ru)O.sub.3 film produced by ion-implanting Ru into the electrode
film 21, where the work function is 5.10 eV. Since the work
function at the lower limit of the conduction band of silicon is
4.05 eV, and the work function of the valence band is 5.17 eV, it
is possible to reduce the threshold voltages for both the nMIS
transistor and the pMIS transistor to 0.4V or less.
(First Modification)
[0121] Incidentally, as a first modification of the first
embodiment, nMIS transistors and pMIS transistors were produced,
while the gate electrode materials explained in the first
embodiments were exchanged variously. It was confirmed that these
transistors could be operated at low thresholds.
(Second Modification)
[0122] Further, a second modification of the embodiment will be
explained. In the second modification, a step of directly forming
oxynitrides (La, Sr) TiON film on silicon substrate 11 as the gate
electrode film was conducted without conducting a step of forming a
gate insulating film 19 on the silicon substrate 11. Thereafter,
anneal was performed in nitrogen atmosphere at a substrate
temperature of 600.degree. C. so that oxynitrided lanthanum
silicate film with a thickness of 2 nm was formed on an interface
between the silicon substrate and the gate electrode film. Steps
subsequent to this step can be performed in the same manner as
those in the second embodiment by regarding this interface layer
(oxynitrided lanthanum silicate film) as the gate insulating film
19. Since the interface layer is produced due to an interface
reaction with the silicon substrate, defects of the interface
between the silicon substrate and the gate insulating film are
remarkably reduced. Therefore, when mobility is measured after
manufacturing the MIS transistor, the MIS transistor with a very
high mobility can be obtained as compared with that manufactured by
the manufacturing method of the second embodiment. Since the
interface between the gate insulating film and the gate electrode
is the reaction layer, interface defects are reduced, so that an
excessive reaction at the interface defects, for example, a
reaction of La silicate and water, does not occurs. Therefore, it
is possible to keep the characteristics of the gate insulating film
and the electrodes in an excellent state.
Third Embodiment
[0123] Next, a method for manufacturing a semiconductor device
according to a third embodiment of the present invention will be
explained with reference to FIG. 7 to FIG. 15. The manufacturing
method is constituted so as to perform formation of a gate
electrode by a damascene process. FIGS. 7 to 15 are sectional views
of manufacturing steps performed in the manufacturing method of the
embodiment.
[0124] As shown in FIG. 7, first, device isolation regions 13 which
separate a formation region for a pMIS transistor and a formation
region for an nMIS transistor on a silicon substrate 11 are formed
like the second embodiment. Subsequently, a dummy gate insulating
film 20 to be removed in a step described later is formed of
silicon oxide film with a thickness of, for example, 20 nm on the
silicon substrate. Next, for example, a dummy gate electrode film
22 to be removed in a step described later is formed of a
polycrystal silicon film with a thickness of, for example, 80 nm
according to CVD process.
[0125] Next, after photoresist is applied on the dummy gate
electrode film 22, the photoresist is patterned according to
lithography technique, so that a resist pattern 27 for forming a
dummy gate electrode is formed (refer to FIG. 8). The dummy gate
electrode film 22 is patterned by performing etching using the
resist pattern 27 as a mask, so that the dummy gate electrode 22
for a pMIS transistor and the dummy gate electrode 22 for an nMIS
transistor are formed. Thereafter, the resist pattern 27 used as
the mask is removed.
[0126] Next, a resist pattern (not shown) which covers a formation
region for the pMIS transistor and has an opening corresponding to
a formation region for the nMIS transistor is formed, and n type
impurities (for example, phosphorus or arsenic) is introduced into
a p well region 15 using the resist pattern and the dummy gate
electrode 22 as masks, so that low concentration diffusion layers
29 for the nMIS transistor are formed. Thereafter, the resist
pattern is removed (refer to FIG. 9). Then, a resist pattern (not
shown) which covers a formation region for the nMIS transistor and
has an opening corresponding to the formation region for the pMIS
transistor is formed, and p type impurities (for example, boron or
boron difluoride) is introduced into an n well region 17 using the
resist pattern and the dummy gate electrode 22 as masks, so that
low concentration diffusion layers 31 for the pMIS transistor are
formed. Thereafter, the resist film is removed (refer to FIG.
9).
[0127] Next, heat treatment is performed. As conditions for the
heat treatment, setting is made such that atmosphere is nitrogen, a
processing temperature is 10500, and a processing time is 30
seconds. Incidentally, as the heat treatment, a proper method can
be selected properly from existing heat treatment methods such as,
for example, spike anneal, laser anneal, or lamp anneal. The
impurities in the low concentration diffusion layer 29, 30, the p
well region 15, and the n well region 17 are activated by the heat
treatment.
[0128] Next, after an insulating film is formed on the whole
surface, the insulating film is etched back, so that side walls 33
are formed on respective side portions of the dummy gate electrode
20 (refer to FIG. 10). The insulating film is formed by depositing
silicon nitride, for example, according to chemical vapor
deposition process. Thereafter, a resist pattern (not shown) which
covers the formation region for the pMIS transistor and has an
opening corresponding to the formation region for the nMIS
transistor is formed. N type impurities (for example, phosphorus or
arsenic) are introduced into the p well region 15 using the resist
pattern, the dummy gate electrodes 22, and the side walls 33 as
masks, so that source-drain diffusion layers 35 for the nMIS
transistor are formed on the p well region 15 on the both sides of
the dummy gate electrode 20 via the low concentration diffusion
layers 29. Thereafter, the resist pattern is removed (refer to FIG.
10). Next, a resist pattern (not shown) which covers the formation
region for the nMIS transistor and has an opening corresponding to
the formation region for the pMIS transistor is formed. P type
impurities (for example, boron or boron difluoride) is introduced
into the p well region 17 using the resist pattern, the dummy gate
electrode 22, and the side walls 33 as masks, so that source-drain
diffusion layers 37 for the pMIS transistor are formed on the p
well region 17 on the both sides of the dummy gate electrode 22 via
the low concentration diffusion layers 31. Thereafter, the resist
pattern is removed (refer to FIG. 10).
[0129] Next, an inter-layer insulating film which covers the dummy
gate electrodes 22 is formed using CVD process. The inter-layer
insulating film is formed of, for example, a silicon oxide film.
Incidentally, the inter-layer insulating film is formed so as to be
at least higher than the dummy gate electrode 22. Then, a surface
of the inter-layer insulating film 40 is planarized and an upper
faces of the dummy gate electrodes 22 are exposed according to CMP
(Chemical Mechanical Polishing) (refer to FIG. 11).
[0130] Next, as shown in FIG. 12, the dummy gate electrodes 22 and
the dummy gate insulating films 20 positioned under them are
removed by etching process, so that gate grooves 41 are formed.
Accordingly, the dummy gate electrodes 22 and the dummy gate
insulating films 20 must be formed of materials having etching
rates higher than those of the side walls 33 and the inter-layer
insulating film 40.
[0131] As shown in FIG. 13, for example, oxynitrided hafnium
silicate is deposited on inner faces of the gate grooves 41 in a
thickness of 4 nm so that gate insulating films 43 are formed using
CVD process. At that time, an oxynitrided hafnium silicate film
(not shown) is also formed on the inter-layer insulating film 40.
Further, electrode films 45 formed of (La, Sr) TiO.sub.3 are formed
so as to fill in the gate electrodes 41 using CVD process. The
electrode film and the oxynitrided hafnium silicate film formed on
the inter-layer insulating film 40 is removed according to CMP.
Thus, the gate electrodes 45 embedded into the gate grooves 41 via
the gate insulating films 43 are formed (refer to FIG. 13).
[0132] Next, as shown in FIG. 14, photoresist is applied on the
interlayer insulating film 40 and a resist pattern 47 which is then
formed with opening 47a corresponding to the formation region for
the pMIS transistor is formed using lithography technique. Ru is
introduced into the gate electrode 45 on the formation region for
the pMIS transistor by ion implantation using the resist pattern 47
as a mask, so that the gate electrode 45 is reformed into a gate
electrode 49.
[0133] Subsequently, after the resist pattern 47 is removed, heat
treatment is performed. As conditions for the heat treatment,
setting is made such that atmosphere is nitrogen, a processing
temperature is 550.degree., and a processing time is 3 minutes.
Incidentally, as the heat treatment, selection can be made-properly
from existing heat treatment methods such as, for example, spike
anneal, laser anneal, and lamp anneal. The gate electrode 45 is
reformed to the gate electrode 49 for the pMIS transistor due to
diffusion of Ru into the gate electrode 49 by the heat treatment.
In that case, since activation at a low temperature is
satisfactory, a range of materials usable for the gate insulating
film is expanded largely. Accordingly, such a material that
dielectric is high but crystallization takes place due to heat, for
example, ZrO.sub.2, HfO.sub.2 can be used for the gate insulating
film.
[0134] Thus, the gate electrode 45 for the nMIS transistor and the
gate electrode 49 for the pMIS transistor are formed in the gate
grooves 41 via the gate insulating films 43, so that an nMIS
transistor and a pMIS transistor are completed (refer to FIG.
15).
[0135] In the manufacturing method of the embodiment, after the
gate electrode 45 for the nMIS transistor and the gate electrode 49
for the pMIS transistor are formed from (Sr, La) TiO.sub.3, the
(Sr, La)(Ti, Ru)O.sub.3 gate electrode 49 is formed by selectively
introducing Ru into the gate electrode for the pMIS transistor.
Accordingly, the gate electrode 45 for the nMIS transistor and the
gate electrode 49 for the pMIS transistor can be formed by only one
film forming step for the (Sr, La)TiO.sub.3 film and two
lithography steps including the forming step of the resist mask
used when patterning is conducted on the dummy gate electrodes
filled with (Sr, La)TiO.sub.3 formed in a film due to use of the
mask for Ru introduction, and two removal steps conducted when the
dummy gate electrodes are patterned and when removal is performed.
Therefore, the manufacturing method of the embodiment is reduced in
number of steps as compared with the conventional manufacturing
method which is constituted so as to form a metal film for forming
the gate electrode for the pMIS transistor and a metal film for
forming the gate electrode for the nMIS transistor separately of
each other, which results in simplicity and convenience.
[0136] In the manufacturing method according to the embodiment, the
gate electrode 45 for the nMIS transistor is the (La, Sr)TiO.sub.3
film, where the work function is 4.05 eV. On the other hand, the
gate electrode 49 for the pMIS transistor is the (La, Sr)(Ti,
Ru)O.sub.3 film produced by ion-implanting Ru into the electrode
45, where the work function is 5.1 eV. Since the work function at
the lower limit of the conduction band of silicon is 4.05 eV, and
the work function of the valence band is 5.17 eV, it is possible to
reduce the threshold voltages for both an N channel transistor and
a P channel transistor to 0.4V or less.
(First Modification)
[0137] Incidentally, as a first modification of the third
embodiment, nMIS transistors and pMIS transistors were produced,
while the gate electrode materials explained in the third
embodiments were exchanged variously. It was confirmed that these
transistors could be operated at low thresholds.
(Second Modification)
[0138] A second modification of the third embodiment will be
explained. In the second modification, first, a step of directly
forming oxynitrides (La, Sr) TiON in the gate grooves 41 as the
gate insulating films was conducted without forming the gate
insulating films 43 in the gate grooves 41. Thereafter, anneal is
performed at a substrate temperature of 550.degree. C. in nitrogen
atmosphere so that an oxynitrided lanthanum silicate film with a
thickness of 2 nm is formed at an interface between the silicon
substrate and the gate electrode film. By regarding the interface
layer (oxynitrided lanthanum silicate film) as the gate insulating
film 43, steps subsequent to the above step can be conducted in the
same manner as the those in the third embodiment. Since the
interface layer is produced due to interface reaction with the
silicon substrate, defects in the interface between the silicon
substrate and the gate insulating film are significantly reduced.
Therefore, when mobility is measured after manufacturing the MIS
transistor, the MIS transistor with a very high mobility can be
obtained as compared with that manufactured by the manufacturing
method of the second embodiment. Since the interface between the
gate insulating film and the gate electrode is the reaction layer,
interface defects are reduced, so that an excessive reaction at the
interface defects, for example, a reaction of La silicate and
water, does not occurs. Therefore, it is possible to keep the
characteristics of the gate insulating film and the electrodes in
an excellent state.
[0139] The material for the gate insulating film, the forming
method of the gate insulating film and the film thickness thereof,
the material for the gate electrode film, the forming method of the
gate electrode film and the film thickness thereof, the material
for conducting conversion between the nMIS transistor and the pMIS
transistor (Ru is used in the above embodiment), the introducing
method of the material and the introduction amount thereof, and the
structures of the transistors are simply illustrative. When the
work function value of the gate electrode for the pMIS transistor
is a value approximating to the upper limit work function value of
the valence band of silicon and the work function value of the gate
electrode for the nMIS transistor is a value approximating to the
lower limit work function value of the conduction band of silicon,
the above items can be changed properly.
[0140] As explained above, according to each embodiment of the
present invention, since the work function of the gate electrode
for the pMIS transistor can be brought close to the upper limit of
the valence band of silicon and the work function of the gate
electrode for the nMIS transistor can be brought close to the lower
limit of the conduction band of silicon, it is made possible to
reduce the high threshold voltage of the metal gate electrode
problematic in the conventional art to about 0.4V or less. The
fluctuation in threshold for each transistor can be reduced
remarkably.
[0141] According to the manufacturing methods according to the
second and third embodiments, when metal gate electrodes with
different work functions are formed in the nMIS transistor and the
pMIS transistor, after an electrode film suitable for one of the
metal gate electrodes is formed on the whole surface, the work
function of the electrode on the other region is controlled by ion
implantation or thermal diffusion after film formation to be
changed largely so that both the electrodes are optimized.
Therefore, the number of steps in the embodiments is reduced as
compared with the number of steps required in the case that films
made of different metals are formed for the nMIS transistor and the
pMIS transistor. Since the work function of the gate electrode for
the pMIS transistor can be brought close to the upper limit of the
valence band of silicon and the work function of the gate electrode
for the nMIS transistor can be brought close to the lower limit of
the conduction band of silicon, it is made easy to reduce the high
threshold voltage of the metal gate electrode problematic in the
conventional art to about 0.4V or less.
[0142] According to the manufacturing methods according to the
second and third embodiments, since the work function can be
controlled freely as compared with those of the metals used
conventionally, it is unnecessary to produce an embedding-like
channel using counter doping at all, which results in step
simplification correspondingly.
[0143] In many cases, the metals used conventionally are
uncongenial with the insulating film. However, the electrically
conductive oxides according to the first embodiment of the present
invention are congenial with the oxide or the oxynitrided
insulating film, so that the range of the gate insulating films
which can be used is remarkably expanded.
[0144] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concepts as defined by the
appended claims and their equivalents.
* * * * *