U.S. patent application number 12/211074 was filed with the patent office on 2009-01-01 for method of manufacturing non-volatile memory.
This patent application is currently assigned to POWERCHIP SEMICONDUCTOR CORP.. Invention is credited to Ko-Hsing Chang, Tsung-Cheng Huang, Yan-Hung Huang.
Application Number | 20090004796 12/211074 |
Document ID | / |
Family ID | 38684315 |
Filed Date | 2009-01-01 |
United States Patent
Application |
20090004796 |
Kind Code |
A1 |
Chang; Ko-Hsing ; et
al. |
January 1, 2009 |
METHOD OF MANUFACTURING NON-VOLATILE MEMORY
Abstract
A method of manufacturing a non-volatile memory includes
providing a substrate and forming a patterned mask layer, a tunnel
dielectric layer, and a first conductive layer on the substrate.
The first conductive layer on the mask layer is removed to form
second conductive layers disposed on the sidewall of the mask layer
and the substrate. The mask layer is then removed and a source
region is formed. Subsequently, an inter-gate dielectric layer and
a third conductive layer are formed on the substrate. The third
conductive layer is patterned to cover the source region and a
portion of the second conductive layer on both sides of the source
region. A portion of the inter-gate dielectric layer and the second
conductive layers are then removed. After that, a dielectric layer,
a fourth conductive layer, and a drain region are formed,
respectively.
Inventors: |
Chang; Ko-Hsing; (Hsinchu,
TW) ; Huang; Tsung-Cheng; (Hsinchu City, TW) ;
Huang; Yan-Hung; (Hsinchu County, TW) |
Correspondence
Address: |
JIANQ CHYUN INTELLECTUAL PROPERTY OFFICE
7 FLOOR-1, NO. 100, ROOSEVELT ROAD, SECTION 2
TAIPEI
100
TW
|
Assignee: |
POWERCHIP SEMICONDUCTOR
CORP.
Hsinchu
TW
|
Family ID: |
38684315 |
Appl. No.: |
12/211074 |
Filed: |
September 15, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11308667 |
Apr 20, 2006 |
7446370 |
|
|
12211074 |
|
|
|
|
Current U.S.
Class: |
438/264 ;
257/E21.422; 257/E21.682; 257/E27.103; 438/267 |
Current CPC
Class: |
H01L 27/115 20130101;
H01L 27/11519 20130101; H01L 27/11521 20130101 |
Class at
Publication: |
438/264 ;
438/267; 257/E21.422 |
International
Class: |
H01L 21/336 20060101
H01L021/336 |
Claims
1. A method of manufacturing the non-volatile memory, comprising:
providing a substrate; forming a patterned mask layer on the
substrate; forming a tunnel dielectric layer and a first conductive
layer on the substrate; removing the first conductive layer on the
top of the mask layer to form a plurality of second conductive
layers on the sidewall of the mask layer and the substrate;
removing the mask layer; forming a source region in the substrate
between the second conductive layers; forming an inter-gate
dielectric layer on the substrate; forming a third conductive layer
on the inter-gate dielectric layer; patterning the third conductive
layer, the inter-gate dielectric layer, and the second conductive
layers; forming a dielectric layer on the substrate and on the
exposed sidewalls of the third conductive layer and the second
conductive layers; forming a fourth conductive layer on the
sidewall of the third conductive layer; and forming a drain region
in the substrate outside the fourth conductive layer.
2. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the cross-section of each of the patterned
second conductive layers present an L-shape, and the patterned
second conductive layer comprises a central region which is
perpendicular to the substrate and a lateral region which is
parallel to the substrate, and the central region is adjacent to
the source region.
3. The method of manufacturing the non-volatile memory as claimed
in claim 2, wherein the material of the second conductive layers
comprises doped polysilicon.
4. The method of manufacturing the non-volatile memory as claimed
in claim 3, wherein a process of forming the dielectric layer on
the sidewall of the lateral region of the second conductive layer
comprises thermal oxidation process.
5. The method of manufacturing the non-volatile memory as claimed
in claim 4, wherein after the thermal oxidation process, the
sidewall of the lateral region takes the shape of a circular arc
curve.
6. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the step of patterning the third conductive
layer comprises: forming a patterned photoresist layer on the third
conductive layer; removing a portion of the third conductive layer
by using the patterned photoresist layer as a mask; and removing
the patterned photoresist layer.
7. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the step of patterning the third conductive
layer further comprises removing a portion of the third conductive
layer by using the inter-gate dielectric layer as a stop layer.
8. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the method of patterning the second conductive
layers further comprises using the patterned third conductive layer
as a self-aligned mask.
9. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the step of patterning the inter-gate
dielectric layer and the second conductive layers further comprises
patterning the tunnel dielectric layer.
10. The method of manufacturing the non-volatile memory as claimed
in claim 1, wherein the method of forming the tunnel dielectric
layer comprises thermal oxidation.
11. A method of manufacturing the non-volatile memory, comprising:
providing a substrate, wherein a plurality of isolation structures
is formed on the substrate in arrays and a mask layer is filled in
the intervals between the isolation structures; removing a portion
of the mask layer and leaving the mask layer between two adjacent
rows of the isolation structures; forming a tunnel dielectric layer
and a first conductive layer on the substrate; removing the first
conductive layer on the top of the mask layer and the top of the
isolation structures to form a plurality of second conductive
layers on two sidewalls of the mask layer and between the isolation
structures; removing portions of the isolation structures; removing
the mask layer; forming a source region in the substrate between
the second conductive layers; forming an inter-gate dielectric
layer on the substrate; forming a third conductive layer on the
inter-gate dielectric layer; patterning the third conductive layer
to cover the source region and portions of the second conductive
layers on the both sides of the source region; removing portions of
the inter-gate dielectric layer and the second conductive layers by
using the third conductive layer as the self-aligned mask; forming
a dielectric layer on the substrate and the exposed sidewalls of
the third conductive layer and second conductive layers; forming a
fourth conductive layer on the sidewall of the third conductive
layer; and forming a drain region in the substrate outside the
fourth conductive layer.
12. The method of manufacturing the non-volatile memory as claimed
in claim 11, wherein the cross-section of each of the patterned
second conductive layers presents an L-shape, and the patterned
second conductive layer comprises a central region which is
perpendicular to the substrate and a lateral region which is
parallel to the substrate, and the central region is adjacent to
the source region.
13. The method of manufacturing the non-volatile memory as claimed
in claim 12, wherein the method of forming the dielectric layer on
the sidewall of the lateral region of the second conductive layers
comprises thermal oxidation process.
14. The method of manufacturing the non-volatile memory as claimed
in claim 13, wherein after the thermal oxidation process, the
sidewall of the lateral region takes the shape of a circular arc
curve.
15. The method of manufacturing the non-volatile memory as claimed
in claim 11, wherein after the step of removing portion of the
isolation structures, the top of the isolation structures is at
least lower than that of the second conductive layers.
16. The method of manufacturing the non-volatile memory as claimed
in claim 11, wherein the step of patterning the third conductive
layer further comprises removing a portion of the third conductive
layer by using the inter-gate dielectric layer as a stop layer.
17. The method of manufacturing the non-volatile memory as claimed
in claim 11, wherein the step of removing a portion of the
inter-gate dielectric layer and the second conductive layers
further comprises removing a portion of the tunnel dielectric
layer.
18. The method of manufacturing the non-volatile memory as claimed
in claim 11, wherein the method of forming the tunnel dielectric
layer comprises thermal oxidation.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of an application Ser. No.
11/308,667, filed on Apr. 20, 2006, now allowed. The entirety of
each of the above-mentioned patent applications is hereby
incorporated by reference herein and made a part of this
specification.
BACKGROUND OF THE INVENTION
[0002] 1. Field of Invention
[0003] The present invention relates to a semiconductor device and
a manufacturing method thereof. More particularly, the present
invention relates to a non-volatile memory and a manufacturing
method thereof.
[0004] 2. Description of Related Art
[0005] Among various non-volatile memory products, EEPROM, having
the advantages that data can be stored, read, and erased more than
once and stored data will not disappear even when power is cut off,
has become a memory device widely used in personal computers and
electronic equipment.
[0006] A conventional EEPROM has a floating gate and a control
gate, which are manufactured by doped polysilicon. In order to
prevent a false determination caused by over-erasing or
over-writing when the conventional EEPROM is erasing or writing, a
select transistor is connected in series on one side of the
floating gate and the control gate, such that programming and
reading of the memory can be controlled by the transistor.
[0007] In the operation of the EEPROM, generally speaking, the
greater the gate-coupling ratio (GCR) between the floating gate and
the control gate, the lower the working voltage for the operation,
such that the operational speed and efficiency of the memory are
greatly enhanced. Since the GCR indicates the ratio of the
capacitance value between the floating gate and the control gate to
the total capacitance value of the memory, therefore, the increase
of the equivalent capacity area between the floating gate and the
control gate helps to increase the GCR.
[0008] However, along with the trend of high integrity of
integrated circuits, the area occupied by each memory cell of the
memory must be reduced, and then the linewidth of a device is also
reduced accordingly. As such, the GCR between the floating gate and
the control gate is decreased, such that the working voltage
required by the non-volatile memory must be increased, which
negatively affects the non-volatile memory applied in the field of
portable electronic products requiring low energy consumption.
Therefore, it is an important topic to manufacture a memory with
high GCR in a limited chip area.
SUMMARY OF THE INVENTION
[0009] In view of the above, the present invention is directed to
provide a non-volatile memory and a manufacturing method thereof,
wherein the GCR between gates is increased, the working voltage of
a memory is reduced, and the operating speed of the memory is
accelerated.
[0010] The present invention is further directed to provide a
non-volatile memory and a manufacturing method thereof to form a
floating gate by means of self-alignment, thereby simplifying the
manufacturing flow.
[0011] The non-volatile memory provided by the present invention
includes a first memory cell that has a substrate, a control gate,
a floating gate, and a select gate. A source region and a drain
region are disposed on the substrate. The control gate is disposed
on the substrate between the source region and the drain region.
The floating gate, disposed between the control gate and the
substrate, includes a central region which is perpendicular to the
substrate and a lateral region which is parallel to the substrate,
wherein the central region is adjacent to the source region. The
select gate is disposed on the sidewall of the control gate and the
lateral region of the floating gate and is adjacent to the drain
region.
[0012] In the aforementioned non-volatile memory, the cross-section
of the floating gate is L-shaped. The sidewall of the lateral
region of the floating gate takes the shape of, for example, a
circular arc curve.
[0013] In the aforementioned non-volatile memory, a second memory
cell having a same structure as the first memory cell is further
included, wherein the first and second memory cells are configured
mirror-symmetrically and, for example, share one source region.
[0014] In the aforementioned non-volatile memory, a tunnel
dielectric layer disposed between the bottom of the floating gate
and the substrate is further included. Furthermore, the
non-volatile memory further includes an inter-gate dielectric layer
disposed between the control gate and the substrate, and between
the control gate and the floating gate.
[0015] In the aforementioned non-volatile memory, a dielectric
layer is further included, which is disposed between the select
gate and the substrate, between the select gate and the control
gate, and between the select gate and the floating gate.
Furthermore, the dielectric layer extends to the substrate of the
drain region and to the control gate.
[0016] In the aforementioned non-volatile memory, the material of
the floating gate is, for example, doped polysilicon. The material
of the inter-gate dielectric layer is, for example, silicon
oxide/silicon nitride/silicon oxide. The material of the tunnel
dielectric layer is, for example, silicon oxide.
[0017] Because the aforementioned non-volatile memory employs an
L-shaped floating gate to enlarge the capacity area between the
floating gate and the control gate, the GCR is increased
correspondingly, and thereby the working voltage required by the
memory is reduced and the operational speed of the memory is
accelerated.
[0018] Additionally, due to the circular arc curve of the sidewall
of the lateral region of the L-shaped floating gate, it is easier
to draw the charges in the floating gate to the select gate during
an erasing operation, thereby accelerating the operational speed of
erasing.
[0019] The present invention provides a method of manufacturing a
non-volatile memory. First, a substrate is provided and a patterned
mask layer is formed on the substrate. A tunnel dielectric layer
and a first conductive layer are formed on the substrate. Then, the
first conductive layer on the top of the mask layer is removed to
form the second conductive layers disposed on the sidewall of the
mask layer and the substrate. After that, the mask layer is removed
and a source region is formed in the substrate between the second
conductive layers. Subsequently, an inter-gate dielectric layer and
a third conductive layer are formed on the substrate. The third
conductive layer is patterned to cover the source region and a
portion of the second conductive layer on the both sides of the
source region. Then, with the third conductive layer as a
self-aligned mask, a portion of the inter-gate dielectric layer and
the second conductive layers are removed. Then, a dielectric layer
is formed on the substrate and the exposed sidewalls of the third
conductive layer and the second conductive layers. A fourth
conductive layer is formed on the sidewall of the third conductive
layer. Then, a drain region is formed in the substrate outside of
the fourth conductive layer.
[0020] In the method of manufacturing the non-volatile memory, in
the step of removing the first conductive layer on the mask layer,
the cross-section of each of the patterned second conductive layers
presents an L-shape and the patterned second conductive layer
includes a central region which is perpendicular to the substrate
and a lateral region which is parallel to the substrate, wherein
the central region is adjacent to the source region.
[0021] In the method of manufacturing the non-volatile memory, the
material of the second conductive layers is, for example, doped
polysilicon. The method of forming the dielectric layer on the
sidewall of the lateral region of the second conductive layer
includes thermal oxidation.
[0022] In the method of manufacturing the non-volatile memory,
after the step of the thermal oxidation, the sidewall of the
lateral region of the first conductive layer takes the shape of a
circular arc curve.
[0023] In the method of manufacturing the non-volatile memory, the
step of patterning the third conductive layer further includes
removing the third conductive layer by using the inter-gate
dielectric layer as a stop layer.
[0024] In the method of manufacturing the non-volatile memory, the
step of removing a portion of the inter-gate dielectric layer and
the second conductive layer further includes removing a portion of
the tunnel dielectric layer.
[0025] In the method for manufacturing the non-volatile memory, the
method of forming the tunnel dielectric layer includes thermal
oxidation.
[0026] The present invention provides another method of
manufacturing the non-volatile memory. A substrate is first
provided, wherein a plurality of isolation structures are formed on
the substrate in arrays and a mask layer is filled in the intervals
between the isolation structures. After that, a portion of the mask
layer is removed and the mask layer between two adjacent rows of
the isolation structures is left. A tunnel dielectric layer and a
first conductive layer are formed on the substrate. Afterward, the
first conductive layer on the top of the mask layer and the
isolation structures is removed and second conductive layers
located on the two sidewalls of the mask layer and between adjacent
isolation structures are formed. After that, a portion of the
isolation structures and the mask layer are removed and a source
region is formed in the substrate between the second conductive
layers. Subsequently, an inter-gate dielectric layer and a third
conductive layer are formed on the substrate. The third conductive
layer, the inter-gate dielectric layer, and the second conductive
layer are patterned. After that, a dielectric layer is formed on
the substrate and the exposed sidewalls of the third conductive
layer and the second conductive layers. A fourth conductive layer
is formed on the sidewall of the third conductive layer. Then, a
drain region is formed in the substrate outside the fourth
conductive layer.
[0027] In the method of manufacturing the non-volatile memory, the
cross-section of each of the patterned second conductive layers
presents an L-shape and the patterned second conductive layer
includes a central region which is perpendicular to the substrate
and a lateral region which is parallel to the substrate, wherein
the central region is adjacent to the source region.
[0028] In the method of manufacturing the non-volatile memory, the
method of forming the dielectric layer on the sidewall of the
lateral region of the second conductive layers includes thermal
oxidation.
[0029] In the method of manufacturing the non-volatile memory,
after the step of the thermal oxidation, the sidewall of the
lateral region takes the shape of a circular arc curve.
[0030] In the method of manufacturing the non-volatile memory,
after the step of removing a portion of the isolation structures,
the top surface of the isolation structures is at least lower than
that of the second conductive layer.
[0031] In the method of manufacturing the non-volatile memory, the
step of patterning the third conductive layer involves, for
example, forming a patterned photoresist layer on the third
conductive layer, removing a portion of the third conductive layer
by using the patterned photoresist layer as a mask, and then
removing the patterned photoresist layer.
[0032] In the method of manufacturing the non-volatile memory, the
step of patterning the third conductive layer further includes
removing a portion of the third conductive layer by using the
inter-gate dielectric layer as a stop layer.
[0033] In the method of manufacturing the non-volatile memory, the
method of patterning the second conductive layers further includes
using the patterned third conductive layer as a self-aligned
mask.
[0034] In the method of manufacturing the non-volatile memory, the
step of patterning the inter-gate dielectric layer and the second
conductive layer further includes patterning the tunnel dielectric
layer.
[0035] In the method of manufacturing the non-volatile memory, the
method of forming the tunnel dielectric layer includes thermal
oxidation.
[0036] In the method of manufacturing the non-volatile memory
provided by the present invention, the L-shaped first conductive
layer, i.e., the floating gate, is formed by means of self
alignment. Since a lithographic process is saved, the number of the
masks used in the process is reduced, thereby simplifying the
manufacturing flow and reducing the manufacturing cost. Further,
due to the design of the process, the adjacent memory cells share
one source region and one control gate to enhance the integrity of
the device.
[0037] In order to make the aforementioned and other features and
advantages of the present invention comprehensible, preferred
embodiments accompanied with figures are described in detail
below.
[0038] It is to be understood that both the foregoing general
description and the following detailed description are exemplary,
and are intended to provide further explanation of the invention as
claimed.
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] FIG. 1 is a structural sectional view of the non-volatile
memory according to one embodiment of the present invention.
[0040] FIGS. 2A-2F are top views of the manufacturing flow of the
non-volatile memory according to one embodiment of the present
invention.
[0041] FIGS. 3A-3F are schematic sectional views along line a-a' in
FIGS. 2A-2F.
[0042] FIGS. 4A-4F are schematic sectional views along line b-b' in
FIGS. 2A-2F.
DESCRIPTION OF EMBODIMENTS
[0043] FIG. 1 is a structural sectional view of the non-volatile
memory according to one embodiment of the present invention.
Referring to FIG. 1, the non-volatile memory provided by the
present invention includes, for example, a plurality of memory
cells disposed on a substrate 100. Each memory cell includes a
tunnel dielectric layer 110, a floating gate 120, an inter-gate
dielectric layer 130, a control gate 140, a dielectric layer 150, a
select gate 160, a source region 165, and a drain source 175. The
source region 165 and the drain region 175 are, for example,
disposed in the substrate 100. The source region 165 is, for
example, a doped region doped with P-type or N-type dopants and the
drain region 175 is, for example, a doped region with the same
conductive type of dopants as that of the source region 165.
[0044] The control gate 140 is, for example, disposed on the
substrate 100 between the source region 165 and the drain region
175. The control gate 140 is, for example, made of conductive
materials such as doped polysilicon, metals, or metal
silicides.
[0045] The floating gate 120 is, for example, disposed between the
control gate 140 and the substrate 100. The material of the
floating gate 120 is, for example, doped polysilicon. In one
embodiment, the cross-section of the floating gate 120 presents,
for example, an L-shape and the L-shaped floating gate 120 includes
a central region 120a which is perpendicular to the substrate 100
and the lateral region 120b which is parallel to the substrate 100,
wherein the central region 120a is adjacent to the source region
165. The sidewall of the lateral region 120b of the L-shaped
floating gate 120 takes the shape of, for example, a circular arc
curve 123, which facilitates the erasing operation of the
non-volatile memory, such that the charges in the floating gate 120
easily enter the select gate 160, thereby accelerating the
operational speed of erasing.
[0046] More specifically, since the L-shaped floating gate 120 is
disposed between the control gate 140 and the substrate 100, the
control gate 140 is not only disposed on the lateral region 120b of
the L-shaped floating gate 120, but also extends to the sidewall of
the central region 120a of the floating gate 120. Since the
floating gate 120 presents an L-shape, the capacity area between
the control gate 140 and the floating gate 120 is also enlarged. As
such, the GCR is increased correspondingly, the working voltage
required by the memory is reduced, and the operating speed of the
memory is accelerated.
[0047] The select gate 160 is, for example, disposed on the
sidewall of the control gate 140 and the floating gate 120 and
especially disposed on the sidewall of the lateral region 120b of
the L-shaped floating gate 120. The material of the select gate 160
is, for example, doped polysilicon. Of course, the select gate 160
can also be made of conductive materials such as metals and metal
silicides.
[0048] The tunnel dielectric layer 110 is, for example, disposed
between the substrate 100 and the floating gate 120, and the
material thereof is, for example, silicon oxide. The inter-gate
dielectric layer 130 is, for example, disposed between the control
gate 140 and the substrate 100, and between the control gate 140
and the floating gate 120. The material of the inter-gate
dielectric layer 130 is, for example, silicon oxide, silicon
nitride, silicon oxynitride, or a composite dielectric material
such as silicon oxide/silicon nitride and silicon oxide/silicon
nitride/silicon oxide.
[0049] The dielectric layer 150 is, for example, disposed between
the select gate 160 and the control gate 140, the select gate 160
and the floating gate 120, and the select gate 160 and the
substrate 100. The dielectric layer 150 further extends to the
control gate 140 and the substrate 100 of the drain region 175. The
material of the dielectric layer 150 is, for example, silicon
oxide.
[0050] In the non-volatile memory provided by the present
invention, for example, two memory cells having a same structure
such as memory cells MC1 and MC2 in FIG. 1 are configured
mirror-symmetrically to form one memory unit MU. The memory cells
MC1 and MC2 share one control gate 140 and one source region 165.
Due to the structure of the memory unit MU, not only is the
manufacturing flow simplified and the manufacturing cost reduced,
but the integrity of the device is also enhanced.
[0051] The method of manufacturing the aforementioned non-volatile
memory will be illustrated below. FIGS. 2A-2F are top views of the
manufacturing flow of the non-volatile memory according to one
embodiment of the present invention. FIGS. 3A-3F are schematic
sectional views along line a-a' in FIGS. 2A-2F, respectively. FIGS.
4A-4F are schematic sectional views along line b-b' in FIGS. 2A-2F,
respectively.
[0052] Referring to FIGS. 2A, 3A, and 4A, in the method, for
example, a substrate 200 is first provided; and a pad layer 201 and
a mask layer 203 are formed on the substrate 200. The substrate 200
is, for example, a silicon substrate. The material of the pad layer
201 is, for example, silicon oxide, and the forming method thereof
is, for example, thermal oxidation. The material of the mask layer
203 is, for example, silicon nitride, silicon carbide, or silicon
oxycarbide, and the forming method thereof is, for example,
chemical vapor deposition.
[0053] Subsequently, a patterned photoresist layer 204 is formed on
the mask layer 203; the exposed mask layer 203, the pad layer 201,
and the substrate 200 are removed by using the patterned
photoresist layer 204 as a mask to form a trench 205. The method of
forming the patterned photoresist layer 204 involves, for example,
forming a positive photoresist layer by means of spin coating, and
the pattern is developed after exposing, thus forming the patterned
photoresist layer 204. The method of removing portions of the mask
layer 203, the pad layer 201, and the substrate 200 is, for
example, reactive-ion etching.
[0054] Then, referring to FIGS. 2B, 3B, and 4B, the insulating
material is filled in the trench 205 to form an isolation structure
207. The method of forming the isolation structure 207 involves,
for example, forming an insulating material layer such as silicon
oxide. The forming method thereof is, for example, high-density
plasma chemical vapor deposition. Of course, the insulating
material just deposited will cover the mask layer 203, so the mask
layer 203 is needed to serve as a stop layer. The insulating
material is planarized to form the isolation structure 207 with a
flat top surface. The planarization method the insulating material
is, for example, chemical mechanical polishing.
[0055] After that, referring to FIGS. 2B, 3B, and 4B, by using
another patterned photoresist layer 208, a portion of the mask
layer 203 and the pad layer 201 are removed to separate the mask
layer 203 and the pad layer 201 into strips. The patterned
photoresist layer 208, for example, covers the mask layer 203
between two adjacent rows of the isolation structures 207. After
that, by using the patterned photoresist layer 208 as a mask, the
exposed mask layer 203 and the pad layer 201 thereunder are
removed.
[0056] Then, referring to FIGS. 2C, 3C, and 4C, a tunnel dielectric
layer 210 is formed on the substrate 200 after removing portions of
the mask layer 203 and the pad layer 201. The material of the
tunnel dielectric layer 210 is, for example, silicon oxide. The
forming method thereof is, for example, thermal oxidation or
chemical vapor deposition. Then, a thin conductive layer 215 is
formed on the substrate 200. The material of the conductive layer
205 is, for example, doped polysilicon, and the forming method
thereof involves forming a layer of undoped polysilicon by chemical
vapor deposition, and then performing a process of
ion-implantation, or adopting an in-situ implanting operation in a
chemical vapor deposition process.
[0057] After that, referring to FIGS. 2D, 3D, and 4D, the
conductive layer 215 on the top of the mask layer 203 and the
isolation structure 207 is removed. The method of removing a
portion of the conductive layer 215 is, for example, chemical
mechanical polishing using the mask layer 203 and the isolation
structure 207 as the stop layer.
[0058] Subsequently, a portion of the isolation structure 207 is
removed, such that the top surface of the isolation structure 207
is lower than that of the conductive layer 215. The method of
removing a portion of the isolation structure 207 is, for example,
dry etching or wet etching. In one embodiment, the top surface of
the isolation structure 207 is, for example, a little higher than
that of the tunnel dielectric layer 210.
[0059] Then, the mask layer 203 is removed. The method of removing
the mask layer 203 is, for example, dry etching or wet etching.
Subsequently, an ion-implantation process is performed by using the
conductive layer 215 as the mask to form the source region 220 in
the substrate 200 among the conductive layer 215. The pad layer 201
is removed together with the mask layer 203, or it can be left.
[0060] Then, an inter-gate dielectric layer 230 is formed on the
substrate 200. The inter-gate electric layer 230 is, for example, a
silicon oxide layer, a silicon nitride layer, a silicon oxynitride
layer, or a composite dielectric layer such as a silicon
oxide/silicon nitride layer or a silicon oxide/silicon
nitride/silicon oxide layer. The method of forming the inter-gate
dielectric layer 230 is, for example, thermal oxidation, or
chemical vapor deposition by using different reaction gases
depending on the material of the film layer.
[0061] Afterward, referring to FIGS. 2E, 3E, and 4E, a conductive
layer 240 is formed on the inter-gate dielectric layer 230. The
material of the conductive layer 240 is, for example, doped
polysilicon. The forming method thereof involves, for example,
forming an undoped polysilicon layer by chemical vapor deposition
and then performing an ion-implantation process, or adopting an
in-situ implantation in a chemical vapor deposition process. Then,
the conductive layer 240 is patterned. The method of patterning the
conductive layer 240 involves, for example, forming a patterned
photoresist layer (not shown) on the conductive layer 240. After
that, a portion of the conductive layer 240 is removed by using the
patterned photoresist layer as the mask, and then the patterned
photoresist layer is further removed. A portion of the conductive
layer 240 is, for example, removed by dry etching using the
inter-gate dielectric layer 230 as the stop layer. The patterned
conductive layer 240 is the control gate of the non-volatile
memory. At this point, the conductive layer 240, i.e., the control
gate, for example, covers the source region 210 and a portion of
the conductive layer 215 on both sides of the source region
210.
[0062] After that, a dielectric layer 245 is formed on the exposed
sidewall (including the top surface of the conductive layer 240) of
the conductive layer 240 by thermal oxidation process. Then, a
portion of inter-gate dielectric layer 230 and the conductive layer
215 are removed by using the conductive layer 240 as the
self-aligned mask. The cross-section of the patterned conductive
layer 215 is L-shaped, and includes a central region 215a which is
perpendicular to the substrate 200 and the lateral region 215b
which is parallel to the substrate 200, wherein the central region
215a is adjacent to the source region 220. Herein, the formed
conductive layer 215 with the L-shaped cross-section is the
floating gate. The method of removing a portion of the inter-gate
dielectric layer 230 and the conductive layer 215 is, for example,
wet etching or dry etching. The tunnel dielectric layer 210
thereunder is removed together with the inter-gate dielectric layer
230 and the conductive layer 215, or it can be removed by wet
etching later.
[0063] Then, referring to FIGS. 2F, 3F, and 4F, another dielectric
layer 247a is formed on the sidewall, i.e., the sidewall of the
lateral region 215b of the conductive layer 215, exposed by the
conductive layer 215 by the thermal oxidation. After the thermal
oxidation, the sidewall of the lateral region 215b of the
conductive layer 215 takes the shape of a circular arc curve 249.
When the thermal oxidation is performed, a dielectric layer 247b is
also formed on the exposed substrate 200.
[0064] Subsequently, the conductive layer 250 is formed on the
substrate 200 on both sides of the conductive layer 240. The
conductive layer 250 serves as the select gate of the non-volatile
memory. The method of forming the conductive layer 250 involves,
for example, forming a conductive material layer (not shown) on the
substrate 200. Then, an anisotropic etching process is performed to
remove a portion of the conductive material layer, so as to form a
conductive layer 250 on the substrate 200 on the sidewall of the
conductive layer 240. The material of the conductive layer 250 is,
for example, doped polysilicon. For example, the conductive layer
250 is formed by means of the ion-implantation after an undoped
polysilicon layer is formed by the chemical vapor deposition or by
an in-situ implantation in a chemical vapor deposition process. The
conductive layer 250 serves as the select gate of the non-volatile
memory.
[0065] Then, a dopant implantation process is performed by using
the conductive layer 250 as the mask to form a drain region 260 in
the substrate 200 outside the conductive layer 250. The drain
region 260, for example, has the dopants with a same conductivity
as that of the source region 220. The subsequent process of forming
the non-volatile memory, for example, forming a bit line (not
shown) for electrically connected to the drain region 260 or the
processes of forming a protection layer and interconnects, are well
known to those skilled in the art and will not be further described
herein details.
[0066] In the method of manufacturing the non-volatile memory, the
mask layer 203 and the isolation structure 207 are used as the stop
layer. A portion of the conductive layer 215 is first removed.
Further, the conductive layer 240 is used as the self-aligned mask
to pattern the conductive layer 215, thereby forming the L-shaped
conductive layer 215 as the floating gate of the memory, as shown
in FIG. 3D.
[0067] Since the floating gate, i.e., the conductive layer 215,
presents an L-shape, the equivalent capacity area between the
floating gate and the control gate, i.e., the conductive layer 240
is enlarged, such that the GCR between the control gate and the
floating gate is enhanced, further reducing the working voltage of
the memory and accelerating the operational speed of the
memory.
[0068] Besides, in the process of manufacturing the L-shaped
floating gate, a lithographic process is saved, such that the
number of the masks is reduced and the manufacturing flow is
simplified. Due to the design of the process, two adjacent memory
cells share one source region and one control gate, which helps to
enhance the integrity of the device.
[0069] Furthermore, a dielectric layer 247 is formed by the thermal
oxidation, and a circular arc curve 249 is formed on the sidewall
of the conductive layer 215. The circular arc curve 249 helps the
erasing operation of the non-volatile memory, thus making the
charges in the conductor 215 (the floating gate), easily enter into
the conductive layer 250 (the select gate), and accelerate the
operational speed of erasing.
[0070] It will be apparent to those skilled in the art that various
modifications and variations can be made to the structure of the
present invention without departing from the scope or spirit of the
invention. In view of the foregoing, it is intended that the
present invention cover modifications and variations of this
invention provided they fall within the scope of the following
claims and their equivalents.
* * * * *