U.S. patent application number 12/093496 was filed with the patent office on 2009-01-01 for mount board and electronic device.
This patent application is currently assigned to NEC CORPORATION. Invention is credited to Katsumi Abe, Kenichiro Fujii, Nobuhiro Mikami, Junya Sato, Atsumasa Sawada, Shinji Watanabe.
Application Number | 20090002973 12/093496 |
Document ID | / |
Family ID | 38048483 |
Filed Date | 2009-01-01 |
United States Patent
Application |
20090002973 |
Kind Code |
A1 |
Watanabe; Shinji ; et
al. |
January 1, 2009 |
Mount Board and Electronic Device
Abstract
An object of the present invention is to allow stress that may
be applied to a semiconductor package to be suppressed, when the
semiconductor package is mounted on a curved board. In a mount
board 1, a semiconductor package 20 is mounted on a curved board 10
including a curved surface on at least a portion thereof. The
curved board 10 includes a pedestal portion 13a disposed on a
region of the curved surface portion where the semiconductor
package 20 is mounted and having an upper surface thereof formed
flat, and a plurality of pad portions 15a disposed on the flat
surface of the pedestal portion 13a. The pedestal portion 13a is
formed of an insulating material. The semiconductor package 20 is
mounted on the pad portions 15a.
Inventors: |
Watanabe; Shinji; (Tokyo,
JP) ; Mikami; Nobuhiro; (Tokyo, JP) ; Sato;
Junya; (Tokyo, JP) ; Fujii; Kenichiro; (Tokyo,
JP) ; Abe; Katsumi; (Tokyo, JP) ; Sawada;
Atsumasa; (Tokyo, JP) |
Correspondence
Address: |
SUGHRUE MION, PLLC
2100 PENNSYLVANIA AVENUE, N.W., SUITE 800
WASHINGTON
DC
20037
US
|
Assignee: |
NEC CORPORATION
Tokyo
JP
|
Family ID: |
38048483 |
Appl. No.: |
12/093496 |
Filed: |
November 8, 2006 |
PCT Filed: |
November 8, 2006 |
PCT NO: |
PCT/JP2006/322251 |
371 Date: |
May 13, 2008 |
Current U.S.
Class: |
361/820 |
Current CPC
Class: |
H01L 2224/76155
20130101; H01L 2924/014 20130101; H05K 1/185 20130101; H05K 3/0014
20130101; H05K 2203/302 20130101; H05K 2201/0195 20130101; H01L
2924/01005 20130101; H05K 1/189 20130101; H01L 2224/18 20130101;
H01L 2924/12042 20130101; H01L 2924/01006 20130101; H05K 3/4644
20130101; H01L 24/16 20130101; H01L 2224/24226 20130101; H05K
1/0284 20130101; H05K 2201/10734 20130101; H01L 2224/24051
20130101; H05K 2201/0191 20130101; H01L 2924/01019 20130101; H05K
2203/1469 20130101; H01L 2224/16227 20130101; H01L 24/82 20130101;
H05K 2201/10477 20130101; H01L 2224/24998 20130101; H05K 2201/09118
20130101; H01L 2924/01078 20130101; H05K 2201/09018 20130101; H05K
2201/09036 20130101; H05K 2201/10515 20130101; H05K 2201/10636
20130101; H01L 2224/73267 20130101; H01L 2924/01033 20130101; H05K
2201/09436 20130101; H01L 2924/19105 20130101; H01L 2924/3511
20130101; H01L 2224/32225 20130101; H05K 3/32 20130101; H01L 24/24
20130101; H01L 2924/19104 20130101; H01L 2924/01004 20130101; H01L
2924/1515 20130101; H01L 2924/19041 20130101; H01L 24/18 20130101;
H01L 2924/01082 20130101; H01L 2924/19043 20130101; H05K 1/0271
20130101; Y02P 70/50 20151101; H01L 2224/82102 20130101; H01L
2924/3011 20130101; H05K 1/18 20130101; H01L 2924/01029 20130101;
H05K 2201/1053 20130101; H01L 2224/16225 20130101; H01L 2924/15151
20130101; H01L 2924/19103 20130101; H05K 1/023 20130101; H05K
2201/0187 20130101; H05K 2201/09045 20130101; H01L 2924/12042
20130101; H01L 2924/00 20130101 |
Class at
Publication: |
361/820 |
International
Class: |
H05K 7/00 20060101
H05K007/00 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 18, 2005 |
JP |
2005-334649 |
Claims
1. A mount board with a semiconductor package mounted on a curved
board thereof, said curved board including a curved surface on at
least a portion thereof; wherein said curved board comprises: a
pedestal portion disposed on a region of said curved-surface
portion where said semiconductor package is mounted and having an
upper surface thereof formed flat, said upper surface being formed
of an insulating material; and a plurality of pad portions disposed
on said flat surface of said pedestal portion; said semiconductor
package being mounted on said pad portions.
2. The mount board according to claim 1, wherein said pedestal
portion is formed by molding an insulating layer used on said
curved board.
3. The mount board according to claim 1, wherein said insulating
layer includes shoulder portions on regions thereof adjacent to
said pedestal portion, each of said shoulder portions having a flat
surface; and said flat surface of said each of said shoulder
portions is formed to be parallel to a tangent to said
curved-surface portion.
4. The mount board according to claim 3, comprising: a plurality of
second pad portions disposed on said flat surface of said pedestal
portion; and electronic component(s) that is (are) mounted on said
second pad portions.
5. The mounding board according to claim 1, wherein said pedestal
portion has a concave part in a region thereof between the pad
portions adjacent to each other.
6. The mount board according to claim 1, wherein said pedestal
portion is formed by including a second insulating layer
therein.
7. The mount board according to claim 6, wherein said second
insulating layer is formed of any one of a laminate, a
thermoplastic resin, a hybrid-type resin, and an inorganic
material, said laminate being formed by laminating film-like
resins, said hybrid-type resin including a thermoplastic resin and
a thermosetting resin.
8. The mount board according to claim 1, wherein said pedestal
portion is formed by molding an insulating material other than an
insulating material of an insulating layer used on said curved
board.
9. The mount board according to claim 8, wherein said pedestal
portion is formed of a filler-containing resin material.
10. The mount board according to claim 8, wherein an electronic
component(s) is (are) mounted inside said pedestal portion.
11. A mount board with a semiconductor package mounted on a curved
board thereof, said curved board including a curved surface on at
least a portion thereof, said curved board comprising: a pedestal
portion disposed on a region of said curved-surface portion where
said semiconductor package is mounted, said pedestal portion being
formed of an insulating material; said pedestal portion being
formed by molding an insulating material other than an insulating
material of an insulating layer used for said curved board; said
semiconductor package being disposed inside said pedestal portion;
external terminals of said semiconductor package being disposed on
an opposite side of said surface of said board and being exposed
from said pedestal portion; said mount board comprising: a wiring
pattern disposed on at least said pedestal portion and said
semiconductor package, said wiring pattern electrically connecting
a wiring layer of said curved board and said external terminals of
said semiconductor package.
12. The mount board according to claim 11, comprising: an
electronic component(s) mounted over said external terminals of
said semiconductor package via pad portions of said wiring
pattern.
13. A curved board including a curved surface on at least a portion
thereof, comprising: a pedestal portion disposed on a region of
said curved-surface portion where a semiconductor package is
mounted and having an upper surface thereof formed flat, said
pedestal portion being formed of an insulating material; and a
plurality of pad portions disposed on said flat surface of said
pedestal portion.
14. The curved board according to claim 13, wherein said pedestal
portion is formed by molding an insulating layer used on said
curved board.
15. The curved board according to claim 13, wherein said insulating
layer includes shoulder portions on regions thereof adjacent to
said pedestal portion, each of said shoulder portions having a flat
surface; and said flat surface of said each of said shoulder
portions is formed to be parallel to a tangent to said
curved-surface portion.
16. The curved board according to claim 15, comprising: a plurality
of second pad portions disposed on said flat surface of said
pedestal portion; and an electronic component(s) that is (are)
mounted on said second pad portions.
17. The curved board according to claim 13, wherein said pedestal
portion has a concave part in a region thereof between the pad
portions adjacent to each other.
18. The curved board according to claim 13, wherein said pedestal
portion is formed by including a second insulating layer
therein.
19. The curved board according to claim 18, wherein said second
insulating layer is formed of one of a laminate, a thermoplastic
resin, a hybrid-type resin, and an inorganic material, said
laminate being formed by laminating film-like resins, said
hybrid-type resin including a thermoplastic resin and a
thermosetting resin.
20. An electronic device comprising: the mount board according to
claim 1.
21. An electronic device comprising: the curved board including
claim 13.
Description
TECHNICAL FIELD
[0001] The present invention relates to a mount board and an
electronic device with electronic components mounted on a circuit
board thereof. More specifically, the invention relates to a mount
board and an electronic device with a curved circuit board.
BACKGROUND ART
[0002] Recently, portable devices represented by cellular phones
have been thriving. Design of a portable device as well as higher
functionality and higher performance of the portable device has
been regarded as important. Then, in order to improve usability and
appearance, a curved surface is being in heavy usage for the shape
of a case of the portable device.
[0003] In a conventional mount board mounted within the case of the
portable device, however, electronic components such as a
semiconductor package are mounted on a flat board. Thus, it is
difficult to efficiently arrange the electronic components within
the case formed of various curved surfaces. For this reason, when
the design is given priority, there is a problem that the size of
the device may increase. Accordingly, it frequently happens that a
design compromise must be inevitably made. Thus, it is strongly
desired to put into practical use a board having a curved surface
in conformity with the curved surface of the case, which is
excellent in component arrangement efficiency within the case.
[0004] On the other hand, as a semiconductor package suited to the
portable device, for which size reduction is required, a
semiconductor package (a semiconductor device) as shown in FIG. 17
may be pointed out. In this semiconductor package, solder balls are
arranged on a bottom surface of the package in a lattice form as
connecting terminals. Such a package is described in Patent
Document 1 and is referred to as a BGA (Ball Grid Array), a CSP
(Chip Size Package), or a WL-CSP (Wafer Level Chip Size Package).
Such a package is extensively used because more terminals can be
arranged on this package with a smaller occupied area.
[0005] As a method of mounting this semiconductor package on the
board, there is adopted the method of printing a cream solder on
pads of the board using a metal mask, and melting the solder by
reflowing after the semiconductor package has been mounted, thereby
obtaining mechanical and electrical connection.
[0006] [Patent Document 1]
[0007] JP Patent No. P3395164 (FIG. 1)
[0008] [Patent Document 2]
[0009] JP Patent Kokai Publication No. JP-P2003-318218A (FIG.
2)
DISCLOSURE OF THE INVENTION
Problems to be Solved by the Invention
[0010] However, when the semiconductor package premised on being
placed on the flat board is mounted on a board formed of a curved
surface, there is a problem that a solder connection failure may
occur according to the size of the semiconductor package or a
curvature of a curved surface of a circuit board.
[0011] When mounting onto a board 203 having a convex curved
surface as shown in FIG. 18 is performed, for example, a distance
between a solder ball 202 and a pad 204 of the board 203 increases
at an outer peripheral portion of a semiconductor package 201.
Further, when mounting onto a concave curved surface as shown in
FIG. 19 is performed, a distance between a solder ball 202 and a
board 203 increases at the central portion of a semiconductor
package 201. With respect to the boards 203 each having a curvature
in some direction as shown in FIGS. 18 and 19 as well, the larger
the curvature of the board 203 is and the larger the size of the
semiconductor package 201 is, there tends to be a terminal at which
the solder ball 202 doest not come into the pad 204 of the board
203. The solder connection failure is thereby brought about.
[0012] When the conventional semiconductor package is mounted on
the curved board as described above, the solder connection failure
caused by noncontact between a solder ball of the semiconductor
package and a pad of the board may occur. Accordingly, the
semiconductor package cannot be mounted on the board formed of the
curved surface.
[0013] Then, as means for solving the problem of the connection
failure that may occur when the semiconductor package as described
in Patent Document 1 is mounted, Patent Document 2 proposes a
method of curving a chip in accordance with the curvature of a
board and then joining the chip to the curved surface of the board
with the chip caused to follow the curved surface, thereby
preventing occurrence of the connection failure (refer to FIG.
20).
[0014] However, when the chip is curved as described above, a warp
may occur on the circuit surface of the chip. Then, a problem
arises that a minute circuit formed on the surface of the chip may
be thereby broken or electrical characteristics of the minute
circuit may change. Electrical characteristics of an analog circuit
in particular greatly change even by a minute warp, and this change
in the electrical characteristics affects overall system
performance. Thus, it is strongly desired to minimize stress that
may be applied to the circuit surface of the chip.
[0015] Further, in recent years, a fragile insulating film (such as
a low-k film) targeted for a faster operation has been adopted.
Then, even in common flat-surface packages, a study of a
lower-stress sealant, a lower-stress structure, or the like is
made. To find out a way to achieve stress reduction is therefore an
important challenge. In a step of mounting a semiconductor package
as well, for example, it is necessary to find a way of restraining
a warp of the semiconductor package during reflow heating when the
semiconductor package is mounted on a board and minimizing stress
that may be applied to a chip within the semiconductor package
after the mounting.
[0016] As described above, there is a problem that the method of
curving the chip, proposed in Patent Document 2 cannot be applied
to the analog circuit of which electrical characteristics may
greatly change and for which restraint of stress to be applied to a
chip is therefore required, the semiconductor package formed of the
fragile insulating film targeted for the faster operation, or the
semiconductor chip.
[0017] A main challenge of the present invention is to allow stress
that may be applied to a semiconductor package to be suppressed,
when the semiconductor package is mounted on a curved board.
Means to Solve the Problems
[0018] A mount board according to a first aspect of the present
invention is the mount board with a semiconductor package mounted
on a curved board thereof, the curved board including a curved
surface on at least a portion thereof. The curved board
includes:
[0019] a pedestal portion disposed on a region of the
curved-surface portion where the semiconductor package is mounted
and having an upper surface thereof formed flat, the upper surface
being formed of an insulating material; and
[0020] a plurality of pad portions disposed on the flat surface of
the pedestal portion. The semiconductor package is mounted on the
pad portions.
[0021] A mount board according to a second aspect of the present
invention is the mount board with a semiconductor package mounted
on a curved board thereof, the curved board including a curved
surface on at least a portion thereof. The curved board
includes:
[0022] a pedestal portion disposed on a region of the
curved-surface portion where the semiconductor package is mounted,
the pedestal portion being formed of an insulating material;
[0023] the pedestal portion being formed by molding an insulating
material other than an insulating material of an insulating layer
used on the curved board;
[0024] the semiconductor package being disposed inside the pedestal
portion;
[0025] external terminals of the semiconductor package being
disposed on an opposite side of the surface of the board and being
exposed from the pedestal portion;
[0026] the mount board comprising:
[0027] a wiring pattern disposed on at least the pedestal portion
and the semiconductor package, the wiring pattern electrically
connecting a wiring layer of the curved board and the external
terminals of the semiconductor package.
[0028] A curved board according to a third aspect of the present
invention is the curved board including a curved surface on at
least a portion thereof. The curved board includes:
[0029] a pedestal portion disposed on a region of the
curved-surface portion where a semiconductor package is mounted and
having an upper surface thereof formed flat, the pedestal portion
being formed of an insulating material; and
[0030] a plurality of pad portions disposed on the flat surface of
the pedestal portion.
[0031] An electronic device according to a fourth aspect of the
present invention is configured by including the mount board or the
curved board.
EFFECT OF THE INVENTION
[0032] According to the present invention (claimed in claims 1
thorough 21), the curved board having a locally flat portion is
formed. On the locally flat portion, the pad portions on the board
to be connected to the semiconductor package are formed to be
flat.
[0033] Accordingly, when the semiconductor package is mounted on
the curved board, the semiconductor package can be mounted on pads
arranged to be flat, as in the case where the semiconductor package
is mounted on a common flat board. For this reason, a solder
connection failure that may arise when a conventional common
semiconductor package represented by a BGA is mounted on a curved
board as shown in FIG. 18 or 19 can be suppressed. Further, it is
not necessary to curve a semiconductor chip and mount the curved
semiconductor chip, either. Mounting of the semiconductor package
on the curved board can be realized in which no stress to the
semiconductor chip included in the semiconductor chip will
arise.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] FIG. 1 is a sectional view schematically showing a
configuration of a mount board according to a first exemplary
embodiment of the present invention;
[0035] FIG. 2 is a sectional view schematically showing a
configuration of a curved board of the mount board according to the
first exemplary embodiment of the present invention;
[0036] FIGS. 3A, 3B and 3C are respectively a top plan view, a
sectional view taken along a line X-X', and a sectional view taken
along a line Y-Y', which schematically show a first curved-surface
shape of a base member of the mount board according to the first
exemplary embodiment of the present invention;
[0037] FIGS. 4A, 4B and 4C are respectively a top plan view, a
sectional view taken along a line X-X', and a sectional view taken
along a line Y-Y', which schematically show a second curved-surface
shape of the base member of the mount board according to the first
exemplary embodiment of the present invention;
[0038] FIGS. 5A to 5E include step sectional views schematically
showing a first manufacturing method of the mount board according
to the first exemplary embodiment of the present invention;
[0039] FIGS. 6A to 6F include step sectional views schematically
showing a second manufacturing method of the mount board according
to the first exemplary embodiment of the present invention;
[0040] FIG. 7 is a sectional view schematically showing a
configuration of a mount board according to a second exemplary
embodiment of the present invention;
[0041] FIGS. 8A to 8E include step sectional views schematically
showing a manufacturing method of the mount board according to the
second exemplary embodiment of the present invention;
[0042] FIG. 9 is a sectional view schematically showing a
configuration of a mount board according to a third exemplary
embodiment of the present invention;
[0043] FIGS. 10A to 10E include step sectional views schematically
showing a manufacturing method of the mount board according to the
third exemplary embodiment of the present invention;
[0044] FIG. 11 is a sectional view schematically showing a
configuration of a mount board according to a fourth exemplary
embodiment of the present invention;
[0045] FIGS. 12A to 12F include step sectional views schematically
showing a manufacturing method of the mount board according to the
fourth exemplary embodiment of the present invention;
[0046] FIGS. 13A and 13B are sectional views each schematically
showing a configuration of a mount board according to a fifth
embodiment of the present invention, FIG. 13A relates to the mount
board with a semiconductor package mounted on a convex surface side
thereof, and FIG. 13B relates to the mount board with the
semiconductor package mounted on a concave surface side
thereof;
[0047] FIGS. 14A and 14B are sectional views each schematically
showing a configuration of a mount board according to a sixth
embodiment of the present invention, FIG. 14A relates to the mount
board with the semiconductor package mounted on a convex surface
side thereof, and FIG. 14B relates to the mount board with the
semiconductor package mounted on a concave surface side
thereof;
[0048] FIGS. 15A and 15B are sectional views each schematically
showing a configuration of a mount board according to a seventh
embodiment of the present invention, FIG. 15A relates to the mount
board with a semiconductor package mounted on a convex surface side
thereof, and FIG. 15B relates to the mount board with the
semiconductor package mounted on a concave surface side
thereof;
[0049] FIGS. 16A and 16B are sectional views each schematically
showing a configuration of a mount board according to an eighth
embodiment of the present invention, FIG. 16A relates to the mount
board with the semiconductor package mounted on a convex surface
side thereof, and FIG. 16B relates to the mount board with the
semiconductor package mounted on a concave surface side
thereof;
[0050] FIG. 17 is a sectional view schematically showing a
configuration of a semiconductor package according to a first
conventional art;
[0051] FIG. 18 is a sectional view of a mount board according to a
second conventional art when a semiconductor package is mounted on
a convex surface side of a curved board;
[0052] FIG. 19 is a sectional view of a mount board according to a
third conventional art when a semiconductor package is mounted on a
concave surface side of a curved board; and
[0053] FIGS. 20A to 20G include step sectional views schematically
showing a method of manufacturing a semiconductor package according
to a fourth conventional art.
EXPLANATIONS OF SYMBOLS
[0054] 1 mount board [0055] 10 curved board (circuit board) [0056]
11 base member (substrate) [0057] 12 wiring layer [0058] 13
insulating layer [0059] 13a pedestal portion [0060] 13b shoulder
portion [0061] 13c concave portion [0062] 14 via [0063] 15 wiring
layer [0064] 15a, 15b pad portion [0065] 16 second insulating layer
[0066] 20 semiconductor package [0067] 21 external terminal [0068]
30 solder ball [0069] 40, 41, 42, 43, 44 press mold [0070] 50
electronic component [0071] 60 curved board [0072] 61 circuit board
[0073] 61a insulating layer [0074] 61b wiring layer [0075] 61c via
[0076] 61d wiring layer [0077] 62 pedestal portion [0078] 63 wiring
layer (wiring pattern) [0079] 63a pad portion [0080] 110
semiconductor device [0081] 112 board [0082] 114 semiconductor chip
[0083] 116 bump [0084] 118 structure [0085] 120 adhesive [0086] 122
underfill [0087] 124 ball bump [0088] 126 depressed portion [0089]
128 gap [0090] 201 semiconductor package [0091] 202 solder ball
[0092] 203 board [0093] 204 pad [0094] 301 curved board [0095] 302
chip [0096] 302a electrode [0097] 303 solder bump [0098] 303a chip
bump [0099] 303b board bump [0100] 304 underfill resin [0101] 305
heating/cooling head [0102] 306 adsorption hole
PREFERRED MODES FOR CARRYING OUT THE INVENTION
First Exemplary Embodiment
[0103] A mount board according to a first exemplary embodiment of
the present invention will be described using drawings. FIG. 1 is a
sectional view schematically showing a configuration of the mount
board according to the first exemplary embodiment of the present
invention. FIG. 2 is a sectional view schematically showing a
configuration of a curved board in the mount board according to the
first exemplary embodiment of the present invention. FIGS. 3A, 3B,
and 3C are respectively a top plan view, a sectional view taken
along a line X-X', and a sectional view taken along a line Y-Y',
which schematically show a first curved surface shape of a base
member in the mount board according to the first exemplary
embodiment of the present invention. FIGS. 4A, 4B, and 4C are
respectively a top plan view, a sectional view taken along a line
X-X', and a sectional view taken along a line Y-Y', which
schematically show a second curved surface shape of the base member
in the mount board according to the first embodiment of the present
invention.
[0104] Referring to FIG. 1, a mount board 1 is formed by mounting
an electronic component such as a semiconductor package 20 on a
curved board 10.
[0105] The curved board 10 is a circuit board having a curved
surface on at least a portion thereof. The curved board 10 includes
a base member 11, a wiring layer 12, an insulating layer 13, vias
14, and a wiring layer 15.
[0106] The base member 11 is the one having a curved surface made
of an insulating material. The base member 11 can be broadly
classified into the base member having the curved surface that is
curved in only one direction (curved only in an X-X' direction in
the case of FIG. 3) as shown in FIG. 3 and the base member having
the curved surface that is curved in two directions (curved in both
of the X-X' direction and a Y-Y' direction in the case of FIG. 4)
as shown in FIG. 4. Then, each curved surface may be the one having
a free curved surface formed of a free-form curve as well as the
one having a fixed curvature. The base member may partly or wholly
have any one of these curved surfaces. A commonly available glass
epoxy resin formed by impregnating a glass cloth with a resin may
be employed for the base member 11. The material of the base member
11 is not limited to the glass epoxy resin, and an aramid nonwoven
cloth may be employed instead of the glass cloth. Further, the base
member 11 may be formed of a material having good curved-surface
processability. A thermoplastic resin which is readily softened and
deformed and of which a shape is easy to secure may be employed. To
take an example, the resin, such as a liquid crystal polymer, may
be employed.
[0107] The wiring layer 12 is a conductive layer formed on the base
member 11. Like a common by available wiring material, a
low-resistance material of copper with a small electrical
resistance may be employed for the wiring layer 12.
[0108] The insulating layer 13 is the insulating layer formed over
the wiring layer 12 and the base member 11. The insulating layer 13
has via holes that lead to the wiring layer 12 in predetermined
locations thereof. The insulating layer 13 has a pedestal portion
13a with a flat upper surface, on a region of a curved-surface
portion where the semiconductor package 20 is mounted. For the
insulating layer 13, a semi-cured sheet-like prepreg commonly used
for a build-up substrate may be employed, and as the material of
the insulating layer 13, the common glass epoxy resin may be
employed, as in the base member 11. The material of the insulating
layer 13 is not limited to the glass epoxy resin, and the aramid
unwoven cloth may be used instead of the glass cloth. The pedestal
portion 13a is formed by molding the insulating layer 13. The
pedestal portion 13a having a thinner thickness is desired in view
of high-density mounting and a via formation property. In a
location where a via is formed in particular, it is desirable that
the thickness of the pedestal portion 13a be 150 .mu.m or less, in
view of the via formation property. When a distance between the
lower wiring layer 12 and the upper wiring layer 15 is reduced,
electrical characteristics such as an insulating property and an
impedance characteristic may deteriorate. Thus, in terms of the
electrical characteristics such as the insulating property and the
impedance characteristic, it is desirable that the thickness of the
pedestal portion 13a even in a thinnest region of the pedestal
portion 13a be 15 .mu.m or more. When a terminal pitch of the
semiconductor package 20 to be mounted is narrow and a solder short
is feared, a solder resist may be formed on a surface (an exposed
surface) of the insulating layer 13.
[0109] The vias 14 are conductive portions that electrically
connect the wiring layer 12 and the wiring layer 15. For the vias
14, a low-resistance material such as copper may be employed.
[0110] The wiring layer 15 is a conductive layer formed on the
insulating layer 13. The wiring layer 15 includes pad portions 15a
on predetermined locations of the flat surface of the pedestal
portion 13a. The pad portions 15a are electrically connected to
corresponding external terminals (not shown) of the semiconductor
package 20 via solder balls 30. For the wiring layer 15, a
low-resistance material such as copper may be employed. When taking
into consideration stress that may be applied to the wiring layer
15 at a time of causing the wiring layer 15 to follow a curved
surface or a concavo-convex shape of the insulting layer 13
including the pedestal portion 13a, a highly crack-resistant wiring
material such as electrolytic copper, formed by an electrolytic
plating method is preferable. The wiring layer 15 may be integrally
formed with the vias 14, or may be formed separately from the vias
14a.
[0111] Herein, the common by available semiconductor package 20
with the solder balls 30 arranged in a lattice form is used as an
example. The semiconductor package 20 is not limited to the one
packaged by mold sealing or the like. The present invention can be
applied to any electronic component that has been hitherto mounted
on a conventional common by available flat board, such as a
semiconductor chip that is not packaged, or a QFP (Quad Flat
Package) including gull wing leads as external terminals.
[0112] Next, a first manufacturing method of the mount board
according to the first exemplary embodiment will be described using
drawings. FIGS. 5A to 5E include step sectional views schematically
showing the first manufacturing method of the mount board according
to the first exemplary embodiment of the present invention.
[0113] First, the wiring layer 12 is formed on the circuit board 11
(refer to FIG. 5A). Herein, the wiring layer 12 can be patterned by
a subtractive method, an additive method, or a semi-additive
method. In the subtractive method, a wiring pattern is formed by
etching a surplus portion of copper foil or copper plating formed
on the circuit board 11. In the additive or semi-additive method,
the wiring layer 12 is formed by plating, after a portion except a
wiring formation region has been masked by an insulating resin.
[0114] Next, the sheet-like insulating layer 13 is formed over the
board 11 and the wiring layer 12 (refer to FIG. 5B).
[0115] Next, molding of the pedestal portion 13a of the insulating
layer 13 and molding of the curved surface of the board are
simultaneously performed by press processing (refer to FIG. 5C).
When the moldings and curing are performed in this step, the
insulating layer 13 is heated and pressurized by press molds 40
each processed into a desired shape. The insulating layer 13 is
thereby softened and flows inside the press molds 40. Then, the
insulating layer 13 is cured into the shape defined by the press
molds after having being filled into the shape defined by the press
molds. By this heating and pressurization, the base member 11 is
also softened and deformed. The curved surface of a desired shape
can be thereby obtained. At the same time, the insulating layer 13
is cured, and the pedestal portion 13a that has the locally flat
surface is thereby formed. A heating temperature in this case needs
to be not less than a temperature at which the insulating layer 13
can be cured. Herein, a temperature of 120.degree. C. or higher,
which is a requirement for the prepreg to be cured, is applied.
However, an optimum temperature differs depending on the material
of the prepreg. Thus, the heating temperature is conditioned to
accommodate the material of the prepreg. Further, in terms of a
molding property in the mold, or in order for the resin material in
the prepreg to flow and be uniformly filled into the mold, it is
preferable that a high fluidity material be selected as the resin
material of the prepreg.
[0116] Next, the via holes are formed in the insulating layer 13,
and then, the vias 14 and the wiring layer 15 are formed (refer to
FIG. 5D). Herein, the via holes are formed by opening the cured
insulating layer 13 by a laser or an etching method until the
insulating layer 12 appears. The thicker the insulating layer 13
is, the more processability of the via holes is reduced.
Accordingly, it is desirable that the insulating layer 13 be formed
to be thin within a range that electrical characteristics thereof
are not affected. Formation of the vias 14 and the wiring layer 15
is performed for an upper portion of the insulating layer 13 by
patterning using the additive method or semi-additive method. When
the vias 14 and the wiring layer 15 are formed, copper plating is
used, and the plating is filled into the via holes. Electrical
connection between the wiring layer 12 and the wiring layer 15 is
thereby obtained. On this occasion, it is desirable that the
surface of the insulating layer 13 be roughened by a desmear
process or the like in order to improve an adhesion force between
the wiring layers 15 and 13. Further, it is desirable that the
surface of a location of the wiring layer 12 to which the plating
will be applied is roughened, as in the insulating layer 13, in
order to improve an adhesion force between each of vias 14 and the
insulating layer 12. When the terminal pitch of the semiconductor
package 20 to be mounted is narrow and the solder short is feared,
the solder resist may be formed on the surface of the insulating
layer 13 after the wiring layer 15 has been formed.
[0117] By the steps described above, the curved board 10 is formed.
Then, by mounting the semiconductor package 20 on the curved board
10 via the solder balls 30, the mount board 1 is formed (refer to
FIG. 5E).
[0118] Herein, an example of a two-layer structure formed of the
wiring layers 12 and 15 is shown for simplicity. However, in the
step in FIG. 5A, a multi-layer circuit board formed by lamination
using a build-up process, a simultaneous lamination process, or the
like may be employed for the base member 11, so that development
into the multi-layer circuit board can be readily realized.
Further, the pedestal portion 13a formed of the insulating layer 13
may be simultaneously formed on both surfaces of the base member
11. On that occasion, the pedestal portion 13a can be arranged on
both surfaces of the base member 11 so that pads for the
semiconductor package are flat. Both surface mounting of the
semiconductor packages 20 is thereby possible.
[0119] Next, a second manufacturing method of the mount board
according to the first exemplary embodiment will be described using
drawings. FIGS. 6A to 6F include sectional views of processing
steps schematically showing the second manufacturing method of the
mount board according to the first exemplary embodiment of the
present invention.
[0120] In the first manufacturing method in FIG. 5, molding of the
insulating layer 13 having the pedestal portion 13a is performed
simultaneously with curving of the entire board. In the second
manufacturing method in FIG. 6, the molding of the pedestal portion
13a is performed separately from the curving of the entire board.
The second manufacturing method will be described below.
[0121] First, the wiring layer 12 is formed on the base member 11
(refer to FIG. 6A). Next, the sheet-like insulating layer 13 is
formed over the base member 11 and the wiring layer 12 (refer to
FIG. 6B). The steps described so far are the same as those in FIGS.
5A and 5B.
[0122] Next, the pedestal portion 13a of the insulating layer 13 is
molded by press processing (refer to FIG. 6C). The pedestal portion
13a on which the semiconductor package 20 is mounted is molded into
a shape having a curvature, on which the pads are flatly arranged,
at a time of curving the board in a subsequent step.
[0123] Next, the via holes are formed in the insulating layer 13.
Then, the vias 14 and the wiring layer 15 are formed (refer to FIG.
6D). Incidentally, this step is the same as that in FIG. 5D.
[0124] Next, using press molds (not shown), the entire board is
curved by heating and pressurization (refer to FIG. 6E). As the
press molds used in this step, the press molds which are similar to
the press molds 40 shown in FIG. 5C may be employed.
[0125] By the steps described above, the curved board 10 is formed.
By mounting the semiconductor package 20 on the curved board 10 via
the solder balls 30, the mount board 1 is formed (refer to FIG.
6F).
[0126] As described above, separation between the molding step of
the insulating layer 13 and the curving step of the entire board is
effective when the curvature of the curved board 10 is extremely
large or the area of the board is extremely large. When the
curvature of the curved board 10 or the area of the board is
extremely large, it is necessary for the wiring layer 15,
facilities for forming the vias 14, and tooling to accommodate the
curvature or the area of the curved board 10, in the step of
forming the wiring layer 15 on the curved board 10 as shown in FIG.
5D, for example. However, the facilities and the tooling may become
complex or the sizes of the facilities and the tooling may be
increased. The facilities for forming the vias 14 are the
facilities associated with the steps of the present invention such
as an exposure machine for wiring, a photomask for wiring, a laser
device for drilling the vias, and an etching layer for forming
interconnects, for example. On the other hand, when the step of
forming the prepreg and the step of curving the entire board are
separated, the facilities related to formation of the wiring layer
15 and the vias 14 should only accommodate the curvature that
defines a mounting range of the semiconductor package alone. Thus,
there is an advantage that the conventional facilities can easily
accommodate the curvature or the area of the curved board.
[0127] According to the first exemplary embodiment, even when the
common semiconductor package 20 with the solder balls 30 arranged
in the lattice form is mounted, space variations between the
semiconductor package and respective pad portions can be
suppressed. The space variations will occur when the semiconductor
package is mounted on the pad portions formed on the curved surface
of a conventional curved board. Soldering quality, which is the
same as that when the semiconductor package is mounted on a flat
board, can be thereby ensured. Further, it is not necessary to
curve the semiconductor package 20 in conformity with the curved
surface of the curved board 10, either. Thus, there is also no fear
of electrical characteristic deterioration caused by a warp (or
strain) of the semiconductor chip 20.
Second Exemplary Embodiment
[0128] A mount board according to a second exemplary embodiment of
the present invention will be described using drawings. FIG. 7 is a
sectional view schematically showing a configuration of the mount
board according to the second exemplary embodiment of the present
invention.
[0129] The mount board 1 according to the second exemplary
embodiment has shoulder portions 13b on regions of the insulating
layer 13 adjacent to the pedestal portion 13a. Each shoulder
portion has a flat surface. The pad portions 15b for mounting
electronic components 50 are formed on the insulating layer 15 on
the shoulder portions 13b. The electronic components 50 are mounted
on the pad portions 15b. The flat surface of the shoulder portion
13b is parallel to a tangent to the curved-surface portion. Other
configurations are the same as those in the first exemplary
embodiment. As the electronic components 50, chip components such
as a resistor, a capacitor, a coil, and the like may be used. Other
semiconductor packages represented by a BGA, a CSP, and a QFP
except the chip components such as the resistor, capacitor, coil,
and the like can also be mounted.
[0130] Next, a method of manufacturing the mount board according to
the second exemplary embodiment will be described using drawings.
FIGS. 8A to 8E include sectional views of processing steps
schematically showing the method of manufacturing the mounding
board according to the second exemplary embodiment of the present
invention.
[0131] First, the wiring layer 12 is formed on the base member 11
(refer to FIG. 8A). Next, the sheet-like insulating layer 13 is
formed over the base member 11 and the insulating layer 12 (refer
to FIG. 8B). The steps described so far are the same as those in
FIGS. 5A and 5B.
[0132] Next, molding of the pedestal portion 13a and the shoulder
portions 13b of the insulating layer 13 and molding of the curved
surface of the board are simultaneously performed by press
processing, and the insulating layer 13 is cured (refer to FIG.
8C). Herein, shapes of press molds 42 are different from those of
the press molds 40 in FIG. 5C in order to obtain the surface of
each shoulder portion 13b in the form of a straight line close to
the tangent to the curved surface of the base member 11.
[0133] Next, the via holes are formed in the insulating layer 13.
Then, the vias 14 and the insulating layer 15 are formed (refer to
FIG. 8D). Incidentally, when the wiring layer 15 is formed, the pad
portions 15a for the semiconductor package and the pad portions 15b
for the electronic components are formed.
[0134] By the above steps, the curved board 10 is formed. Then, the
semiconductor package 20 is mounted on the curved board 10 via the
solder balls 30, and the electronic components 50 are also mounted.
The mount board 1 is thereby formed (refer to FIG. 8E).
[0135] According to the second exemplary embodiment, with respect
to the shape of the pedestal portion 13a in the mount board 1, the
surface of the shoulder portion 13b is formed flat as shown in FIG.
7. The electronic components 50 can be mounted on the shoulder
portion 13b as well, so that a higher mounting density can be
achieved. The capacitor and the coil in particular greatly affect
electrical characteristics. Thus, it is desired that the capacitor
and the coil be arranged as much as possible in the vicinity of the
semiconductor package 20. When the structure of the mount board 1
according to the second exemplary embodiment is adopted, the
electrical characteristics and product performance are improved.
The closer the straight line defined by the shape of the shoulder
portion 13 is to the tangent to the curved surface, the wider area
of the flat part of the shoulder portion 13 can be ensured. The
area for mounting can be thereby utilized to the fullest
extent.
Third Exemplary Embodiment
[0136] A mount board according to a third exemplary embodiment of
the present invention will be described using drawings. FIG. 9 is a
sectional view schematically showing a configuration of the mount
board according to the third exemplary embodiment of the present
invention.
[0137] In the mount board 1 according to the third exemplary
embodiment, concave parts (recesses) 13c are formed in the pedestal
portion 13a of the insulating layer 13. The pad portions 15a are
formed to be flat, irrespective of whether the upper surface of the
pedestal portion is planarized or not. It means that, while
planarization of the pad portions is achieved by planarizing the
pedestal portion in the first and second exemplary embodiments, it
is not always necessary for the pedestal portion 13a to be flat in
the third exemplary embodiment if only the upper surfaces of the
pad portions 15a are arranged to be flat. Other configurations are
the same as those in the first exemplary embodiment.
[0138] Next, a method of manufacturing the mount board according to
the third exemplary embodiment will be described using drawings.
FIGS. 10A to 10E include sectional views of processing steps
schematically showing the method of manufacturing the mount board
according to the third exemplary embodiment of the present
invention.
[0139] First, the wiring layer 12 is formed on the base member 11
(refer to FIG. 10A). Next, the sheet-like insulating layer 13 is
formed over the base member 11 and the wiring layer 12 (refer to
FIG. 10B). These steps described so far are the same as those in
FIGS. 5A and 5B.
[0140] Next, molding of the pedestal portion 13a and the concave
parts 13c of the insulating layer 13 and molding of the curved
surface of the board are simultaneously performed (refer to FIG.
10C). Herein, a desired concavo-convex (i.e., profiled) shape is
formed in a press mold 43 in advance.
[0141] Next, the via holes are formed in the insulating layer 13.
Then, the vias 14 and the wiring layer 15 are formed (refer to FIG.
10D). By the steps described above, the curved board 10 is formed.
Then, a semiconductor package 20 is mounted on the curved board 10
via solder balls 30. The mount board 1 is thereby formed (refer to
FIG. 10E).
[0142] According to the third exemplary embodiment, by very simple
means of a change in the shape of the press mold 43, a structure
having the concave parts 13c of the pedestal portion 13a between
the pad portions 15a can be implemented. Then, by including the
concave parts 13c, an effect of easing stress caused by a
difference between thermal expansion coefficients of the
semiconductor package 20 and the curved board 10 can be expected.
The stress may arise on an electric connecting portion such as
solder or an interface between the solder and a pad due to an
environmental load such as a temperature cycle. A mounting
structure with higher reliability can be thereby obtained.
Fourth Exemplary Embodiment
[0143] A mount board according to a fourth exemplary embodiment of
the present invention will be described using drawings. FIG. 11 is
a sectional view schematically showing a configuration of the mount
board according to the fourth exemplary embodiment of the present
invention.
[0144] In the mount board 1 according to the fourth exemplary
embodiment, a second insulating layer 16 is disposed between the
pedestal portion 13a and the base member 11, as an auxiliary
material for the insulating layer 13. Other configurations are the
same as those in the first exemplary embodiment.
[0145] No particular limitation is imposed on the material of the
second insulating layer 16 if only the material is the insulating
material. A thermosetting resin film may be applied as a material
of the second insulating layer 16. When a film material is
employed, a laminate formed by laminating films so as to obtain a
desired supply amount may be employed. As a more preferable
material to be used for the second insulating layer 16, a
thermoplastic resin may be pointed out. By employing the
thermoplastic resin having a high softening level within a
temperature range at a time of molding the insulating layer 13,
improvement in a molding property of the pedestal portion 13a and a
curved-surface molding property of the board can be expected.
Further, for the second insulating layer 16, a material that will
be melted by heating and then will be mixed into the prepreg may be
employed. Alternatively, the second insulating layer 16 may be
formed of a plurality of materials (in a hybrid-type resin
including the thermoplastic resin and the thermosetting resin, for
example). When rigidity is demanded, an inorganic material may be
used for the second insulating layer 16.
[0146] Next, a method of manufacturing the mount board according to
the fourth exemplary embodiment will be described using drawings.
FIGS. 12A to 12F include sectional views of processing steps
schematically showing the method of manufacturing the mount board
according to the fourth exemplary embodiment of the present
invention.
[0147] First, the wiring layer 12 is formed on the base member 11
(refer to FIG. 12A). Next, the second insulating layer 16 is formed
at a position corresponding to the pedestal portion (indicated by
reference numeral 13a in FIG. 12C) on the base member 11 and over
the wiring layer 12. Then, the sheet-like (first) insulating layer
13 is formed over the base member 11, wiring layer 12, and second
insulating layer 16 (refer to FIG. 12B). Next, the pedestal portion
13a of the wiring layer 13 is molded by press processing (refer to
FIG. 12C). Next, the via holes are formed in the insulating layer
13 (and in the second wiring layer 16 depending on the position of
a via hole). Then, the vias 14 and the insulating layer 15 are
formed (refer to FIG. 12D). Next, using press molds (not shown),
the entire board is curved by heating and pressurization (refer to
FIG. 12E). Then, the semiconductor package 20 is mounted on the
curved board 10 via the solder balls 30. The mount board 1 is
thereby formed (refer to FIG. 12F).
[0148] According to the fourth exemplary embodiment, the second
insulating layer 16 is disposed between the pedestal portion 13a
and the base member 11. There may be a case where a sufficient
amount for forming the pedestal portion 13a cannot be ensured with
the insulating layer 13 alone because the curvature of the curved
board 10 is large or the size of the semiconductor package 20 to be
mounted is large. The mount board of the fourth exemplary
embodiment can cope with such a case.
Fifth Exemplary Embodiment
[0149] A mount board according to a fifth embodiment of the present
invention will be described using drawings. FIGS. 13A and 13B are
sectional views each schematically showing a configuration of the
mount board according the fifth exemplary embodiment of the present
invention. FIG. 13A relates to the mount board with the
semiconductor package mounted on a convex side thereof, and FIG.
13B relates to the mount board with the semiconductor package
mounted on a concave side thereof.
[0150] In the first to fourth exemplary embodiments, the pedestal
portion is formed in the step of manufacturing the curved board
(circuit board) using the insulating layer. In the fifth exemplary
embodiment, a pedestal portion 62 is formed of an insulating
material other than that used for an insulating layer 61a. The
pedestal portion 62 is formed, separately from manufacture of a
circuit board 61. In a mount board 1 according to the fifth
exemplary embodiment, the pedestal portion 62 is arranged on the
circuit board 61 having a curved surface. Then, a wiring layer 63
that is electrically connected to a wiring layer 61d on the circuit
board 61 is formed on the pedestal portion 62. Pad portions 63a
that lead to the wiring layer 63 are formed on the flat surface of
the pedestal portion 62.
[0151] Herein, as the circuit board 61, a flat circuit board formed
by a customary manufacturing method and then processed to have a
curved surface by a method such as thermal pressing may be
employed. In the circuit board 61, a wiring layer 61b is embedded
within an insulating layer 61a, and a wiring layer 61d is disposed
on the insulating layer 61a. The wiring layer 61d is electrically
connected to the wiring layer 61b through each via 61c.
[0152] The pedestal portion 62 is formed on the curved circuit
board 61. For the pedestal portion 62, an insulating material of a
resin material, an inorganic material such as glass, or a
filler-containing resin material may be employed. The resin
material is an organic material. As the pedestal portion 62, the
pedestal portion processed into the shape as shown in FIG. 13A or
13B in advance by a method such as resin molding or cutting molding
(generally, shaping) may be attached. Alternatively, the pedestal
portion 62 may be formed by printing and then curing a paste-like
or a liquid-like material or curing by a molding method or the
like.
[0153] The wiring layer 63 includes the pad portions 63a and is
formed on the pedestal portion 62 so that the wiring layer 63 is
electrically connected to the wiring layer 61d on the circuit board
61. The pad portions 63a are formed on the flat surface of the
pedestal portion 62. For formation of the wiring layer 63, a method
of drawing a conductive paste by printing or an ink jet method and
then curing the drawn conductive past may be employed. The pad
portions 63a are electrically connected to external terminals 21 of
the semiconductor package 20 via the solder balls 30.
[0154] According to the fifth exemplary embodiment, interconnect
(wiring) formation and lamination need not be performed on the
curved surface of the circuit board 61 in the manufacturing step of
the circuit board 61. Thus, in the manufacturing step of the
circuit board 61, the flat circuit board manufactured by
conventional facilities and the conventional method may be
applied.
Sixth Exemplary Embodiment
[0155] A mount board according to a sixth exemplary embodiment of
the present invention will be described using drawings. FIGS. 14A
and 14B are sectional views each schematically showing a
configuration of a mount board according to the sixth exemplary
embodiment of the present invention. FIG. 14A shows the mount board
with a semiconductor package mounted on a convex side thereof. FIG.
14B shows a mount board with a semiconductor package mounted on a
concave side thereof.
[0156] In the mount board 1 according to the sixth exemplary
embodiment, electronic components 50 are included within a pedestal
portion 62. Other configurations are the same as those in the fifth
exemplary embodiment. The pedestal portion 62 is formed by mounting
the other electronic component(s) 50 (such as a chip resistor, a
chip capacitor, and a chip coil) on the curved circuit board 61 in
advance and then performing post processing.
[0157] According to the sixth exemplary embodiment, the electronic
component(s) 50 is (are) included within the pedestal portion 62. A
higher density of mounting of the components can be therefore
achieved, thereby allowing contribution to size reduction and
thickness reduction of a final product. Further, the closer an
electrical distance of the capacitor that becomes necessary for
noise removal of the semiconductor package 20 to the semiconductor
package is, the more the effect of noise removal is increased.
Thus, significant performance improvement in terms of electrical
characteristics as well can be expected. An effect can also be
obtained in which a range of application to a high-speed
semiconductor application or the like is expanded.
Seventh Exemplary Embodiment
[0158] A mount board according to a seventh exemplary embodiment of
the present invention will be described using drawings. FIGS. 15A
and 15B are sectional views each schematically showing a
configuration of a mount board according to the seventh exemplary
embodiment of the present invention. FIG. 15A relates to a mount
board with a semiconductor package mounted on a convex side
thereof. FIG. 15B relates to a mount board with the semiconductor
package mounted on a concave side thereof.
[0159] In a mount board 1 according to the seventh exemplary
embodiment, a semiconductor package 20 is mounted within a pedestal
portion 62. As a manufacturing method, the semiconductor package 20
is arranged on a curved circuit board 61 so that external terminals
21 of the semiconductor package 20 are placed on an opposite side
of the surface of the board. Then, a paste-like insulating material
or a liquid-like insulating material is printed and then cured,
thereby forming the pedestal portion 62. A wiring layer 63 is
formed over the semiconductor package 20 and the pedestal portion
62. The wiring layer 63 is formed of a conductive paste that has
been drawn by printing or by an ink jet method and then cured. The
wiring layer 63 is formed over the pedestal portion 62 and the
semiconductor package 20 so that the wiring layer 63 is
electrically connected to a wiring layer 61d on the circuit board
61 and the external terminals 21 of the semiconductor package
20.
[0160] As described above, by embedding the semiconductor package
20 within the pedestal portion 62, the occupied volume for mounting
of the semiconductor package 20 can be minimized. This can greatly
contribute to size reduction and thickness reduction of a final
product.
Eighth Exemplary Embodiment
[0161] A mount board according to an eighth exemplary embodiment of
the present invention will be described using drawings. FIGS. 16A
and 16B are sectional views each schematically showing a
configuration of the mount board according to the eighth exemplary
embodiment of the present invention. FIG. 16A shows the mount board
with the semiconductor package mounted on a convex side thereof.
FIG. 16B shows the mount board with the semiconductor package
mounted on a concave side thereof.
[0162] In the mount board 1 according to the eighth exemplary
embodiment, the semiconductor package 20 is arranged within the
pedestal portion 62. The electronic components 50 are mounted over
the external terminals 21 of the semiconductor package 20 via the
wiring layer 63. Other configurations are the same as those in the
seventh exemplary embodiment.
[0163] According to the eighth exemplary embodiment, a high-density
mounting structure that has efficiently utilized a mounting area
can be obtained.
[0164] As described above, a mounting structure of the curved board
in conformity with the curved surface of a case, which is excellent
in component arrangement efficiency within the case for an
electronic device formed of curved surfaces, can be implemented.
Accordingly, by applying this structure to the electronic device of
which design is regarded as important, a product's added value can
be increased. The present invention is useful for being applied to
a portable device such as a cellular phone, a digital still camera,
a PDA (Personal Digital Assistant), a notebook personal computer,
or the like for which size reduction and thickness reduction are
particularly demanded.
* * * * *