U.S. patent application number 11/949048 was filed with the patent office on 2009-01-01 for semiconductor structure.
Invention is credited to Chih-Hao Cheng, Chung-Yuan Lee, Tzung-Han Lee.
Application Number | 20090001457 11/949048 |
Document ID | / |
Family ID | 40159340 |
Filed Date | 2009-01-01 |
United States Patent
Application |
20090001457 |
Kind Code |
A1 |
Lee; Tzung-Han ; et
al. |
January 1, 2009 |
Semiconductor structure
Abstract
The present invention discloses a semiconductor structure
comprising a semiconductor substrate having a U-shape trench, a
U-shape gate dielectric layer on the U-shape trench, a U-shape gate
region on the U-shape gate dielectric layer, a conducting matter in
the U-shape gate region, and a cover dielectric layer on the
conducting matter. The semiconductor structure may have a minimized
size and when recess channels are formed thereby, the integration
is accordingly improved without suffering from the short channel
effect.
Inventors: |
Lee; Tzung-Han; (Taipei
City, TW) ; Cheng; Chih-Hao; (Taipei County, TW)
; Lee; Chung-Yuan; (Tao-Yuan City, TW) |
Correspondence
Address: |
NORTH AMERICA INTELLECTUAL PROPERTY CORPORATION
P.O. BOX 506
MERRIFIELD
VA
22116
US
|
Family ID: |
40159340 |
Appl. No.: |
11/949048 |
Filed: |
December 3, 2007 |
Current U.S.
Class: |
257/330 ;
257/E29.262 |
Current CPC
Class: |
H01L 27/10891 20130101;
H01L 27/10876 20130101 |
Class at
Publication: |
257/330 ;
257/E29.262 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 26, 2007 |
TW |
096123070 |
Claims
1. A semiconductor structure comprising: a semiconductor substrate
having a U-shaped trench in the semiconductor substrate; a U-shaped
gate dielectric layer formed on a surface of the U-shaped trench; a
U-shaped gate region formed on a top surface of the U-shaped gate
dielectric layer; a conducting matter formed in the U-shaped trench
and enclosed by the U-shaped gate region, wherein the conducting
matter is electrically connected to the U-shaped gate region; and a
cover dielectric layer formed on top of the U-shaped trench to
cover the U-shaped gate region and the conducting matter.
2. The semiconductor structure of claim 1, wherein the conducting
matter is served as a word line.
3. The semiconductor structure of claim 1, wherein the conducting
matter comprises a material selected from the group consisting of
tungsten, nickel, copper, cobalt, a combination thereof, and a
silicide thereof.
4. The semiconductor structure of claim 1 further comprising a
U-shaped adhesive layer formed between the U-shaped gate region and
the conducting matter.
5. The semiconductor structure of claim 4, wherein the adhesive
layer comprises a material selected from the group consisting of
titanium, tantalum, an alloy thereof, and a nitride thereof.
6. The semiconductor structure of claim 4, wherein the cover
dielectric layer covers the adhesive layer on top of the U-shaped
trench.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a structure of a
semiconductor device, and particularly to a structure of a buried
word line.
[0003] 2. Description of the Prior Art
[0004] As electronic products are becoming lighter, thinner,
shorter, and smaller, dynamic random access memory (DRAM)
geometries are being scaled down to match the trends of high
integration and high density. DRAM composed of a lot of memory
cells is one of the most popular volatile memory devices. Each
memory cell of DRAM comprises a MOS (metal-oxide-semiconductor)
transistor and at least a capacitor stacked each other in a series
connection. By using word lines and bit lines, DRAM can be read and
programmed.
[0005] In order to miniaturize DRAM, gate channel length is
shortened, but the short channel effect becomes an obstacle to the
improvement of the integration of the semiconductor device. Methods
of avoiding the short channel effect had been proposed, for
example, decreasing the thickness of the gate oxide layer,
increasing dopant concentration, and the like. However, theses
methods may encounter some problems, such as low element
reliability and slow data transfer rates, and are unsuitable to be
actually used.
[0006] In order to solve these problems, a hole type recess channel
MOS transistor has been developed and gradually adopted to increase
the integration. In comparison with a conventional horizontal MOS
transistor, the hole type recess channel MOS transistor includes
the gate and the source/drain formed in an etched trench of a
semiconductor substrate, and furthermore, the gate channel region
is disposed at the bottom portion of the trench, thereby to reduce
the horizontal area of the MOS transistor for improving the device
integration.
[0007] FIG. 1 illustrates a schematically cross-sectional view of a
recess channel MOS transistor device having a gate structure and a
word line structure thereabove, which is constructed in a
semiconductor substrate 10. The MOS transistor includes a gate
oxide layer 12, a polysilicon layer 14, a doped polysilicon layer
16, an inner spacer 18, a polysilicon layer 20, a tungsten metal
layer 22, a silicon nitride layer 24, and spacers 26. The tungsten
metal layer 22 serving as a word line is disposed above the surface
of the semiconductor substrate 10.
[0008] To improve the integration of a semiconductor device is
constantly a subject to be researched and developed, and,
therefore, there is still a need for a novel MOS transistor device
structure.
SUMMARY OF THE INVENTION
[0009] One object of the present invention is to provide a
structure of a buried word line, which has a film stack structure.
Each film may be very thin, and accordingly the integration of the
semiconductor device can be improved.
[0010] The semiconductor structure according to the present
invention comprises a semiconductor substrate having a U-shaped
trench in the semiconductor substrate; a U-shaped gate dielectric
layer formed on a surface of the U-shaped trench; a U-shaped gate
region formed on a top surface of the U-shaped gate dielectric
layer; a conducting matter formed in the U-shaped trench and
enclosed by the U-shaped gate region, wherein the conducting matter
is electrically connected to the U-shaped gate region; and a cover
dielectric layer formed on top of the U-shaped trench to cover the
U-shaped gate region and the conducting matter.
[0011] The semiconductor structure according to the present
invention is a film stack structure, in which, a buried word line
and a recess channel is formed in the semiconductor substrate.
Since each film of the film stack structure can be very thin, the
integration of the semiconductor device can be improved.
Furthermore, due to the design of recess channel, the short channel
effect can be avoided.
[0012] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 illustrates a schematically cross-sectional view of a
conventional recess channel MOS transistor device having a gate
structure and a word line structure above the gate structure;
[0014] FIGS. 2 and 3 illustrate schematically cross-sectional views
of some embodiments of the semiconductor structure according to the
present invention; and
[0015] FIGS. 4 and 5 illustrate schematically partially
cross-sectional views and partially perspective views of some
embodiments of the semiconductor structure according to the present
invention.
DETAILED DESCRIPTION
[0016] FIG. 2 illustrates a schematically cross-sectional view of
an embodiment of the present invention, which may be utilized in an
EUD type transistor. The semiconductor structure as shown in FIG. 2
comprises a semiconductor substrate 50 and a film stack structure
of a U-shape gate dielectric layer 52, a U-shape gate region 54, a
conducting layer 56, and a cover dielectric layer 58.
[0017] The semiconductor substrate 50 has a U-shaped trench
therein. The U-shape gate dielectric layer 52 is disposed on the
surface of the U-shape trench of the semiconductor substrate 50 and
may be for example a silicon oxide compound layer formed by the
oxidation of the silicon at the surface of the semiconductor
substrate. It has to be mentioned here that the surface of the
U-shape trench of the semiconductor substrate 50 means for the
inner surface of the U-shape trench or the outer surface of the
U-shape trench.
[0018] The U-shape gate region 54 is disposed in the U-shape trench
formed in the U-shape gate dielectric layer 52. The gate region 54
may be deposited into the trench by deposition and then etched back
to form a recess for subsequent formation of the conducting layer
therein. The gate region 54 may comprise, for example,
polysilicon.
[0019] The conducting layer 56 is disposed in the recess of the
U-shape gate region 54 to serve as a word line and may comprise,
for example, one selected from the group consisting of tungsten,
nickel, copper, cobalt, a combination thereof, and a silicide
thereof or a material of low resistance.
[0020] A cover dielectric layer 58 covers the top of the conducting
layer 56 and the top of the U-shape gate region 54. The cover
dielectric layer 58 and the gate dielectric layer 52 together
separate the conducting layer 56 and the U-shape gate region 54
from the semiconductor substrate 50. The cover dielectric layer may
include dielectric material such as silicon nitride, silicon oxide,
and the like. The height of the bottom of the cover dielectric
layer 58 is substantially lower than the height of the top 60 of
the semiconductor substrate 50. In such structure, the
semiconductor structure according to the present invention is
entirely buried in the semiconductor substrate, such that the part
of the semiconductor substrate 50 surrounding the U-shape gate
dielectric layer 52 forms a gate channel.
[0021] Furthermore, an adhesive layer 62 may be optionally disposed
between the U-shape gate region 54 and the conducting layer 56, as
shown in FIG. 3. The adhesive layer 62 is also in a U-shape because
it is between the U-shape gate region and the conducting layer. The
adhesive layer 62 may comprise one selected from the group
consisting of titanium, tantalum, an alloy thereof, and a nitride
thereof, for example, Ti, Ta, TiN, TaN, TiTa alloy, and the like,
or a material of low resistance. The adhesive layer improves the
adhesion of the conducting layer to the gate region and also plays
a role as a barrier layer to inhibit the diffusion of the
ingredients of the conducting layer into the gate region to affect
the electric properties.
[0022] Furthermore, the semiconductor structure according to the
present invention may have other modified aspects. For example,
referring to FIG. 4 showing a schematically partially
cross-sectional view and partially perspective view of a
semiconductor structure according to the present invention, the
bottom portions of the U-shape trench of the semiconductor
substrate, the U-shape gate dielectric layer 52, the U-shape gate
region 54, and the conducting layer 56 together may have an indent,
such that the semiconductor substrate has a corresponding fin
structure. Alternatively, the semiconductor structure may further
have an adhesive layer, as shown in FIG. 5. The bottom portions of
the U-shape trench of the semiconductor substrate, the U-shape gate
dielectric layer 52, the U-shape gate region 54, the adhesive layer
62, and the conducting layer 56 may together have an indent, such
that the semiconductor substrate has a corresponding fin structure.
Such structure may be utilized in a fin transistor.
[0023] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention.
* * * * *