U.S. patent application number 12/198857 was filed with the patent office on 2008-12-25 for metal gated ultra short mosfet devices.
This patent application is currently assigned to International Business Machines Corporation. Invention is credited to Jack Oon Chu, Bruce B. Doris, Meikei Ieong, Jing Wang.
Application Number | 20080318374 12/198857 |
Document ID | / |
Family ID | 38618671 |
Filed Date | 2008-12-25 |
United States Patent
Application |
20080318374 |
Kind Code |
A1 |
Chu; Jack Oon ; et
al. |
December 25, 2008 |
Metal Gated Ultra Short MOSFET Devices
Abstract
MOSFET devices suitable for operation at gate lengths less than
about 40 nm, and methods of their fabrication is being presented.
The MOSFET devices include a ground plane formed of a
monocrystalline Si based material. A Si based body layer is
epitaxially disposed over the ground plane. The body layer is doped
with impurities of opposite type than the ground plane. The gate
has a metal with a mid-gap workfunction directly contacting a gate
insulator layer. The gate is patterned to a length of less than
about 40 nm, and possibly less than 20 nm. The source and the drain
of the MOSFET are doped with the same type of dopant as the body
layer. In CMOS embodiments of the invention the metal in the gate
of the NMOS and the PMOS devices may be the same metal.
Inventors: |
Chu; Jack Oon; (Manhasset,
NY) ; Doris; Bruce B.; (Brewster, NY) ; Ieong;
Meikei; (Wappingers Falls, NY) ; Wang; Jing;
(Beacon, NY) |
Correspondence
Address: |
INNOVATION INTERFACE, LLC
303 TABER AVENUE
PROVIDENCE
RI
02906
US
|
Assignee: |
International Business Machines
Corporation
Armonk
NY
|
Family ID: |
38618671 |
Appl. No.: |
12/198857 |
Filed: |
August 26, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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12013704 |
Jan 14, 2008 |
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12198857 |
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11407473 |
Apr 20, 2006 |
7348629 |
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12013704 |
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Current U.S.
Class: |
438/211 ;
257/E21.191; 257/E21.631; 257/E29.055; 257/E29.27 |
Current CPC
Class: |
H01L 21/28017 20130101;
H01L 29/105 20130101; H01L 29/7838 20130101 |
Class at
Publication: |
438/211 ;
257/E21.631 |
International
Class: |
H01L 21/8238 20060101
H01L021/8238 |
Claims
1. A method for manufacturing a MOSFET device, comprising: forming
a ground plane of a monocrystalline Si based material, and
selecting dopant impurities in said ground plane to be of a first
type with a concentration of between about
1.times.10.sup.18/cm.sup.3 and 1.times.10.sup.20/cm.sup.3;
depositing by selective epitaxy a body layer of between about 2 nm
and 7 nm thickness over said ground plane, whereby creating an
interface between said ground plane and said body layer, in-situ
doping said body layer with impurities of a second type to a
concentration of between about 5.times.10.sup.18/cm.sup.3 and
5.times.10.sup.19/cm.sup.3, and keeping a region of transition
between said first type and said second type of dopant impurities
to a width across said interface of between about 2.5 nm and 0.5
nm; disposing a gate insulator layer over said body layer;
disposing a gate over said gate insulator layer, wherein said gate
comprises a mid-gap workfunction metal which is in direct contact
with said gate insulator layer, and patterning said gate to a
length of less than about 40 nm; and forming a source and a drain,
selecting dopant impurities in said source and said drain to be of
said second type with a concentration of between about
5.times.10.sup.19/cm.sup.3 and 2.times.10.sup.20/cm.sup.3, and
keeping the junction depths of said source and said drain to less
than about 7 nm.
2. The method of claim 1, further comprising the selection of said
dopant impurities of said first type to be n-type, and said dopant
impurities of said second type to be p-type.
3. The method of claim 1, further comprising the selection of said
dopant impurities of said first type to be p-type, and said dopant
impurities of said second type to be n-type.
4. The method of claim 1, further comprising the selection of said
monocrystalline Si based material and said Si based body layer to
be essentially of pure Si.
5. The method of claim 1, wherein said forming of said ground plane
comprises epitaxial deposition and in-situ doping of said
monocrystalline Si based material.
6. The method of claim 1, wherein said forming of said ground plane
comprises ion implantation and annealing of said first type of
dopant impurities in said monocrystalline Si based material.
7. The method of claim 1, wherein said forming of said source and
said drain include a selective deposition for raising said source
and said drain, followed by ion implanting and annealing said
second type of dopant impurities.
8. The method of claim 1, wherein said forming of said source and
said drain include selectively depositing a Si based material into
hollowed regions of said source and said drain, and in-situ
introducing said second type of dopant impurities into said source
and said drain.
9. The method of claim 1, wherein the processes of forming of said
ground plane, depositing of said body layer, disposing of said gate
insulator layer, disposing of said gate, are all carried out in a
single vacuum system, without breaking vacuum inbetween carrying
out said processes.
10. A method for manufacturing a CMOS circuit, comprising:
processing at least one NMOS device comprising of: forming a ground
plane of a monocrystalline Si based material, and selecting p-type
impurities in said ground plane to be of a concentration of between
about 1.times.10.sup.18/cm.sup.3 and 1.times.10.sup.20/cm.sup.3;
depositing by selective epitaxy a body layer of between about 2 nm
and 7 nm thickness over said ground plane, whereby creating an
interface between said ground plane and said body layer, in-situ
doping said body layer with n-type impurities to a concentration of
between about 5.times.10.sup.18/cm.sup.3 and
5.times.10.sup.19/cm.sup.3, and keeping a region of transition
between said p-type and said n-type impurities to a width across
said interface of between about 2.5 nm and 0.5 nm; forming a source
and a drain, selecting dopant impurities in said source and said
drain to be of n-type with a concentration of between about
5.times.10.sup.19/cm.sup.3 and 2.times.10.sup.20/cm.sup.3, and
keeping the junction depths of said source and said drain to less
than about 7 nm; and, processing at least one PMOS device
comprising of: forming a ground plane of a monocrystalline Si based
material, and selecting n-type impurities in said ground plane to
be of a concentration of between about 1.times.10.sup.18/cm.sup.3
and 1.times.10.sup.20/cm.sup.3; depositing by selective epitaxy a
body layer of between about 2 nm and 7 nm thickness over said
ground plane, whereby creating an interface between said ground
plane and said body layer, in-situ doping said body layer with
p-type impurities to a concentration of between about
5.times.10.sup.18/cm.sup.3 and 5.times.10.sup.19/cm.sup.3, and
keeping a region of transition between said n-type and said p-type
impurities to a width across said interface of between about 2.5 nm
and 0.5 nm; forming a source and a drain, selecting dopant
impurities in said source and said drain to be of p-type with a
concentration of between about 5.times.10.sup.19/cm.sup.3 and
2.times.10.sup.20/cm.sup.3, and keeping the junction depths of said
source and said drain to less than about 7 nm; and, processing each
of said at least one NMOS device and said at least one PMOS device,
comprising of: disposing a gate insulator layer over said body
layer; disposing a gate over said gate insulator layer, wherein
said gate comprises a mid-gap workfunction metal which is in direct
contact with said gate insulator layer, and selecting said metal of
said NMOS gate and said metal of said PMOS gate to be identical
metals.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation of application Ser. No.
12/013,704, filed Jan. 14, 2008, which application in turn is a
Divisional of application Ser. No. 11/407,473, filed Apr. 20, 2006,
now U.S. Pat. No. 7,348,629 issued Mar. 25, 2008. Both of these
parent applications are incorporated herein by reference in their
entirety.
FIELD OF THE INVENTION
[0002] The present invention relates to electronic devices. In
particular it relates to less than 40 nm gate length field effect
devices and methods of producing such structures.
BACKGROUND OF THE INVENTION
[0003] Today's integrated circuits include a vast number of
devices. Smaller devices and shrinking ground rules are the key to
enhance performance and to improve reliability. As FET (Field
Effect Transistor) devices are being scaled down, the technology
becomes more complex, and changes in device structures and new
fabrication methods are needed to maintain the expected performance
enhancement from one generation of devices to the next. The
mainstay material of microelectronics is silicon (Si), or more
broadly, Si based materials. One such Si based material of
importance for microelectronics is the silicon-germanium (SiGe)
alloy.
[0004] There is great difficulty in maintaining performance
improvements in devices of deeply submicron generations. Various
detrimental device effects become more serious with successively
decreasing device dimensions. For instance, with shortening gate
lengths the so called short channel effects (SCEs), most notably
drain-induced barrier lowering (DIBL) pose severe roadblocks to
miniaturization. Also, parasitic capacitances, such as source and
drain capacitance, stand in the way of device performance. At the
same time, achieving ever higher gate capacitance runs into
roadblocks, such as the depletion of the gate material, which
traditionally has been poly-Si.
[0005] Traditionally, CMOS technologies advance from one generation
to the next by scaling the gate length. This is accomplished by
thinning the gate dielectric, increasing the channel doping and
forming shallower source/drains. Thus far, gate dimensions have
been scaled down to about 40 nm by using this approach for MOSFET
(Metal Oxide Semiconductor Field-Effect-Transistor) devices with
poly-Si gate electrodes. Many elements needed to support the gate
length scaling scheme are approaching physical limitations. For
instance, making junctions highly conductive, and simultaneously of
shallow depth, with the use of ion implantation and annealing
becomes very difficult, due to dopant activation and diffusion
effects. For standard processes, higher dopant activation (at
higher temperatures) is usually accompanied by additional diffusion
issues and concerns. Furthermore, excessive junction leakage may
prevent channel doping from being increased beyond the
concentration needed to control short channel effects for less than
40 nm gate length devices. Thus, a new device design, architecture,
and processing methodology is needed to overcome the drawbacks
associated with the prior art.
SUMMARY OF THE INVENTION
[0006] In view of the problems discussed above this invention
discloses a MOSFET suitable for operation at gate lengths less than
40 nm. Such a MOSFET device includes a ground plane formed of a
monocrystalline Si based material. This ground plane has dopant
impurities of a concentration of between about
1.times.10.sup.18/cm.sup.3 and 1.times.10.sup.20/cm.sup.3. A Si
based body layer is epitaxially disposed over the ground plane with
a thickness of between about 2 nm and 7 nm. The body layer is doped
with impurities of opposite type than the ground plane at a
concentration of between about 1.times.10.sup.18/cm.sup.3 and
5.times.10.sup.19/cm.sup.3. The transition region between the
dopants of the ground plane and the dopants of the body layer has a
width across their interface of between about 2.5 nm and 0.5 nm. A
gate insulator layer is disposed over the body layer, and a gate is
disposed over the gate insulator layer. The gate has a metal with a
mid-gap workfunction directly contacting the gate insulator layer.
The gate is patterned to a length of less than about 40 nm, and
possibly less than 20 nm. The source and the drain of the MOSFET
are doped with the same type of dopant as the body layer, with a
concentration of between about 5.times.10.sup.19/cm.sup.3 and
2.times.10.sup.20/cm.sup.3. The junction depth of the source and
the drain is less than about 7 nm.
[0007] In representative embodiments of the present invention the
Si based material of the device is essentially pure Si.
[0008] In CMOS embodiments of the invention the metal in the gate
of the NMOS and the PMOS devices may be the same metal.
[0009] A method for fabricating a MOSFET suitable for operation at
gate lengths less than 40 nm is also disclosed. The method involves
depositing by selective epitaxy a body layer of between about 2 nm
and 7 nm thickness over a ground plane, and doping the ground plane
and the body layer with opposite type of doping impurities. The
method further includes disposing a mid-gap workfunction metal over
the gate insulator. The metal may be selected to be the same metal
for NMOS and PMOS devices in a CMOS configuration.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] These and other features of the present invention will
become apparent from the accompanying detailed description and
drawings, wherein:
[0011] FIG. 1A shows, in a schematic cross sectional view, an
embodiment, including raised source/drain, of a less than 40 nm
gate length MOSFET;
[0012] FIG. 1B shows, in a schematic cross sectional view, an
alternate embodiment of a less than 40 nm gate length MOSFET;
[0013] FIG. 1C gives selected MOSFET device parameters as functions
of structural parameters for selected preferred embodiments of the
present invention;
[0014] FIG. 2 shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where a
ground plane has been fabricated;
[0015] FIG. 3 shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where a
counter doped body layer has been fabricated;
[0016] FIG. 4 shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where a
gate insulator layer and a metal gate layer have been
processed;
[0017] FIG. 5 shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where
the gate has been patterned;
[0018] FIG. 6A shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where
the raised source/drain junctions are being formed; and
[0019] FIG. 6B shows, in a schematic cross sectional view, a stage
in the processing of a less than 40 nm gate length MOSFET, where
the source/drain regions are hollowed for selective deposition the
of source/drain junctions.
DETAILED DESCRIPTION OF THE INVENTION
[0020] FIG. 1A and FIG. 1B show, in a schematic cross sectional
view, exemplary embodiments of ultra short, less than about 40 nm
gate length MOSFET devices. The depicted embodiments incorporate
elements that are instrumental in achieving useful characteristics
for such ultra short gate length MOSFET devices. Embodiments of the
present invention are aimed at gate lengths less than about 40 nm,
with the 15 nm to 35 nm regime being preferred. It is also
preferred that a mid-gap workfunction metal be the material which
is in direct contact with the gate insulator. The metal gate
electrode is preferred due to its high carrier concentration, which
leads to low gate resistance and high gate capacitance. The term
"mid-gap" means that the workfunction of the gate material, in the
presented embodiments the metal, has a workfunction which is
roughly halfway between the workfunctions of the p-type and n-type
versions of the semiconductor material which forms the MOSFET. The
workfunction of the gate material influences the device threshold
(V.sub.t). For ultra short MOSFET devices the desired threshold
values are less than 0.5V, and possibly less than 0.2V. Satisfying
such threshold requirements, coupled with fulfilling demands for
high gate capacitance, and achieving acceptable short-channel
effects (SCEs), such as drain-induced barrier lowering (DIBL),
necessitates the inventive combinations of the present disclosure.
These include high dopant concentration substrate, or ground plane,
a device body hosting the channel which has the same doping type as
the channel mobile carriers, and ultra shallow, sharp, junctions.
The preferred doping ranges and physical dimensions of several
device components are inventive, and contrary to the accepted
teachings of the art. The sharp doping profiles needed to realize
embodiments of the present invention are made possible by novel low
temperature epitaxial techniques. In preferred embodiments of the
invention the ultra short gate MOSFET devices are combined into
CMOS configurations, in which the gates of the NMOS and PMOS
devices may comprise the same mid-gap workfunction metal.
[0021] In the art of microelectronics the material that has
progressed the farthest in miniaturization is silicon (Si). Si
based materials are various alloys of Si in the same basic
technological content as Si. One such Si based material of
importance for microelectronics is the silicon-germanium (SiGe)
alloy. The devices in the embodiments of the present invention are
hosted in Si based materials, typically SiGe with an up to about
20% of Ge concentration. In exemplary embodiments of the invention
the Si based material may be essentially pure Si.
[0022] Referring to FIG. 1A and FIG. 1B, the gate 30 of the MOSFET
device is disposed over the gate insulator layer 40. The material
which is in direct contact with the gate insulator layer 40 is a
metal 30' with a mid-gap workfunction. Such metals are know in the
art, they include W, Ta, TiN, and others. Through its workfunction
value the gate metal 30' has influence over the device threshold.
The indicating number 30' shows that the metal may be part of a
larger gate stack 30, which stack might include materials such as
poly-Si and poly-SiGe. In representative embodiments the gate 30
might include only the mid-gap metal, containing no other
materials. The wavy line terminating the top part of the gate 30 in
the figures indicates the possibility that, as known in the art,
several materials, or structures may be further involved in a
completed gate stack, or electrode.
[0023] The length 80 of the gate 30 may be the most important
device parameter determining device performance. The range of gate
lengths 80 contemplated in representative embodiments of this
invention are in the range of about 10 nm to about 40 nm, which is
classified as an "ultra short" regime in the microelectronics art.
In typical embodiments of the presented invention the gate length
80 is in the range of about 15 nm to about 35 nm.
[0024] Further referring to FIG. 1A and FIG. 1B, the device has a
monocrystalline Si based body layer 10. The body of the device
hosts the channel where the current conduction takes place along
the interface with the gate insulator 40, on the side opposing the
gate. The body layer 10 is epitaxially disposed over a ground plane
20. In representative embodiments the body layer 10 may be
epitaxially grown on the ground plane 20. The terms "epitaxially",
"epitaxy", "epi", etc. carry their customary usage: meaning the
single crystal lattice structure carries across an interface.
Typically in epitaxy a single crystal, or monocrystalline, material
forms a platform onto which another single crystal material with
matching crystalline characteristics is deposited by one of several
techniques known in the art. Such techniques include, for instance,
molecular beam epitaxy (MBE), and various types of chemical vapor
depositions (CVD).
[0025] In exemplary embodiments of this invention the body layer 10
has a thickness in the range of about 2 nm to about 7 nm. In
typical embodiments of the invention, the body layer 10 may be
about 5 nm thick. The body layer 10 is purposely doped with the
same type of dopant as the carriers of the device current.
Accordingly, for NMOS devices the body layer 10 is doped with
n-type impurities, such as P, As, Sb, and others know in the art;
and for PMOS devices the body layer 10 is doped with p-type
impurities, such as B, Ga, I, and others know in the art. The
concentration of the doping impurities in the body layer 10 is
selected to be in the range of about 1.times.10.sup.18/cm.sup.3 to
about 5.times.10.sup.19/cm.sup.3, with preferred embodiments having
the range of about 5.times.10.sup.18/cm.sup.3 to about
5.times.10.sup.19/cm.sup.3. The selection of such dopant
concentrations assures proper threshold value, good DIBL behavior,
and high current carrying capability in the devices. In this
disclosure, the dopant type found in the body layer 10, for
referential purposes, is named "second type". Where the layer
underneath the gate insulator is purposefully doped to be of the
same type as the mobile channel charge, at times is referred to as
"counter doped". The general concept of counter doping, typically
used for so called depletion type devices, was known in the art,
see for instance U.S. Pat. No. 5,780,899 to Hu. However, Hu does
not teach the present invention.
[0026] The MOSFET device has a ground plane 20 formed of a
monocrystalline Si based material. The dopant impurities in the
ground plane are of a type opposite to the type of the mobile
channel charge of the device. For NMOS devices the ground plane is
p-type, doped with impurities such as B, Ga, I, and others know in
the art; while for PMOS devices the ground plane is n-type, doped
with impurities such as P, As, Sb, and others know in the art. In
this disclosure the dopant type found in the ground plane 20, for
referential purposes, is named "first type". The level of doping in
the ground plane 20 influences important device behavioral
parameters including the threshold value, and the size of DIBL. For
the ultra short devices of the embodiments of the present
invention, the acceptable doping for the ground plane 20 may be in
the range of about 1.times.10.sup.18/cm.sup.3 to about
1.times.10.sup.20/cm.sup.3, with the preferred doping being in the
range of about 8.times.10.sup.18/cm.sup.3 to about
1.times.10.sup.19/cm.sup.3.
[0027] For the voltages encountered in the operation of ultra short
devices, which are typically less than about 2V, or even less than
about 1.5V, the doping concentration in the ground plane limits the
depletion regions to the range of less than about 20 nm.
Consequently, beyond the thickness of about 20 nm the actual
thickness of the ground plane is not a critical parameter in
determining device behavior, and can comfortably be adjusted
according to, for instance, ease of fabrication and design. The
general concept of ground planes in MOSFET designs is known in the
art, see for instance U.S. Pat. No. 6,391,752 to Colinge. However,
Colinge does not teach the present invention.
[0028] Further referring to FIG. 1A and FIG. 1B, the body layer 10
and the ground plane 20 have a common interface 15. Across this
interface an abrupt transition between the first and the second
type of dopant impurities may be needed for the desirable operation
of the MOSFET device. The selective epitaxial deposition of the
body layer 10, and the in-situ doping of the body layer during the
epitaxy may allow the desired abrupt transition between the dopant
impurities of first type in ground plane 20 and the dopant
impurities of the second type in body layer 10. In representative
embodiments of the invention the region of transition between the
first type and the second type of dopant impurities has a width
across the ground plane/body layer interface 15 of between about
2.5 nm and 0.5 nm. The 0.5 nm width may represent a transition over
about a single monolayer of the crystal structure.
[0029] The ground plane 20 is disposed over a substrate 100. If, as
preferred in the embodiments of the present invention, the ground
plane electrically isolates the device, then the nature of the
substrate is of no major importance. Typically, the substrate 100
may be a Si wafer, Si-on-insulator (SOI) structure,
SiGe-on-insulator (SGOI) structure, or an insulating layer, or
another support structure known in the art.
[0030] FIG. 1A shows an exemplary embodiment where the source 50
and the drain 50 (both noted with the single reference numeral 50,
since structurally they are interchangeable), are of a raised type.
Creating shallow source/drain junctions by the technique of
depositing material over the source and the drain is a technique
known in the art. Such a fabrication may include a selective
deposition process, an implantation, and a rapid thermal annealing,
or a laser annealing. The height of the source/drain material
protruding over the plane of the gate insulator/body layer
interface, which interface is indicated by a dashed line in FIGS.
1A and 1B, may typically be about 25 nm. Implanting into a material
of such thickness, coupled with rapid thermal annealing, or a laser
annealing techniques as known in the art, can produce the desired
junction properties for the MOSFET devices. In exemplary
embodiments of the invention the dopant concentration in the source
50 and the drain 50 are in the range of about
5.times.10.sup.19/cm.sup.3 to about 2.times.10.sup.20/cm.sup.3,
with the junction depths 84 not exceeding about 7 nm. Junction
depths are given relative to the gate insulator/body layer
interface, which interface is indicated with the dashed horizontal
line in various figures.
[0031] In FIG. 1A the bottom of the source/drain junctions are
drawn as being slightly deeper than the plane of the interface 15
between the ground plane 20 and the body layer 10. The relative
position of the source/drain junction depth 84 compared to the body
layer thickness should not be inferred, or limited, based on the
depictions of the figures. The junction depth 84 and the body layer
thickness are independently arrived at in various embodiments of
the present invention, and while they both fall into roughly the
same magnitude, each may be slightly larger then the other,
depending on the details of a particular embodiment. The situation
when the source/drain junction depth 84 and the body layer
thickness approximately coincide is amongst the exemplary
embodiments of the present invention.
[0032] FIG. 1B shows, in a schematic cross sectional view, an
alternate embodiment where the source 50 and the drain 50 are not
raised, but leveled as their top is approximately in the gate
insulator/body layer interface plane. In embodiments of the present
invention these leveled junctions have essentially the same dopant
concentration and junction depth as junctions of the raised
embodiments, namely a dopant concentration in the range of about
5.times.10.sup.19/cm.sup.3 to about 2.times.10.sup.20/cm.sup.3, and
source/drain junction depths 84 of less than about 7 nm. These type
of junctions in typical embodiments may be fabricated by selective
deposition of the junction material and in-situ doping.
[0033] The gate insulator 40 of the device may be similar to ones
know in the art. It may contain silicon dioxide, silicon
oxynitride, as well as, so called high-k materials. The gate
insulator may contain a crystalline portion, as well, as being
epitaxially grown over the body layer 10. Although the gate
insulator 40 may have many variation in its details, it is
preferable for it to have an equivalent oxide thickness (EOT) of
less than about 1 nm. The EOT, a concept known in the art, refers
to the thickness of such an SiO.sub.2 layer which has the same
capacitance per unit area as the insulator layer in question.
[0034] FIG. 1A also depicts sidewall spacers 70 on the sides of the
gate electrode. Such structures, and their fabrication, are know in
the art, and they are depicted in some of the figures, as they may,
or may not, be present in various embodiments of the invention.
[0035] Further referring to FIG. 1A and FIG. 1B, the lateral
extension of the depicted MOSFET device is not shown, as indicated
with the wavy lines. Any isolation technique used in the art in the
fabrication of small devices, such as for instance, shallow trench
isolation (STI), is suitable for the purposes of the embodiments of
the present invention.
[0036] FIG. 1C gives selected MOSFET device parameters as the
function of structural parameters for preferred embodiments of the
present invention. The selected parameters of interest are the
MOSFET device threshold at saturation V.sub.t(sat), (given in units
of Volts), which is the threshold value when the drain is biased
high; and the drain-induced barrier lowering, DIBL (given in units
of milliVolts/Volts). The V.sub.t(sat) and DIBL values show that
preferred embodiments of the present invention result in useful
devices at such an ultra short gate length as 20 nm, or at even
shorter gate lengths.
[0037] FIG. 2 through FIG. 6 schematically show the fabrication
steps involved in the MOSFET devices and CMOS circuits of the
embodiments of the present invention.
[0038] FIG. 2 shows, in a schematic cross sectional view, a stage
in the processing of a 40 nm gate length MOSFET where a ground
plane 20 has been fabricated. The ground plane 20 is disposed over
a substrate 100. Typically, the substrate 100 may be a Si wafer,
SOI structure, SGOI structure, or an insulating layer, or an other
support structure known in the art. Providing such a suitable
substrate 100 may be the initial stage in the fabrication of the
MOSFET device. The ground plane 20 may be created by implanting
suitable dopant impurities into the substrate, followed by
annealing, possibly by rapid thermal means, or by laser means.
[0039] In alternate embodiments the ground plane 20 may be
epitaxially deposited over the monocrystalline substrate surface.
During such deposition the ground plane may be in-situ doped. The
meaning in the art of "in-situ doping" is that the doping
impurities are introduced during the growth process. Other suitable
means for creating the ground plane 20 are also known in the art,
for instance layer transfer, and such means may be used in
embodiments of the present invention. The ground plane 20 material
is a Si based semiconductor, such as SiGe, possibly alloyed with
further elements, such as C. In exemplary embodiments, the Si based
semiconductor of the ground plane is essentially pure Si.
[0040] FIG. 3 shows, in a schematic cross sectional view, a stage
in the processing of the MOSFET device where a counter doped body
layer 10 has been fabricated. In representative embodiments of the
invention a low temperature in-situ doped selective epitaxy process
is used to form the body layer 10. The temperature range of the
epitaxial process may be between about 500.degree. C. and
650.degree. C., and the doping range between about
1.times.10.sup.18/cm.sup.3 and 5.times.10.sup.19/cm.sup.3. A
preferred process for the epitaxial deposition of the body layer 10
may be UHV-CVD (ultra-high-vacuum chemical-vapor-deposition). Such
a deposition technique is described for instance in U.S. Pat. No.
5,906,680 to B. S. Meyerson, which is incorporated herein by
reference. The low temperature of the epitaxial deposition may
assure that the impurities in the ground plane 20 and those in the
body layer 10 do not inter-diffuse. For this reason, the transition
width across the ground plane/body layer interface 15 between the
first type and the second type of dopant impurities can be kept in
the range of about 2.5 nm to about 0.5 nm.
[0041] FIG. 4 shows, in a schematic cross sectional view, a stage
in the processing of the MOSFET device when a gate insulator 40 has
been disposed over the body layer 10, and the gate 30 has been
disposed over the gate insulator 40. The gate insulator 40 in
exemplary embodiments of the invention is fabricated by methods
known in the art. The gate insulator 40 may be grown, or deposited.
The gate insulator 40 may contain silicon dioxide, silicon
oxynitride, as well as, so called high-k materials. The gate
insulator 40 may also have a crystalline portion, as it may be
epitaxially grown over the body layer 10.
[0042] The fabrication may continue with the disposing of a metal
layer 30' with a mid-gap workfunction over the gate insulator 40.
Such metals are know in the art, they include W, Ta, TiN, and
others. Disposed over the metal layer 30' may be other material
layers that in combination with the metal layer 30' together form
the gate stack, or gate electrode 30.
[0043] It is understood that apart from the discussed fabrication
processes, a large number of additional steps may have to be
performed during the fabrication of the MOSFET devices. Such may
include, for instance, cleaning, etching, patterning, and other
steps, as it is known in the art. It is also understood that in the
case of fabricating CMOS circuits most of the processes outlined
here have to be done separately for both the NMOS and PMOS devices.
When one of the device types is being acted upon, the other type is
usually being covered by masking. However, this may not be the case
for disposing the mid-gap workfunction metal layer 30'. In
preferred CMOS circuit embodiments of the invention the NMOS and
PMOS devices may have an identical metal of mid-gap workfunction
disposed over their respective gate dielectrics, and possibly, but
not necessarily, during the same processing step.
[0044] FIG. 5 shows, in a schematic cross sectional view, a stage
in the processing of the MOSFET device where the gate has been
patterned. Such patterning may follow lithography techniques know
in the art. Typically, such a lithographic process defines the
final, less than 40 nm, gate length 80.
[0045] FIG. 6A and FIG. 6B show in a schematic cross sectional
view, stages of differing embodiments of the source/drain 50
processing.
[0046] Referring to FIG. 6A, the device after the gate patterning
may undergo steps known in the art, such as the sidewall spacer 70
formation on the sides of the gate electrode. In representative
embodiments of the present invention the source/drain formation
involves selective material deposition, thereby raising the
source/drain 50. The height of the source/drain protrusion may be
of about 25 nm. The raised source/drain then will be implanted 110
with the proper dopant impurity type, using an implant energy and
dose in such a manner that after an annealing procedure, which may
be a rapid thermal annealing, or a laser annealing process, the
source and drain junctions end up with a depth 84 which is less
than about 7 nm.
[0047] Referring to FIG. 6B, in alternate embodiments of the
invention a different approach may be employed to achieve shallow,
highly doped junctions. In this case, material is hollowed out in
the locations of the source/drain 50', and a selective deposition
is used to grow back the source/drain, resulting in the completion
of the embodiment as it is shown in FIG. 1B. During the growth
process the desired doping level is in-situ provided. The final
shallow, less than about 7 nm, junction depth may be reached by the
proper combination of the depth of the hollowing of the
source/drain regions 50', and the deposition process
parameters.
[0048] In preferred embodiments of the present invention the
processes of forming of the ground plane, depositing of the body
layer, forming of the gate insulator layer, forming of the gate,
may all be carried out in a UHV-CVD system, without the breaking of
the vacuum. A system capable for such a degree of integration has
been disclosed in U.S. Pat. No. 6,013,134 to J. Chu et al, which is
incorporated herein by reference. The integration of the
fabrication process, including maintaining vacuum in the deposition
system even between successive steps, may allow for the abrupt
interfaces and transitions practiced in embodiments of the present
invention. Such an abrupt transition is, for instance, the dopant
impurity type change across the ground plane/body layer interface
15, which transition is of between about 2.5 nm and 0.5 nm. The 0.5
nm width may represent a transition over about a single monolayer
of the crystal structure.
[0049] Many modifications and variations of the present invention
are possible in light of the above teachings, and could be apparent
for those skilled in the art. The scope of the invention is defined
by the appended claims.
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