U.S. patent application number 11/955627 was filed with the patent office on 2008-12-25 for system and method for estimating input power for a power processing circuit.
Invention is credited to Prashant Gugle, Chandrasekaran Jayaraman.
Application Number | 20080316779 11/955627 |
Document ID | / |
Family ID | 40135820 |
Filed Date | 2008-12-25 |
United States Patent
Application |
20080316779 |
Kind Code |
A1 |
Jayaraman; Chandrasekaran ;
et al. |
December 25, 2008 |
SYSTEM AND METHOD FOR ESTIMATING INPUT POWER FOR A POWER PROCESSING
CIRCUIT
Abstract
A controller for a power processing circuit and a related method
of operating the same. In one embodiment, the controller includes a
multiplier configured to produce a product of an input current and
an input voltage of the power processing circuit. The controller
also includes a low-pass filter configured to produce an input
power estimate of an input power to the power processing circuit as
a function of the product of the input current and the input
voltage. In another embodiment, the controller is a power-factor
controller and includes a voltage loop compensator configured to
produce a voltage compensation signal as a function of an output
voltage of the power processing circuit. The controller also
includes an input power estimator configured to produce an input
power estimate of an input power to the power processing circuit as
a function of the voltage compensation signal.
Inventors: |
Jayaraman; Chandrasekaran;
(Bangalore, IN) ; Gugle; Prashant; (Bangalore,
IN) |
Correspondence
Address: |
SLATER & MATSIL, L.L.P.
17950 PRESTON RD, SUITE 1000
DALLAS
TX
75252-5793
US
|
Family ID: |
40135820 |
Appl. No.: |
11/955627 |
Filed: |
December 13, 2007 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
60945024 |
Jun 19, 2007 |
|
|
|
Current U.S.
Class: |
363/74 ;
363/89 |
Current CPC
Class: |
Y02B 70/10 20130101;
Y02B 70/126 20130101; H02M 1/4225 20130101; G01R 21/133 20130101;
H02M 3/156 20130101 |
Class at
Publication: |
363/74 ;
363/89 |
International
Class: |
H02M 7/02 20060101
H02M007/02; H02M 7/155 20060101 H02M007/155 |
Claims
1. A controller for use with an electrical system, comprising: a
multiplier configured to produce a product of an input current and
an input voltage of said power processing circuit; and a low-pass
filter configured to produce an input power estimate of an input
power to said power processing circuit as a function of said
product of said input current and said input voltage.
2. The controller as recited in claim 1 further comprising a
conversion unit configured to perform a correction of said input
power estimate.
3. The controller as recited in claim 2 wherein said conversion
unit is calibrated over a range of power converter operating
conditions during a manufacturing step to improve accuracy of said
input power estimate.
4. The controller as recited in claim 1 wherein said multiplier and
said low-pass filter comprise a digital circuit.
5. The controller as recited in claim 1 wherein said input current
is a scaled, digitized input current of a boost power stage of said
power processing circuit and said input voltage is a scaled,
digitized input voltage.
6. The controller as recited in claim 1 further comprising a
pulse-width modulator configured to produce a signal to control a
duty cycle of a boost power switch in a boost power stage of said
power processing circuit.
7. The controller as recited in claim 1, further comprising: a
voltage loop compensator configured to produce a voltage
compensation signal as a function of a first error signal derived
from a scaled, digitized output voltage of a boost power stage of
said power processing subtracted from a reference output voltage; a
multiplier configured to produce a time-dependent current reference
signal as a function of a voltage feed-forward signal derived from
a scaled, digitized input voltage via a feedback circuit and said
voltage compensation signal; a summer configured to produce a
second error signal as a function of a current feedback signal
derived from a scaled, digitized inductor current of a boost power
stage of said power processing circuit and said time-dependent
current reference signal; a current loop compensator configured to
produce a current compensation signal from said second error
signal; and a pulse width modulator configured to produce a signal
to control a duty cycle of a boost power switch in said boost power
stage of said power processing circuit as a function of said
current compensation signal.
8. A method of operating a controller of a power processing
circuit, comprising: producing a product of an input current and an
input voltage of said power processing circuit with a multiplier;
and producing an input power estimate of an input power to said
power processing circuit as a function of said product of said
input current and said input voltage with a low-pass filter.
9. The method as recited in claim 8 further comprising performing a
correction of said input power estimate.
10. The method as recited in claim 9, further comprising
calibrating said correction of said input power estimate during a
manufacturing step to improve accuracy of said input power
estimate.
11. The method as recited in claim 8 wherein said multiplier and
said low-pass filter comprise a digital circuit.
12. The method as recited in claim 8 wherein said input current is
a scaled, digitized inductor current of a boost power stage of said
power processing circuit and said input voltage is a scaled,
digitized input voltage.
13. The method as recited in claim 8 further comprising producing a
signal to control a duty cycle of a boost power switch in a boost
power stage of said power processing circuit.
14. The method as recited in claim 8, further comprising: producing
a voltage compensation signal as a function of a first error signal
derived from a scaled, digitized output voltage of a boost power
stage of said power processing subtracted from a reference output
voltage; producing a time-dependent current reference signal as a
function of a voltage feed-forward signal derived from a scaled,
digitized input voltage and said voltage compensation signal;
producing a second error signal as a function of a current feedback
signal derived from a scaled, digitized inductor current of a boost
power stage of said power processing circuit and said
time-dependent current reference signal; producing a current
compensation signal from said second error signal; and producing a
signal to control a duty cycle of a boost power switch in said
boost power stage of said power processing circuit as a function of
said current compensation signal.
15. A power converter, comprising: a boost power stage including a
boost power switch configured to receive an input power with an
input current and input voltage; and a controller, including: a
multiplier configured to produce a product of said input current
and said input voltage, and a low-pass filter configured to produce
an input power estimate of said input power as a function of said
product of said input current and said input voltage.
16. The power converter as recited in claim 15 wherein said
controller further includes a conversion circuit configured to
perform a correction of said input power estimate.
17. The power converter as recited in claim 15 wherein said
multiplier and said low-pass filter comprise a digital circuit.
18. The power converter as recited in claim 15 wherein said input
current is a scaled, digitized inductor current of said boost power
stage and said input voltage is a scaled, digitized input
voltage.
19. The power converter as recited in claim 15 wherein said input
power estimate is provided to an external system through a
communications means.
20. The power converter as recited in claim 15 wherein said
controller, further includes: a voltage loop compensator configured
to produce a voltage compensation signal as a function of a first
error signal derived from a scaled, digitized output voltage of
said boost power stage subtracted from a reference output voltage;
a multiplier configured to produce a time-dependent current
reference signal as a function of a voltage feed-forward signal
derived from a scaled, digitized input voltage via a feedback
circuit and said voltage compensation signal; a summer configured
to produce a second error signal as a function of a current
feedback signal derived from a scaled, digitized inductor current
of said boost power stage and said time-dependent current reference
signal; a current loop compensator configured to produce a current
compensation signal from said second error signal; and a pulse
width modulator configured to produce a signal to control a duty
cycle of said boost power switch as a function of said current
compensation signal.
Description
[0001] This application claims the benefit of U.S. Provisional
Application No. 60/945,024, entitled "System and Method for
Estimating Input Power by Filtering an Instantaneous
Voltage-Current Product," filed on Jun. 19, 2007, which is
incorporated herein by reference.
TECHNICAL FIELD
[0002] The present invention is directed, in general, to electronic
power conversion and, more specifically, to a controller adapted to
estimate an average input power to a power processing circuit, and
method of operating the same.
BACKGROUND
[0003] A switch-mode power converter (also referred to as a "power
converter") is a power supply or power processing circuit that
converts an input voltage waveform, such as an ac input voltage
waveform, into a specified output voltage waveform, such as a dc
output voltage waveform. Controllers associated with the power
converters manage an operation thereof by controlling the
conduction periods of power switches employed therein. Generally,
the controllers are coupled between an input and output of the
power converter in a feedback loop configuration.
[0004] Typically, the controller measures an internal operating
characteristic (e.g., an internal bus voltage) or an output
characteristic, (e.g., an output voltage or an output current)
representing an operating condition of the power converter, and
based thereon modifies a duty cycle of a power switch or power
switches of the power converter to regulate an internal operating
characteristic or the output characteristic. The duty cycle is a
ratio represented by a conduction period of a power switch to a
switching period thereof. Thus, if a power switch conducts for half
of the switching period, the duty cycle for the power switch would
be 0.5 (or 50 percent). Additionally, as the needs for systems such
as a microprocessor powered by the power converter dynamically
change (e.g., as a computational load on the microprocessor
changes), the controller should be configured to dynamically
increase or decrease the duty cycle of the power switches therein
to regulate the internal or the output characteristic at a desired
value. In an exemplary application, the power converters have the
capability to convert an unregulated ac input voltage, such as a
nominal 240 volts ac, to a regulated, dc output voltage such as 400
volts, to power a load, which may include a further stage of power
conversion, such as a dc-to-dc converter.
[0005] A new consideration for the design of a power converter in
certain applications is the need for the power converter to
estimate accurately an input power thereto averaged over a period
of the input waveform, with an accuracy of, for instance, a few
percent. The power converter may communicate the input power
estimate to a system external to the power converter. Hence, there
is a need to incorporate such input power estimation capability
into a power converter.
[0006] The need to estimate accurately an input power to a power
converter is a parallel need to the general objective to reduce
energy consumed by an electronic system, for example as described
in the U.S. patent application CDW-011CP1, filed Feb. 23, 2007,
Ser. No. 11/710,276, entitled "Power System with Power Converters
Having an Adaptive Controller" and U.S. patent application
CDW-011CP1CP1P1, filed Mar. 19, 2007, Ser. No. 60/918,806, entitled
"Power System States", which are incorporated herein by
reference.
[0007] Power converter designers in the past have inadequately
responded to this new design requirement. A particular technique
that has been used to estimate input power averaged over an input
voltage waveform includes sensing instantaneous input current and
voltage to the power converter and forming an integral over a cycle
of the input voltage waveform of a product of the instantaneous
input current and voltage. This approach can entail a substantial
amount of added signal processing, particularly when implemented
with digital circuit elements. The allocation of a digital resource
in a high-performance, cost competitive application may be made on
a priority basis in view of the basic control needs of the power
converter, and may reluctantly be used as an auxiliary
computation-intensive task such as estimation of power converter
input power by integrating a product of waveforms. Producing an
accurate estimate of input power to a power converter, particularly
in a digital control application, without consuming valuable
additional computing resources can have immediate effects on the
applicability and marketplace acceptance of a particular power
converter design
[0008] A controller for a power processing circuit is presently not
available that estimates input power without substantial signal
processing overhead. Accordingly, what is needed in the art is a
controller for a power processing circuit that can provide an
estimate of the input power without consuming substantial signal
processing resources.
SUMMARY OF THE INVENTION
[0009] These and other problems are generally solved or
circumvented, and technical advantages are generally achieved, by
advantageous embodiments of the present invention that include a
controller for a power processing circuit. In one embodiment, the
controller includes a multiplier configured to produce a product of
an input current and an input voltage of the power processing
circuit. The controller also includes a low-pass filter configured
to produce an input power estimate of an input power to the power
processing circuit as a function of the product of the input
current and the input voltage.
[0010] In another embodiment, the controller includes a voltage
loop compensator configured to produce a voltage compensation
signal as a function of an output voltage of the power processing
circuit. The controller also includes an input power estimator
configured to produce an input power estimate of an input power to
the power processing circuit as a function of the voltage
compensation signal.
[0011] In a further embodiment, the controller including the power
estimator is part of a redundant or non-redundant power converter
system providing electrical power to a system external to the power
converter. The external system may comprise a data processing
system such as a server, a storage system, a data packet router, or
any system requiring electrical power where an accurate input power
estimate would be advantageous. The controller is configured to
provide the input power estimate to the external system through a
communications means, including but not limited to I.sup.2C,
Ethernet, an SPI bus, or any other suitable electronic
communications medium or protocol. The external system may command
the controller to provide the input power estimate, or conversely,
the controller may provide the input power estimate to the external
system as part of a scheduled information transfer.
[0012] The foregoing has outlined rather broadly the features and
technical advantages of the present invention in order that the
detailed description of the invention that follows may be better
understood. Additional features and advantages of the invention
will be described hereinafter which form the subject of the claims
of the invention. It should be appreciated by those skilled in the
art that the conception and specific embodiment disclosed may be
readily utilized as a basis for modifying or designing other
structures or processes for carrying out the same purposes of the
present invention. It should also be realized by those skilled in
the art that such equivalent constructions do not depart from the
spirit and scope of the invention as set forth in the appended
claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] For a more complete understanding of the present invention
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0014] FIG. 1 illustrates a simplified schematic diagram of an
embodiment of a power processing circuit including a controller
constructed according to the principles of the invention;
[0015] FIG. 2 illustrates a block diagram of an embodiment of a
controller employable in a power processing circuit constructed
according to the principles of the invention;
[0016] FIGS. 3 and 4 illustrate block diagrams of further
embodiments of a controller employable in the power processing
circuit constructed according to the principles of the
invention;
[0017] FIG. 5 illustrates numerically generated waveforms for
rectified input voltage and inductor current for two cycles of the
ac input voltage employed in a simulation in accordance with a
power converter employing the controller of FIG. 2;
[0018] FIG. 6 illustrates a waveform of an input power estimate
with respect to time in accordance with the controller of FIG.
2;
[0019] FIG. 7 illustrates a waveform of two cycles of an exemplary
ac input voltage and a corresponding exemplary rectified ac input
voltage produced in a simulation in accordance with a power
converter employing the controller of FIG. 3;
[0020] FIG. 8 illustrates a waveform of a variation of percentage
error of an estimated input power with respect to various input
line conditions in a simulation in accordance with a power
converter employing the controller of FIG. 3;
[0021] FIG. 9 illustrates waveforms of a percentage error of an
estimated input power versus a measured input power obtained
experimentally in accordance with a power converter employing the
controller of FIG. 2;
[0022] FIG. 10 illustrates waveforms of a percentage error of an
estimated input power versus a measured input power obtained
experimentally in accordance with a power converter employing the
controller of FIG. 3; and
[0023] FIG. 11 illustrates a block diagram of an embodiment of a
power system coupled to loads and including power converters
controlled by a power system controller, constructed according to
the principles of the invention.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0024] The making and using of the presently preferred embodiments
are discussed in detail below. It should be appreciated, however,
that the present invention provides many applicable inventive
concepts that can be embodied in a wide variety of specific
contexts. The specific embodiments discussed are merely
illustrative of specific ways to make and use the invention, and do
not limit the scope of the invention.
[0025] The present invention will be described with respect to
exemplary embodiments in a specific context, namely, a controller
configured to estimate an input power to a power processing circuit
coupleable to an ac power source. In an exemplary embodiment, a
power processing circuit is a power converter coupled to an ac
power source including a controller configured to estimate an input
power thereto.
[0026] For a power processing circuit such as a power converter
operating from ac input mains, the integration of a product of
instantaneous input voltage and current over a time interval from a
time t1 to t2 gives the total energy consumed in that time
interval. For a power processing circuit whose input voltage and
current are periodic, if the fundamental frequencies of the voltage
and current are the same, then the integration of the product of
instantaneous voltage and current over one fundamental cycle of the
ac input power gives the energy consumed in one cycle. Hence,
dividing the above integral by the time period gives power drawn by
the power processing circuit. For a periodic function, integration
over one cycle divided by the time period gives the average value
of that function.
[0027] Alternatively, the average value of a signal can be
obtained, or constructed, according to the principles of the
invention by using a low-pass filter. Filtering the instantaneous
product of a voltage and current with a low-pass filter such that
the fundamental and harmonic frequency components thereof are
substantially attenuated gives the average power drawn by the power
processing circuit. It can be noted that filtering an instantaneous
product of voltage and current is a method of estimating power,
which can be applied for any electrical system having input voltage
and current that are periodic in nature.
[0028] Turning now to FIG. 1, illustrated is a simplified schematic
diagram of an embodiment of a power processing circuit (e.g., a
power converter) 100 including a controller 102 constructed
according to the principles of the invention. The power converter
includes a boost power stage 101 that may be configured to perform
power factor correction, and a bypass path 103 comprising diode D6.
An input power source 104 to the boost power stage 101 is an ac
power source, which is coupled to a diode bridge rectifier
comprising diodes D1, D2, D3, and D4 through EMI filter 106. The
boost power stage 101, controlled by controller 102, produces a
regulated output voltage V.sub.out across an output filter
capacitor C1, which provides the output voltage V.sub.out to a
load, represented by resistor R1.
[0029] The boost power stage 101 includes a boost power switch
Q.sub.boost and diode D5, which alternately conduct to transfer
power from the input power source 104 through an inductor L1 to the
output filter capacitor C1. The controller 102 senses the output
voltage V.sub.out, the rectified input voltage V.sub.rect, and
bridge rectified current i.sub.rect to produce a signal D to
control a duty cycle of the boost power switch Q.sub.boost, thereby
regulating the output voltage V.sub.out and the power factor of
power drawn from the input power source 104. In this condition,
bypass diode D6 would be reverse biased and hence the bypass
current i.sub.bypass would be equal to zero and the bridge
rectified current i.sub.rect would be equal to the inductor current
i.sub.L. The power converter 100 includes an electromagnetic
interference ("EMI") filter 106 to reduce high-frequency conducted
noise fed back to the input power source 104.
[0030] The bypass path 103 includes bypass diode D6 which would
peak charge the output voltage V.sub.out, in an unregulated
fashion, when, for example, the control duty cycle D to the boost
power switch Q.sub.boost is set to zero. In this condition, the
inductor current i.sub.L would be equal to zero and the bridge
rectified current i.sub.rect would be equal to the bypass current
i.sub.bypass.
[0031] Turning now to FIG. 2, illustrated is a block diagram of an
embodiment of a controller 200 employable in a power processing
circuit (e.g., a power converter) constructed according to the
principles of the invention. In an advantageous embodiment, the
controller is implemented with a digital controller. The controller
200 is coupled to a boost power stage powered from an input power
source, both of which were illustrated and described with reference
to FIG. 1. An output voltage V.sub.out from the boost power stage
is fed back in signal processing path or outer voltage loop 240
with a sensing gain k.sub.dc to an analog to digital converter
(designated "ADC"), producing feedback signal
V.sub.out.sub.--.sub.fb (e.g., a scaled, digitized output voltage),
which is subtracted from a reference output voltage
V.sub.out.sub.--.sub.ref in summer 204 to produce a first error
signal E1. The first error signal E1 is coupled to a voltage loop
compensator 206 that produces a voltage compensation signal V.sub.c
therefrom provided to a multiplier 208. The voltage compensator may
advantageously comprise a PI ("proportional-integral") compensator
cascaded with a high frequency pole.
[0032] The rectified input voltage V.sub.rect to the boost power
stage is sensed in a signal processing path or voltage feed-forward
loop 244 with sensing gain k.sub.ac, converted to signal
V.sub.in.sub.--.sub.sp in digital format (e.g., a scaled, digitized
input voltage) by an ADC. This signal is coupled to a second input
of the multiplier 208. The signal V.sub.in.sub.--.sub.sp is also
coupled to an input of a feedforward circuit. The feedforward
circuit filters the scaled, digitized input voltage
V.sub.in.sub.--.sub.sp in low-pass filter ("LPF") 230, squares the
filtered scaled, digitized input voltage V.sub.in.sub.--.sub.sp in
squarer 232, the result of which is inverted in inverter 234. The
result of the feedforward circuit is illustrated in FIG. 2 as a
voltage feed-forward signal V_ff, and is coupled to a third input
of the multiplier 208. An output signal from the multiplier 208 is
a time-dependent current reference signal I.sub.ref(t), which sets
a desired current waveform for an inductor in the boost power
stage.
[0033] The controller 200 senses a bridge rectified current
i.sub.rect in a signal processing path or inner current loop 242
with sensing gain k.sub.c, which is coupled to an ADC, producing
current feedback signal I_fdbk (e.g., a scaled, digitized bridge
rectified current). The current feedback signal I_fdbk is
subtracted from the time-dependent current reference signal
I.sub.ref(t) of the multiplier 208 in a summer 212. The result of
this subtraction (e.g., a second error signal E2) is coupled to a
current loop compensator 214 that produces a current compensation
signal I.sub.c that is provided to a pulse-width modulator ("PWM")
216. The pulse-width modulator 216 produces a signal D to control
duty cycle of a boost power switch in the boost power stage that
was illustrated and described with reference to FIG. 1. The current
loop compensator may advantageously comprise a PI compensator
cascaded with a lead compensator.
[0034] The bandwidth of the outer voltage loop 240 is typically
around five hertz ("Hz"), and the bandwidth of the inner current
loop 242 is typically around five kilohertz ("kHz"). Other
bandwidths may be used depending on system requirements. The
voltage feed-forward loop 244 is implemented to improve the line
transient performance of a power converter.
[0035] To achieve less total harmonic distortion in the input
current and high power factor, the sampling frequency of the scaled
rectified input voltage V.sub.rect is chosen to be large enough
(preferably 10 kHz or higher in many applications) to reconstruct
the rectified input voltage V.sub.rect with little distortion.
Similarly, the sampling rate of the bridge rectified current
i.sub.rect is done at least at the switching frequency of a boost
power switch of the boost power stage, which typically is of the
order of 100 kHz or higher in recent commercial product
designs.
[0036] Additionally, the scaled, digitized input voltage signal
V.sub.in.sub.--.sub.sp (indicative of the rectified input voltage
V.sub.rect or the input voltage to the power converter) from the
ADC and the current feedback signal I_fdbk (indicative of the
bridge rectified current i.sub.rect), are multiplied in a
multiplier 252 (to produce a product of the input voltage and input
current), for example at a 10 kHz rate, and are fed into a low-pass
filter 254. The low-pass filter 254 may be implemented with a
frequency response shaped so that the fundamental and higher
harmonic frequencies of the rectified ac line voltage are
substantially reduced. Low-pass filters with a desired frequency
response can be readily implemented using design procedures well
known in the art. A series of cascaded low-pass filters can also be
used as necessary to achieve an attenuation level for harmonic
components. Since both an input voltage and an input current of a
boost power stage are available in digital format at a high
sampling rate, for instance, in the controller illustrated in FIG.
2, the active power drawn by the boost power stage can be
accurately estimated.
[0037] In an advantageous embodiment, a two-stage, cascaded,
low-pass filter is implemented, without limitation, in a "C"
computer language, each stage with a corner frequency at 12 Hz and
with a computational repetition rate of 10 kHz. The representation
and implementation of a low-pass filter in a computer language such
as C is well known in the art, and will not be described here
further in the interest of brevity. Of course, other filter
structures, such as cascaded band stop filters to remove the higher
order harmonics, may be used.
[0038] A filter output signal F.sub.s represents a quantity that is
a measure of the average input power to a boost power stage. In an
ideal case when the filter output signal F.sub.s is multiplied by a
conversion factor, m, an estimate of average input power, in watts
for example, is thereby produced. However, due to non-idealities in
sensing circuits, for instance, when an additive but unknown bias
current is present in a sense circuit or, as is typically the case,
an operational amplifier exhibits a small but unknown offset
voltage or a component deviates from a nominal value by tolerance,
etc., or due to non-idealities in digital computation, for example,
errors introduced due to truncation and round-off, deviations are
unavoidably introduced between an actual and an estimated value of
average input power.
[0039] To improve accuracy of the estimated value of average input
power, in an advantageous embodiment, a linear or higher-order
fitting equation, e.g., a linear equation of the form mx+c, where
"m" and "c" are fitting constants and "x" is an independent
variable, may be used for the conversion represented in a
conversion circuit 258. The parameters of the fitting equation,
e.g., m and c, can be determined for a given power converter during
a calibration process by comparing estimated power with an actual
average input power measurement, preferably in a controlled
environment, using calibration processes well-known in the art.
Fitting equations can also be used for variations with respect to
input line voltage, an operating temperature, etc.
[0040] It is noted that any error in generating the bridge
rectified current i.sub.rect and the scaled, digitized input
voltage signal V.sub.in.sub.--.sub.sp, which are the inputs to the
multiplier 252, would lead to an error in the estimated power.
Hence, to improve the accuracy over wide input voltage and load
conditions, calibration can also be done individually for these
parameters. In such cases, it would be preferable to carry out a
calibration of the input power after completing the calibration of
the individual parameters, such as the bridge rectified current
i.sub.rect and digitized input voltage signal
V.sub.in.sub.--.sub.sp.
[0041] As the bridge rectified current i.sub.rect is used, the
power estimator works well for both the conditions when the power
processing is done by the boost power stage 101 regulating the
output voltage V.sub.out, as well as when the boost power stage 101
is switched off, whereby the output voltage V.sub.out is peak
charged in a unregulated fashion through the bypass path 103. In
the latter case, since the bridge rectified current i.sub.rect
would be peaky in nature and since the controller 102 would have a
lower computational load (as no processing is required to control
the boost power stage 101), the sampling and the computational
rates to estimate the input power can be increased to closely track
the peak-natured current, and thereby accurately estimate the input
power. Calibration may be done for this mode of operation to
improve accuracy further.
[0042] Thus, a process to estimate average input power for a power
processing circuit that may be coupled to an ac (or a dc) input
power source has been introduced that processes a product of an
input voltage times an input current to a power processing circuit
with a filter (preferably a low-pass filter). The process avoids
the need to form an integral of a product of an instantaneous input
current and voltage over a cycle of an input voltage waveform,
thereby avoiding the need for substantial computing resources to
make an average input power estimate.
[0043] In the Designer Reference Manual from Freescale
Semiconductor, Inc., entitled "Design of a Digital AC/DC SMPS Using
the 56F8323 Device," (2005), in Section 5.2.2 (equation 5.5)
therein, it was shown that for a sinusoidal input voltage to a
power converter, the voltage compensation signal V.sub.c of the
voltage loop compensator 306 is proportional to the input power
drawn by a boost power stage controlled with power-factor
correction. The relationship between the input power drawn by the
boost power stage and the output signal of the voltage loop
compensator for input voltages having harmonic content up to,
without limitation, the 11.sup.th harmonic of the input ac voltage
and total harmonic distortion less than, without limitation, ten
percent is numerically established as described herein.
[0044] Turning now to FIG. 3, illustrated is a block diagram of
another embodiment of a controller 300 employable in the power
processing circuit (e.g., a power converter) constructed according
to the principles of the invention. A difference between the
feedback circuit of the controllers described in FIG. 2 and FIG. 3
is that the signal-processing order of a squaring function 332 and
a low-pass filter 330 has been inverted before generating a voltage
feed-forward signal V_ff. The average input power estimating
process described previously herein would not be affected by this
modification, but is preferable for the process as described below.
Remaining elements in FIG. 3 and in following figures that are
similar to similarly numbered elements in a previous figure and
will not be described in the interest of brevity.
[0045] A signal that is proportional to the mean-square value of
the rectified input voltage V.sub.rect may be provided by squaring
the V.sub.in.sub.--.sub.sp signal (a scaled, digitized rectified
input voltage) and coupling the squared result to a low-pass filter
330 with a corner frequency that substantially attenuates the
fundamental of the line frequency and higher harmonic frequency
components. Thus, the controller described in FIG. 3 generates a
voltage feed-forward signal V_ff that is inversely proportional to
the mean-square value of the rectified input voltage
V.sub.rect.
[0046] Hence, from the structure illustrated in FIG. 3, the
time-dependent current reference signal I.sub.ref(t) applied within
the controller (i.e., the signal applied to the non-inverting input
of an summer 312) can be written as EQN 1:
I.sub.ref(t)=V.sub.c
V.sub.rect(t)/(V.sub.rms.sup.2k.sub.ack.sub.adck.sub.lpf),
wherein k.sub.adc represent the signal processing gain of the ADC
that provides the scaled, digitized input voltage signal.
V.sub.in.sub.--.sub.sp, k.sub.lpf represents gain of the low-pass
filter 330, and V.sub.rms.sup.2 represents the square of the RMS
value of the rectified input voltage V.sub.rect. The voltage
compensation signal V.sub.c represents the output of the voltage
loop compensator 306. The boost power stage inductor current
i.sub.L (which is same as the bridge rectified current i.sub.rect
when the controller 102 is regulating the output voltage V.sub.out,
as previously discussed) in response to the inner current loop 342,
can be determined as set forth in EQN 2:
i.sub.L(t)=G(V.sub.cV.sub.rect(t)/(V.sub.rms.sup.2k.sub.ack.sub.adck.sub-
.lpf)),
wherein the function G( ) represents the response of the inner
current loop 342. At a steady-state condition, the average input
power and the RMS input voltage are constant, and hence EQN 2 can
be written as EQN 3:
i.sub.L(t)=[V.sub.c/(V.sub.rms.sup.2k.sub.ack.sub.adck.sub.lpf)]G((V.sub-
.rect(t)).
[0047] The instantaneous input power P.sub.in(t) to the power
converter can be written as EQN 4:
P.sub.in(t)=V.sub.rect(t)i.sub.L(t)
Substituting EQN 3 into EQN 4 produces EQN 5:
P.sub.in(t)=[V.sub.c/(V.sub.rms.sup.2k.sub.ack.sub.adck.sub.lpf)]G(V.sub-
.rect(t))V.sub.rect(t).
[0048] The average input power P.sub.dc to the boost power stage
can be obtained by integrating EQN 5 over one cycle of the ac input
waveform to produce EQN 6:
P dc = ( 1 T ) V c V rm s 2 k ac k adc k lpf .intg. V rect ( t ) G
( V rect ( t ) ) t ##EQU00001## P dc = [ V c k ac k adc k lpf ]
.lamda. ##EQU00001.2##
wherein as set forth in EQN 7:
.lamda. = 1 T V rm s 2 .intg. G ( V rect ( t ) ) V rect ( t ) t .
##EQU00002##
[0049] In EQN 6, all factors except .lamda. are known. Hence the
equation to estimate the average input power can be written,
neglecting the factor .lamda., as EQN 8:
P.sub.est=V.sub.c/(k.sub.ack.sub.adck.sub.lpf).
Thus, from EQN 8 it can be seen that the voltage compensator output
V.sub.c is a measure of the average input power to a boost power
stage. In an ideal case when the signal V.sub.c is multiplied by a
conversion factor, m, an estimate of average input power, in watts
for example, is thereby produced with a percentage error between
the actual and the estimate given by the EQN 9.
% _Error = 100 ( P dc - P est ) / P dc = 100 ( .lamda. - 1 ) /
.lamda. . ##EQU00003##
[0050] The value of .lamda. was numerically estimated to be quite
close to unity, and the corresponding percentage error was
estimated to be less than 0.15 percent for input voltage having
harmonic content up to 11.sup.th harmonic and total harmonic
distortion less than 10 percent. Hence, the input power can be
accurately estimated using an ideal estimator where the signal
V.sub.c is multiplied by a conversion factor, m, to get an estimate
of average input power.
[0051] To minimize the error introduced due to non-idealities in
the system, and to improve the accuracy of the estimated value of
average input power, in an advantageous embodiment, a linear or
higher-order fitting equation can be used for the power estimator
350, and the parameters therein can be calibrated.
[0052] Turning now to FIG. 4, illustrated is a block diagram of a
further embodiment of a controller 400 employable in a power
processing circuit (e.g., a power converter) constructed according
to the principles of the invention. Differences between the
controllers described in FIGS. 3 and 4 are as follows: First, a
reference rectified sine wave, V.sub.sine(t), of fixed amplitude,
generated from a signal generator 410 that is phase-locked with the
rectified input voltage signal V.sub.inst.sub.--.sub.sp using a
phase-locked loop (PLL) 409, is used as one of the inputs to the
multiplier 408, instead of the V.sub.inst.sub.--.sub.sp signal as
illustrated in FIG. 3. Second, a modification in the feedforward
path 444, wherein the inversion block 434 does the inversion of the
square-root of the signal fed from the LPF 430 instead of the
simple inversion as illustrated in FIG. 3. It can be shown that the
output V.sub.c of voltage loop compensator 406 is a measure of the
average input power to a boost power stage. In an ideal case when
the signal V.sub.c is multiplied by a conversion factor, m, as
illustrated in block 450, an estimate of average input power, in
watts, for example, can be obtained, similar to the case discussed
with reference to FIG. 3. Again, a linear or higher order
conversion unit can be used, and the parameters of the same can be
calibrated to improve the accuracy of power estimation.
[0053] The first power estimation process introduced above with
respect to FIG. 2 to estimate average input power, without
limitation, for a boost power stage that may or may not be
controlled with power-factor correction, using a low-pass filter to
filter a product of instantaneous voltage and current may be
numerically verified using a MathCad.TM. spreadsheet. Arbitrary
voltage and current waveforms, each with fundamental frequencies of
100 Hz, may be numerically generated for 100 cycles of the ac input
waveform.
[0054] Turning now to FIG. 5, illustrated are numerically generated
waveforms for rectified input voltage V.sub.rect and inductor
current i.sub.L for two cycles of the ac input voltage employed in
a simulation in accordance with a power converter employing the
controller of FIG. 2. Input power is calculated by integrating the
instantaneous product of input voltage and inductor current
numerically over one ac input voltage waveform cycle. Input power
is also calculated numerically by filtering the product of the
voltage and current samples for 100 ac input voltage waveform
cycles using a two-stage, cascaded, low-pass filter, each with a
corner frequency at 12 Hz. FIG. 6 illustrates a waveform of an
input power estimate P.sub.est with respect to time in accordance
with the controller illustrated and described with respect to FIG.
2.
[0055] The steady state value of the filtered output may be
compared with the numerical integration method and found that the
percentage error is insignificant. Thus, a process as introduced
above that uses a low-pass filter to filter a product of
instantaneous voltage and current can advantageously produce an
accurate estimate of input power for a boost power stage.
[0056] Regarding the controller illustrated and described with
respect to FIG. 3, the value of the parameter .lamda. and the
percentage error introduced due to assuming its value is unity may
be estimated using MathCad.TM. for different ac line harmonic
conditions. The ac input voltage waveform in the time domain with a
selected amount of harmonic content is numerically generated. The
rectified input ac line voltage is generated by taking the absolute
value of the ac input voltage waveform. FIG. 7 illustrates a
waveform of two cycles of an exemplary ac input voltage 701 and a
corresponding exemplary rectified ac input voltage 702 (which
coincides with the ac input voltage for portions of a cycle and
thus hides portions thereof) produced in a simulation in accordance
with a power converter employing the controller of FIG. 3. The
waveform of FIG. 7 provides the fundamental component of the ac
input voltage equal to 100 volts ("V") and the amplitude of the
third harmonic equal to 10 V, with no phase shift relative to the
fundamental component.
[0057] The inner current loop 342 illustrated in FIG. 3 may be
modeled in MathCad.TM. as a first-order system with a corner
frequency at two kHz. The function G(V.sub.rect(S)) may be obtained
by calculating the response of the inner current loop 342 loop to
the Fast Fourier Transform ("FFT") of the rectified input voltage
V.sub.rect(S), where the symbol "s" represents the complex argument
of the respective transformed function in the frequency domain. The
function G(V.sub.rect(t)) is obtained by taking the inverse FFT of
G(V.sub.rect(S)). Then the value of .lamda. was calculated by
integrating EQN 7 numerically, and the corresponding percent error
"%_error" is calculated using EQN 9.
[0058] The result obtained for different values of harmonic content
in the ac input voltage waveform is tabulated below in TABLE I for
15 exemplary cases ("Cond. No."). In each case, the amplitude of
the fundamental component of the ac input voltage waveform is 100
V. The amplitudes of the third, fifth, seventh, ninth, and eleventh
harmonic components are as tabulated. The angle associated with
various harmonic components shown in TABLE I is the phase angle of
the harmonic waveform at the zero crossings of the fundamental
component of the waveform. The values of total harmonic distortion
V.sub.thd shown in the second-rightmost column of TABLE I is an
approximate value for illustrative purpose only. The percentage
error ("error (%)") of the estimated input power to the boost power
stage is shown in the rightmost column of TABLE I.
TABLE-US-00001 TABLE I Harmonic Value (in V.sub.rms) @ angle (deg.)
Cond. No. 1.sup.st 3.sup.rd 5.sup.th 7.sup.th 9.sup.th 11.sup.th
V.sub.thd (%) Error (%) 1 100 0 0 0 0 0 0 -0.085 2 100 10 @ 0 0 0 0
0 10 -0.089 3 100 10 @ 45 0 0 0 0 10 -0.089 4 100 10 @ 90 0 0 0 0
10 -0.09 5 100 10 @ 135 0 0 0 0 10 -0.09 6 100 10 @ 180 0 0 0 0 10
-0.091 7 100 10 @ 270 0 0 0 0 10 -0.09 8 100 10 @ 315 0 0 0 0 10
-0.089 9 100 0 10 @ 45 0 0 0 10 -0.098 10 100 0 0 10 @ 270 0 0 10
-0.112 11 100 0 0 0 10 @ 90 0 10 -0.129 12 100 0 0 0 0 10 @ 315 10
-0.149 13 100 5 @ 0 5 @ 0 5 @ 0 5 @ 0 0 10 -0.102 14 100 0 5 @ 0 5
@ 0 5 @ 0 5 @ 0 10 -0.114 15 100 8 @ 0 7 @ 180 0 0 0 10 -0.096
[0059] Turning now to FIG. 8, illustrated is a plot of a variation
of percentage error ("error (%)") of an estimated input power in
accordance with a power converter employing the controller of FIG.
3. The percentage error of the estimated input power is provided
with respect to the input ac line condition. It is evident in FIG.
8 that the percentage error introduced due to assuming a unity
value for the factor .lamda. may be considered insignificant.
[0060] An experimental setup may be constructed using a 650-watt
power converter to validate the input power estimation processes
introduced herein. The power converter included a power-factor
corrected, single-phase, boost power stage drawing power from an ac
line. The output of the boost power stage was converted to 12 V by
an isolated, dc-dc power converter. The controller for the boost
power stage may be realized using a digital controller, similar to
one illustrated and described previously hereinabove.
[0061] A microcontroller may be used on the secondary side of the
power converter to provide an interface with an external system
(such as a server or storage processor) for supervisory activities.
In addition, a universal asynchronous receiver transmitter ("UART")
communication link (or any other suitable communication link) may
be provided between the digital controller on the primary side of
the isolation boundary of the dc-to-dc section and the
microcontroller on the secondary side of the isolation boundary.
The estimated power calculated by the digital controller may be
monitored by an external system via the above-mentioned
communication link. The communication update rate through the UART
communication link may be about every ten milliseconds ("ms"),
depending on the requirements of the external system. Voltages and
currents in the aforementioned setup are measured using typical
laboratory procedures.
[0062] In a mass production application, it may be advantageous to
calibrate the controller at some point during the manufacturing
process, perhaps during a test process using automated test
equipment (ATE). With continuing reference to the controller of
FIGS. 2, 3, and 4, the fitting parameters m and c used to calculate
the estimated input power may be calibrated at 20 amperes ("A") and
40 A of load current, at an ac input voltage of 110 V with zero
total harmonic distortion ("THD"), and with a line frequency of 60
Hz, for example, The ATE may then communicate appropriate
calibration parameters for m and c to the controller, allowing the
controller to use the stored calibration parameters to improve the
accuracy of an estimated input power. The calibration process may
be carried out for multiple operating points to improve overall
accuracy, for example, at multiple ac input line frequencies,
multiple line voltages, multiple harmonic distortion contents, and
multiple output power levels.
[0063] As a further example, the input voltage may be set at three
different line conditions. The first is a substantially pure sine
wave of 110 V. The second is a fundamental component of 110 V plus
a third harmonic of 11 V at zero degrees relative to the
fundamental. The third is a fundamental component of 110 V plus a
ninth harmonic of 11 V at zero degrees relative to the
fundamental.
[0064] Turning now to FIG. 9, illustrated are plots of a percentage
error of an estimated input power versus a measured input power in
accordance with a power converter employing the controller of FIG.
2. More specifically, the illustrated plots provide the percentage
error for the input power estimate for a process in which a
low-pass filter filters a product of an input voltage times an
input current to the power converter.
[0065] Turning now to FIG. 10, illustrated are plots of a
percentage error of an estimated input power versus a measured
input power in accordance with a power converter employing the
controller of FIG. 3. More specifically, the illustrated plots
provide the percentage error for the input power estimate for a
process in which a voltage compensation signal of a voltage loop
compensator is scaled by gains and processed by an input power
estimator. It is evident from the plots of FIGS. 9 and 10 that
errors in the input power estimate are well within a .+-.2% error
band for a wide range of load and input voltage harmonic
conditions.
[0066] It has thus been shown that the input active power drawn by
a power converter can be accurately estimated, for example, with
accuracy better than .+-.2%, with a process that advantageously
employs a modest expenditure of signal-processing resources. The
input power in accordance with a power converter can be estimated
by filtering the integrated value of a product of instantaneous
voltage and current with a low-pass filter. Alternatively, the
input power in a power converter can be estimated by scaling a
voltage compensation signal of a voltage loop compensator processed
by an input power estimator.
[0067] Turning now to FIG. 11, illustrated is a block diagram of an
embodiment of a power system, 1100, coupled to loads, including
power converters controlled by a power system controller
(designated "PSC"), constructed according to the principles of the
invention. The power system is operable in a plurality of
operational states, each with an associated power level. A
requirement occurring with increasing frequency for systems of
recent design is to measure and report the power drawn by system
elements in their various operational states so that the total
energy consumed by the system can be minimized, for example, by the
power system controller.
[0068] The loads in FIG. 11 are represented, without limitation, by
a plurality of servers (designated "SVR_1 . . . SVR_n" and also
referred to as "SVR") powered by respective power converters
(designated "PU_1 . . . PU_n" and also referred to as "PU") over
respective power buses (designated "PB_1 . . . PB_n" and also
referred to as "PB"). Each server SVR may be individually coupled
over respective server buses (designated "SVRBUS_1 . . . SVRBUS_n"
and also referred to as "SVRBUS") to a respective power converter
PU for its power source as illustrated herein, or may be coupled to
more than one power converter PU and powered in a redundant manner
to form multiple redundant power converters PU. The power system
controller may also be powered by one of the illustrated power
converters PU, or by another power converter not shown.
[0069] The power converters PU are coupled to the power system
controller PSC over respective power converter communication buses
(designated "PCBUS_1 . . . PCBUS_n" and also referred to as
"PCBUS") that conduct signals therebetween to communicate requests
for a power converter operational state PC.sub.op.sub.--.sub.state
from the power system controller PSC to a power converter PU. The
power system controller PSC may also be coupled over a bus
(designated "BUS_env") to a circuit element (not shown) signaling
an environmental parameter such as a component temperature. In
addition, the power system controller PSC may be coupled over a bus
(designated "BUS_test") to a signal source such as a manufacturing
test set that provides a power converter parameter measured after a
manufacturing step. The power system controller PSC receives
signals representing a power converter status PC.sub.status from
the power converters PU over the respective power converter
communication buses PCBUS and transmits commands thereover for the
power converter operational states PC.sub.op.sub.--.sub.state to
the power converters PU. A signal transmitted by a power converter
may include an estimate of its input power, which is communicated
to the power system controller over its respective power converter
communication bus. The commands for the power converter PU to enter
the power converter operational states PC.sub.op.sub.--.sub.state,
which may advantageously include consideration of the estimate of
power converter input power, can be used to enhance (e.g.,
optimize) an operational efficiency or reliability of the power
converter PU at a power system level. The ability of a power
converter to estimate accurately its input power is thus essential
to minimizing the energy consumed by the system.
[0070] Thus, a controller configured to estimate a power level in a
power processing circuit that can be coupled to an ac power source
has been described. In one embodiment, the controller includes a
multiplier configured to produce a product of an input current and
an input voltage of the power processing circuit. The controller
also includes a low-pass filter configured to produce an input
power estimate of an input power to the power processing circuit as
a function of the product of the input current and the input
voltage. In an exemplary embodiment, the input power estimate is an
output signal of the controller. In an exemplary embodiment, the
controller modifies the input power estimate with a linear
correction in a conversion circuit to produce a signal
substantially proportional to the input power of the power
processing circuit. In an exemplary embodiment, the multiplier and
low-pass filter include a digital circuit. The controller can also
control a power factor of the power processing circuit.
[0071] In another embodiment, the controller includes a voltage
loop compensator configured to produce a voltage compensation
signal as a function of an output voltage of the power processing
circuit. The controller also includes an input power estimator
configured to produce an input power estimate of an input power to
the power processing circuit as a function of the voltage
compensation signal. In an exemplary embodiment, the input power
estimate is an output signal of the controller. In an exemplary
embodiment, the controller further includes a feedforward circuit
that produces a signal inversely proportional to a filtered square
of an input voltage to the power processing circuit, and a
multiplier coupled to an output of the voltage loop compensator and
to the feedforward circuit. The controller further includes a
summer that forms a difference between an output of the multiplier
and a signal representing a current in an inductor of a boost power
stage of the power processing circuit, and a current loop
compensator coupled to the summer. An output of the current loop
compensator is coupled to a pulse-width modulator, and an output of
the pulse-width modulator is coupled to a power switch of the boost
power stage. In an exemplary embodiment, the input power estimator
is coupled to an output of the voltage loop compensator, and
employs a relationship that may be a linear relationship in a
conversion circuit to produce the input power estimate. The
filtered square of an input voltage to the power processing circuit
is filtered to attenuate substantially a fundamental and its higher
harmonic frequency components of an ac input line powering the
power processing circuit. In an exemplary embodiment, the input
power estimator includes a digital circuit.
[0072] Another exemplary embodiment of the invention provides a
method of operating a power processing circuit. In accordance with
one exemplary embodiment, the method includes controlling a power
factor of the power processing circuit by coupling a voltage loop
compensator to an output characteristic of the power processing
circuit, and producing a signal indicative of input power to the
power processing circuit from an output of the voltage loop
compensator. In an exemplary embodiment, the method includes
producing a feedforward signal inversely proportional to a filtered
square of an input voltage to the power processing circuit, and
multiplying an output of the voltage loop compensator, the
feedforward signal, and the rectified input voltage to form a
product. The method further includes forming a difference between
the product and a current signal representing a current in an
inductor of the power processing circuit, coupling a current loop
compensator to the summer, generating a pulse-width modulated
signal from an output of the current loop compensator, and
controlling a power switch of the power processing circuit with the
pulse-width modulated signal. In accordance with an exemplary
embodiment, the method further includes using a linear relationship
in a conversion circuit to produce the signal indicative of input
power from the output of the voltage loop compensator. In
accordance with an exemplary embodiment, the method further
includes filtering the square of the input voltage to the power
processing circuit with a filter that substantially attenuates a
fundamental and its higher harmonic frequency components of an ac
input line powering the power processing circuit. In an exemplary
embodiment, the method includes using a digital circuit to produce
the input power estimate. In an exemplary embodiment, the method
includes producing an output signal of the controller from the
input power estimate.
[0073] In an exemplary embodiment, the input power estimate may be
performed with the boost power factor correction (PFC) circuit
inactive, or with the PFC circuit configured to provide a power
factor between about 0.5 and 0.95. In an exemplary embodiment, the
input power estimate may be performed using a substantially dc
input power source, with or without the boost circuit active.
[0074] In an exemplary embodiment, the controller may be calibrated
to improve the accuracy of the input power estimate. The
calibration parameters may be determined at a manufacturing test
process using an ATE, with the calibration parameters stored in a
nonvolatile memory for use by the controller during the input power
estimate process.
[0075] In an exemplary embodiment, the controller, including the
power estimator, is part of a power converter system, redundant or
non-redundant, providing electrical power to a system external to
the power converter. The external system may comprise a data
processing system such as a server, a storage system, a data packet
router, or any system requiring electrical power where an accurate
input power estimate would be advantageous. The controller is
configured to provide the input power estimate to the external
system through a communications means, including but not limited to
I.sup.2C, Ethernet, a SPI bus, or any suitable electronic
communications medium. The external system may command the
controller to provide the input power estimate, or conversely, the
controller may provide the input power estimate to the external
system as part of a scheduled information transfer.
[0076] Another exemplary embodiment of the invention provides a
method of producing an input power estimate of a power processing
circuit. In an exemplary embodiment, the method includes
multiplying a current and a voltage to produce a current-voltage
product, and filtering the current-voltage product with a low-pass
filter to produce the input power estimate. In an exemplary
embodiment, the method further includes modifying the input power
estimate with a linear correction in a conversion circuit to
produce a signal substantially proportional to a power level. In a
further exemplary embodiment, the method includes performing the
multiplication and the filtering with a digital circuit. In an
exemplary embodiment, the method includes producing an output
signal of the controller from the input power estimate.
[0077] Those skilled in the art should understand that the
previously described embodiments of an input power estimator and
related methods are submitted for illustrative purposes only. Those
skilled in the art understand further that various changes,
substitutions, and alterations can be made to input power estimator
without departing from the spirit and scope of the invention in its
broadest form. In addition, other embodiments capable of providing
the advantages as described hereinabove are well within the broad
scope of the present invention. While the input power estimator and
method have been described as providing advantages in the
environment of a power converter, other power processing circuits
and applications therefor such as an input power estimator for a
power conversion arrangement for a motor or other electromechanical
device are well within the broad scope of the present
invention.
[0078] For a better understanding of power electronics, see
"Principles of Power Electronics," by J. G. Kassakian, M. F.
Schlecht and G. C. Verghese, Addison-Wesley (1991), and "Power
Electronics," by Ned Mohan, Tore M. Undeland, William P. Robbins,
John Wiley & Sons, for details in power electronics and
closed-loop control design for power electronics converters, and
the Designer Reference Manual from Freescale Semiconductor, Inc.,
entitled "Design of a Digital AC/DC SMPS Using the 56F8323 Device,"
for using digital control for power electronic applications. The
aforementioned references are incorporated herein by reference.
[0079] Also, although the present invention and its advantages have
been described in detail, it should be understood that various
changes, substitutions and alterations can be made herein without
departing from the spirit and scope of the invention as defined by
the appended claims. For example, the input power estimators
discussed hereinabove can be implemented in different methodologies
and replaced by other processes, or a combination thereof, to form
the devices providing input power estimation for a power converter
as described herein.
[0080] Moreover, the scope of the present application is not
intended to be limited to the particular embodiments of the
process, machine, manufacture, composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the
disclosure of the present invention, processes, machines,
manufacture, compositions of matter, means, methods, or steps,
presently existing or later to be developed, that perform
substantially the same function or achieve substantially the same
result as the corresponding embodiments described herein may be
utilized according to the present invention. Accordingly, the
appended claims are intended to include within their scope such
processes, machines, manufacture, compositions of matter, means,
methods, or steps.
* * * * *