U.S. patent application number 12/203192 was filed with the patent office on 2008-12-25 for image sensor with gain control.
Invention is credited to Christopher Parks.
Application Number | 20080315272 12/203192 |
Document ID | / |
Family ID | 39496179 |
Filed Date | 2008-12-25 |
United States Patent
Application |
20080315272 |
Kind Code |
A1 |
Parks; Christopher |
December 25, 2008 |
IMAGE SENSOR WITH GAIN CONTROL
Abstract
An image sensor having a plurality of pixels; each pixel
includes one or more photosensitive elements that collect charge in
response to incident light; one or more transfer mechanisms that
respectively transfer the charge from the one or more
photosensitive elements; a charge-to-voltage conversion region
having a capacitance, and the charge-to-voltage region receives the
charge from the one or more photosensitive elements; a first reset
transistor connected to the charge-to-voltage conversion region; a
second reset transistor connected to the first reset transistor,
which in combination with the first reset transistor, selectively
sets the capacitance of the charge-to-voltage conversion regions
from a plurality of capacitances.
Inventors: |
Parks; Christopher;
(Rochester, NY) |
Correspondence
Address: |
Pedro P. Hernandez;Patent Legal Staff
Eastman Kodak Company, 343 State Street
Rochester
NY
14650-2201
US
|
Family ID: |
39496179 |
Appl. No.: |
12/203192 |
Filed: |
September 3, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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11624773 |
Jan 19, 2007 |
7427790 |
|
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12203192 |
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Current U.S.
Class: |
257/292 ;
257/E27.132; 257/E31.001; 348/E3.018 |
Current CPC
Class: |
H04N 5/374 20130101;
H04N 5/3745 20130101; H01L 27/14609 20130101; H04N 5/3559
20130101 |
Class at
Publication: |
257/292 ;
257/E31.001 |
International
Class: |
H01L 31/00 20060101
H01L031/00 |
Claims
1. An image sensor having a plurality of pixels; each pixel
comprising: (a) one or more photosensitive elements that collect
charge in response to incident light; (b) one or more transfer
mechanisms that respectively transfer the charge from the one or
more photosensitive elements; (c) a charge-to-voltage conversion
region having a capacitance, and the charge-to-voltage region
receives the charge from the one or more photosensitive elements;
(d) a first reset transistor connected to the charge-to-voltage
conversion region; (e) a second reset transistor connected in
series to the first reset transistor, which in combination with the
first reset transistor, selectively sets the capacitance of the
charge-to-voltage conversion regions from a plurality of
capacitances; and (f) one or more additional transistors connected
either in series or parallel to the first reset transistor for
further selectively setting the capacitance of the
charge-to-voltage conversion regions from a plurality of
capacitances.
2. The image sensor as in claim 1, wherein the charge-to-voltage
conversion region is a floating diffusion.
3. The image sensor as in claim 1, wherein the image sensor is
included in an image capture device.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation application of U.S. application Ser.
No. 11/624,773 filed Jan. 19, 2007.
FIELD OF THE INVENTION
[0002] The invention relates generally to the field of CMOS active
pixel image sensor and, more particularly, to providing in pixel
floating diffusion capacitance control.
BACKGROUND OF THE INVENTION
[0003] FIG. 1 shows the typical CMOS active pixel image sensor 100.
The basic component of the image sensor 100 is the array of
photosensitive pixels 130. The row decoder circuitry 105 selects an
entire row of pixels 130 to be sampled by the correlated double
sampling (CDS) circuitry 125. The analog-to-digital converter 115
scans across the column decoders and digitizes the signals stored
in the CDS. The analog-to-digital converter 115 may be of the type
which has one converter for each column (parallel) or one
high-speed converter to digitize each column serially. The
digitized data may be directly output from the image sensor 100 or
there may be integrated image processing 120 for defect correction,
color filter interpolation, image scaling, and other special
effects. The timing generator 110 controls the row and column
decoders to sample the entire pixel array or only a portion of the
pixel array.
[0004] FIG. 2 shows one pixel of a CMOS image sensor. There is a
photodiode 151 to collect photo-generated electrons. When the
signal is read from the photodiode 151 the RG signal is pulsed to
reset the floating diffusion node 155, via the reset transistor
150, to the VDD potential. The row select signal RSEL is turned on
to connect the output transistor 153 to the output signal line
through the row select transistor 154. CDS circuit samples the
reset voltage level on the output signal line. Next the transfer
transistor 152 is pulsed on and off to transfer charge from the
photodiode 151 to the floating diffusion node 155. The new voltage
level on the output signal line minus the reset voltage level is
proportional to the amount of charge on the floating diffusion.
[0005] The magnitude of the floating diffusion voltage change is
given by V=Q/C where Q is the amount of charge collected by the
photodiode 151 and C is the capacitance of the floating diffusion
node 155. If the capacitance C is too small and the charge Q is too
large, then the voltage output will be too large for the CDS
circuit. This problem commonly occurs when the pixel size is 2.7
.mu.m or larger and the power supply voltage VDD is 3.3 V or less.
The prior art solution to this problem has generally consisted of
placing extra capacitance on the floating diffusion node 155.
[0006] In FIG. 3, U.S. Pat. No. 6,730,897 increases the floating
diffusion 160 node capacitance by adding a capacitor 161 connected
between the floating diffusion 160 and GND. In FIG. 4, U.S. Pat.
No. 6,960,796 increases the floating diffusion 162 node capacitance
by adding a capacitor 163 connected between the floating diffusion
162 and the power supply VDD. The prior art does increase the
floating diffusion node capacitance enough to ensure the maximum
output voltage is within the power supply limit at maximum
photodiode charge capacity. However, the prior art solution is not
optimum for low light level conditions. When there is a very small
amount of charge in the photodiode, the larger floating diffusion
capacitance lowers the voltage output making it harder to measure
the small signals. What is needed is a way to have a small floating
diffusion capacitance (for increased voltage output) when imaging
in low light levels and a large floating diffusion capacitance (to
lower voltage output below the power supply range) when imaging in
high light levels. This is a form of in pixel gain control.
[0007] FIG. 5 shows a pixel with an extra "dangling" transistor 165
connected to the floating diffusion 166. This pixel is from U.S.
patent application Ser. No. 2006/0103749A1. Switching on the
transistor 165 with the AUX signal line increases the capacitance
of the floating diffusion 166. This method of changing the floating
diffusion capacitance requires four transistor gates 165, 167, 168,
and 169 to closely surround and directly electrically connect to
the floating diffusion. The presence of four transistor gates does
not allow for the smallest possible floating diffusion node
capacitance. When the transistor 165 is turned off, the gate still
adds some additional capacitance compared to the case where only
three transistors are adjacent to the floating diffusion.
[0008] U.S. Pat. No. 7,075,049 also shows pixels with the ability
to change the floating diffusion node capacitance. It also has the
requirement of four transistors adjacent to the floating diffusion
node. Therefore, the pixel designs in U.S. Pat. No. 7,075,049 does
not provide for the smallest possible floating diffusion
capacitance.
[0009] The invention disclosed here will show how to build a pixel
where the floating diffusion capacitance can be changed in response
to signal level. Furthermore, the invention will only require three
transistor gates to be adjacent to the floating diffusion.
SUMMARY OF THE INVENTION
[0010] The present invention is directed to overcoming one or more
of the problems set forth above. Briefly summarized, according to
one aspect of the present invention, the invention resides in an
image sensor having a plurality of pixels; each pixel includes (a)
one or more photosensitive elements that collect charge in response
to incident light; (b) one or more transfer mechanisms that
respectively transfer the charge from the one or more
photosensitive elements; (c) a charge-to-voltage conversion region
having a capacitance, and the charge-to-voltage region receives the
charge from the one or more photosensitive elements; (d) a first
reset transistor connected to the charge-to-voltage conversion
region; (e) a second reset transistor connected to the first reset
transistor, which in combination with the first reset transistor,
selectively sets the capacitance of the charge-to-voltage
conversion regions from a plurality of capacitances.
[0011] These and other aspects, objects, features and advantages of
the present invention will be more clearly understood and
appreciated from a review of the following detailed description of
the preferred embodiments and appended claims, and by reference to
the accompanying drawings.
ADVANTAGEOUS EFFECT OF THE INVENTION
[0012] The invention allows for changing the image sensor pixel
charge to voltage conversion capacitance without compromising the
minimum possible capacitance.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 is a prior art CMOS images sensor with integrated
control electronics and signal processing;
[0014] FIG. 2 is a prior art four-transistor pixel;
[0015] FIG. 3 is a prior art pixel with an extra floating diffusion
capacitor connected to ground (zero volts);
[0016] FIG. 4 is a prior art pixel with an extra floating diffusion
capacitor connected to the power supply VDD;
[0017] FIG. 5 is a prior art pixel with an extra floating diffusion
capacitance control transistor attached to the floating
diffusion;
[0018] FIG. 6 is a schematic diagram of the present invention
showing two reset transistors connected in series to the floating
diffusion for capacitance control;
[0019] FIG. 7 illustrates the present invention operating in low
capacitance high gain mode;
[0020] FIG. 8 illustrates the invention operating in high
capacitance low gain mode;
[0021] FIG. 9 illustrates the present invention in a pixel with
multiple photodiodes connected to one shared floating
diffusion;
[0022] FIG. 10 illustrates the present invention with three reset
transistors in series for two levels of floating diffusion
capacitance control;
[0023] FIG. 11 is an image sensor of the present invention using a
pixel with floating diffusion capacitance control; and
[0024] FIG. 12 is a camera imaging system having an image sensor
using a pixel with floating diffusion capacitance control.
DETAILED DESCRIPTION OF THE INVENTION
[0025] Before discussing the present invention in detail, it is
instructive to note that the present invention is preferably used
in, but not limited to, a CMOS active pixel sensor. Active pixel
sensor refers to an active electrical element within the pixel,
other than transistors functioning as switches. For example, the
floating diffusion or amplifier are active elements. CMOS refers to
complementary metal oxide silicon type electrical components such
as transistors which are associated with the pixel, but typically
not in the pixel, and which are formed when the source/drain of a
transistor is of one dopant type and its mated transistor is of the
opposite dopant type. CMOS devices include some advantages one of
which is it consumes less power.
[0026] FIG. 6 is a schematic diagram of a pixel 208 having gain
control of the present invention. It is noted that it only has
three transistors adjacent to the floating diffusion node 200 while
the prior art always had four transistors adjacent to the floating
diffusion node. The three transistors are the transfer transistor
206 that controls the transfer of photo-generated charge from the
photodiode 207 to the floating diffusion node 200, the reset
transistor 201 and the output signal transistor 204. Transistor 205
is the row select transistor that is turned on to select which row
is to have the output signal transistor 204 connected to the output
signal line. Transistor 203 is a secondary reset transistor that
allows changing of the floating diffusion capacitance when operated
in conjunction with transistor 201.
[0027] The operation of the pixel is illustrated in FIGS. 7 and 8.
First in FIG. 7, the pixel operation is in low capacitance (high
gain) mode. This mode would be used in low light level conditions.
The photodiode 207 has collected a small amount of photo-generated
charge. In this case, it is desired to have the minimum floating
diffusion 200 capacitance. To lower the capacitance, transistors
201 and 203 are turned off. It is noted, for clarity, that n+doping
202 (diffusion) exists to form transistors 201 and 203. When the
amount of photo-generated charge is measured the transfer gate 206
pulses on and then off to cause the transfer of charge from the
photodiode 207 to the floating diffusion 200. The new voltage on
the floating diffusion 200 is sampled through the output 204 and
row select 205 transistors (as shown in FIG. 6). After the output
is sampled, turning on both transistors 201 and 203 connects the
floating diffusion to the VDD power to supply reset for the
floating diffusion.
[0028] High capacitance (low gain) mode is illustrated in FIG. 8.
In this case, the photodiode 207 has been exposed to bright light
and has collected a large amount of photo-generated charge. This
amount of charge would not fit on the floating diffusion node 200
in the low capacitance mode of FIG. 7. Therefore, in FIG. 8, the
transistor 201 is turned on so now charge can spread out under the
transistor gate 201 and the diffusion 202 also becomes part of the
expanded floating diffusion. When charge is transferred from the
photodiode 207 to the expanded floating diffusion, it fits onto the
higher capacitance floating diffusion The expanded floating
diffusion is reset by pulsing the transistor 203 on and off.
[0029] FIG. 9 illustrates how the present invention can be applied
to other types of pixels. FIG. 9 is a pixel with two photodiodes
210 and 211 connected by transfer gates to the floating diffusion
212. The invention places two reset transistors 213 and 214 in
series to provide capacitance control of the floating diffusion
212. Hence, it is possible to apply the present invention to every
pixel type having a floating diffusion connected to one or more
transfer gates, one output transistor, and one reset transistor.
The present invention replaces the reset transistor of a prior art
pixel by two or more transistors placed in series between the
floating diffusion and reset power supply node.
[0030] FIG. 10 illustrates how it is possible to have more than two
levels of floating diffusion capacitance control by placing more
than two reset transistors 215, 216, and 217 in series. The number
of difference capacitance combinations in this case is equal to 2.
For an arbitrary number of reset transistors, the number of
capacitance combinations is N-1 where N is the number of reset
transistors. It is also possible to replace transistor 216 by a set
of transistors in parallel instead of in series. Placing the
transistors in parallel would allow for a greater number of
capacitance combinations than if they were all in series.
[0031] FIG. 11 shows a CMOS active pixel image sensor 300 of the
present invention having a pixel 208 of the present invention
employing pixel level floating diffusion capacitance (or gain)
control. The basic component of the image sensor 300 is the array
of photosensitive pixels 208. The row decoder circuitry 305 selects
an entire row of pixels 208 to be sampled by the correlated double
sampling (CDS) circuitry 325. The analog-to-digital converter 315
scans across the column decoders and digitizes the signals stored
in the CDS. The analog-to-digital converter 315 may be of the type
that has one converter for each column (parallel) or one high-speed
converter to digitize each column serially. The digitized data may
be directly output from the image sensor or there may be integrated
image processing 320 for defect correction, color filter
interpolation, image scaling, and other special effects. The timing
generator 310 controls the row and column decoders to sample the
entire pixel array or only a portion of the pixel array.
[0032] FIG. 12 shows the image sensor 300 employing a pixel level
floating diffusion capacitance control in an electronic imaging
system, preferably a digital camera 400.
[0033] The invention has been described with reference to a
preferred embodiment. However, it will be appreciated that
variations and modifications can be effected by a person of
ordinary skill in the art without departing from the scope of the
invention.
PARTS LIST
[0034] 100 image sensor [0035] 105 row decoder circuitry [0036] 110
timing generator [0037] 115 analog-to-digital converter [0038] 120
integrated image processing [0039] 125 correlated double sampling
(CDS) circuitry [0040] 130 array of photosensitive pixels [0041]
150 reset transistor [0042] 151 photodiode [0043] 152 transfer
transistor [0044] 153 output transistor [0045] 154 row select
transistor [0046] 155 floating diffusion node [0047] 160 floating
diffusion [0048] 161 capacitor [0049] 162 floating diffusion [0050]
163 capacitor [0051] 165 "dangling" transistor/transistor gate
[0052] 166 floating diffusion [0053] 167 reset
transistor/transistor gate [0054] 168 transistor gate [0055] 169
transistor gate [0056] 200 floating diffusion [0057] 201 reset
transistor/transistor gate [0058] 202 diffusion [0059] 203
secondary reset transistor [0060] 204 output signal transistor
[0061] 205 row select transistor [0062] 206 transfer
transistor/gate [0063] 207 photodiode [0064] 208 pixel/array of
pixels [0065] 210 photodiode [0066] 211 photodiode [0067] 212
floating diffusion [0068] 213 reset transistor [0069] 214 reset
transistor [0070] 215 reset transistor [0071] 216 reset transistor
[0072] 217 reset transistor [0073] 300 image sensor [0074] 305 row
decoder circuitry [0075] 310 timing generator [0076] 315
analog-to-digital converter [0077] 320 integrated image processing
[0078] 325 correlated double sampling (CDS) circuitry [0079] 400
electronic imaging system (digital camera)
* * * * *