U.S. patent application number 12/195856 was filed with the patent office on 2008-12-18 for microcomputer and dividing circuit.
Invention is credited to Yasushi Akao, Yoichi Asano, Shiro Baba, Hideaki Chaki, Shuya Fujita, Kaoru Fukada, Katsuhiko Ishida, Masahiro Kainaga, Yugo Kashiwagi, Shumpei KAWASAKI, Toshimasa Kihara, Keiichi Kurakazu, Shigeki Masumura, Kouki Noguchi, Eiji Sakakibara, Noriko Sawa, Tadahiko Sugawara, Yasuhiro Tawara, Takashi Tsukamoto, Mitsuru Watabe, Takanaga Yamazaki.
Application Number | 20080313444 12/195856 |
Document ID | / |
Family ID | 26482784 |
Filed Date | 2008-12-18 |
United States Patent
Application |
20080313444 |
Kind Code |
A1 |
KAWASAKI; Shumpei ; et
al. |
December 18, 2008 |
MICROCOMPUTER AND DIVIDING CIRCUIT
Abstract
Herein disclosed is a microcomputer MCU adopting the general
purpose register method. The microcomputer is enabled to have a
small program capacity or a high program memory using efficiency
and a low system cost, while enjoying the advantage of
simplification of the instruction decoding as in the RISC machine
having a fixed length instruction format of the prior art, by
adopting a fixed length instruction format having a power of 2 but
a smaller bit number than that of the maximum data word length fed
to instruction execution means. And, the control of the coded
division is executed by noting the code bits.
Inventors: |
KAWASAKI; Shumpei; (Tokyo,
JP) ; Sakakibara; Eiji; (Tokyo, JP) ; Fukada;
Kaoru; (Tokyo, JP) ; Yamazaki; Takanaga;
(Tokyo, JP) ; Akao; Yasushi; (Tokyo, JP) ;
Baba; Shiro; (Tokyo, JP) ; Kihara; Toshimasa;
(Tokyo, JP) ; Kurakazu; Keiichi; (Tokorozawa-shi,
JP) ; Tsukamoto; Takashi; (Tokyo, JP) ;
Masumura; Shigeki; (Tokyo, JP) ; Tawara;
Yasuhiro; (Tokyo, JP) ; Kashiwagi; Yugo;
(Tokyo, JP) ; Fujita; Shuya; (Tokyo, JP) ;
Ishida; Katsuhiko; (Tokyo, JP) ; Sawa; Noriko;
(Tokyo, JP) ; Asano; Yoichi; (Tokyo, JP) ;
Chaki; Hideaki; (Tokorozawa-shi, JP) ; Sugawara;
Tadahiko; (Tokyo, JP) ; Kainaga; Masahiro;
(Yokohama-shi, JP) ; Noguchi; Kouki; (Tokyo,
JP) ; Watabe; Mitsuru; (Naka-gun, JP) |
Correspondence
Address: |
MATTINGLY, STANGER, MALUR & BRUNDIDGE, P.C.
1800 DIAGONAL ROAD, SUITE 370
ALEXANDRIA
VA
22314
US
|
Family ID: |
26482784 |
Appl. No.: |
12/195856 |
Filed: |
August 21, 2008 |
Related U.S. Patent Documents
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Application
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Filing Date |
Patent Number |
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11120105 |
May 3, 2005 |
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12195856 |
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10011807 |
Dec 11, 2001 |
6996700 |
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11120105 |
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09632332 |
Aug 3, 2000 |
6343357 |
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10011807 |
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09053638 |
Apr 2, 1998 |
6253308 |
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09632332 |
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08478730 |
Jun 7, 1995 |
5991545 |
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09053638 |
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07897457 |
Jun 10, 1992 |
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08478730 |
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Current U.S.
Class: |
712/234 ;
712/E9.003; 712/E9.016; 712/E9.017; 712/E9.025; 712/E9.028;
712/E9.035; 712/E9.049; 712/E9.055; 712/E9.075 |
Current CPC
Class: |
G06F 2207/5352 20130101;
G06F 9/3557 20130101; G06F 9/3867 20130101; G06F 9/30 20130101;
G06F 9/30181 20130101; G06F 9/30112 20130101; G06F 9/324 20130101;
G06F 9/30167 20130101; G06F 9/3836 20130101; G06F 9/3013 20130101;
G06F 7/535 20130101; G06F 9/30189 20130101; G06F 9/322 20130101;
G06F 9/3001 20130101; G06F 9/3802 20130101; G06F 9/3814 20130101;
G06F 9/30163 20130101; G06F 9/30149 20130101; G06F 9/3857 20130101;
G06F 9/3859 20130101; G06F 9/30145 20130101; G06F 9/3016
20130101 |
Class at
Publication: |
712/234 ;
712/E09.003 |
International
Class: |
G06F 9/06 20060101
G06F009/06 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 24, 1991 |
JP |
3-178739 |
May 21, 1992 |
JP |
4-154525 |
Claims
1.-21. (canceled)
22. A microcomputer formed on a single semiconductor device
comprising: a CPU having a 32-bit general purpose register; and a
memory coupled to said CPU, wherein said CPU is capable of
processing at least one conditional branch instruction and at least
one unconditional branch instruction, wherein the memory stores
instructions to be processed by said CPU, wherein each of the
instruction bit lengths of the conditional branch instruction and
the unconditional branch instruction is 16 bits, and wherein a
displacement length of the conditional branch instruction is
smaller than the displacement length of the unconditional branch
instruction.
23. The microcomputer according to claim 22, wherein the
displacement length of the conditional branch instruction is 8
bits.
24. The microcomputer according to claim 22, wherein the
displacement length of the unconditional branch instruction is 12
bits.
25. The microcomputer according to claim 22, wherein the memory is
a cache memory.
26. A microcomputer formed on a single semiconductor device
comprising: a RISC type CPU having a 32-bit general purpose
register; and a memory coupled to said RISC type CPU, wherein said
RISC type CPU is capable of processing at least one conditional
branch instruction and at least one unconditional branch
instruction, wherein the memory stores instructions to be processed
by said RISC type CPU, wherein each of the instruction bit lengths
of the conditional branch instruction and the unconditional branch
instruction is 16 bits, and wherein a displacement length of the
conditional branch instruction is smaller than the displacement
length of the unconditional branch instruction.
27. The microcomputer according to claim 26, wherein the
displacement length of the conditional branch instruction is 8
bits.
28. The microcomputer according to claim 26, wherein the
displacement length of the unconditional branch instruction is 12
bits.
29. The microcomputer according to claim 26, wherein the memory is
a cache memory.
30. A microcomputer formed on a single semiconductor device
comprising: a CPU having a 32-bit general purpose register; a RAM
coupled to said CPU; a DMA controller coupled to said RAM; and a
memory coupled to said CPU, wherein said CPU is capable of
processing at least one conditional branch instruction and at least
one unconditional branch instruction, wherein the memory stores
instructions to be processed by said CPU, and wherein a
displacement length of the conditional branch instruction is
smaller than the displacement length of the unconditional branch
instruction.
31. The microcomputer according to claim 30, wherein the memory is
a cache memory.
32. The microcomputer according to claim 30, wherein each of the
instruction bit lengths of the conditional branch instruction and
the unconditional branch instruction is 16 bits.
33. The microcomputer according to claim 32, wherein the
displacement length of the conditional branch instruction is 8
bits.
34. The microcomputer according to claim 32, wherein the
displacement length of the unconditional branch instruction is 12
bits.
35. A microcomputer formed on a single semiconductor device
comprising: a CPU having general purpose registers and a program
counter; and a memory coupled to said CPU, wherein said CPU is
capable of processing at least one data transfer instruction, at
least one conditional branch instruction and at least one
unconditional branch instruction, wherein each of the instruction
bit lengths of the data transfer instruction, the conditional
branch instruction and the unconditional branch instruction is 16
bits, wherein the memory stores instructions to be processed by
said CPU, wherein the conditional branch instruction includes a
first area for a first displacement, wherein the unconditional
branch instruction includes a second area for a second
displacement, wherein a length of the first displacement of the
conditional branch instruction is smaller than a length of the
second displacement of the unconditional branch instruction,
wherein the data transfer instruction includes a third area for a
third displacement and a fourth area for destination register
information for designating the general purpose register where the
data is loaded, wherein the branch address of the conditional
branch instruction is obtained based on the first displacement in
the first area of the conditional branch instruction and an address
in the program counter, wherein the branch address of the
unconditional branch instruction is obtained based on the second
displacement in the second area of the unconditional branch
instruction and an address in the program counter, and wherein 32
bits source data of the data transfer instruction is obtained from
a memory location indicated by an address obtained based on the
third displacement in the third area of the data transfer
instruction and an address in the program counter, and the source
data is loaded into one of the general purpose registers which is
designated by the fourth area of the data transfer instruction.
36. The microcomputer according to claim 35, wherein the
displacement length of the data transfer instruction is 8 bits.
37. The microcomputer according to claim 35, wherein the program
counter is 32 bit length.
38. The microcomputer according to claim 35, wherein the general
purpose register is 32 bit length.
39. The microcomputer according to claim 35, wherein the
displacement length of the conditional branch instruction is 8
bits.
40. The microcomputer according to claim 35, wherein the
displacement length of the unconditional branch instruction is 12
bits.
41. The microcomputer according to claim 35, wherein the memory is
a cache memory.
42. The microcomputer according to claim 35, wherein the address of
the memory location is obtained by adding the displacement in the
first area with an address in the program counter.
43. The microcomputer according to claim 35, wherein the data
transfer instruction further includes a fifth area having an
operation code defining a data transfer operation, wherein the
operation code includes data size information of the data to be
transferred, and wherein the displacement is shifted by 2 bits and
the shifted displacement is added to the address in the program
counter when the data size information indicates that the data size
is 32 bits.
Description
BACKGROUND OF THE INVENTION
[0001] The present invention relates to an architecture of a
microcomputer, particularly a RISC (Reduced Instruction Set
Computer) type microcomputer and, more particularly, to a
technology effective if applied to a microcomputer to be packaged
in a device for controlling it.
[0002] Moreover, the present invention relates to a circuit for
coded division such as a dividing circuit for a coded binary number
of arbitrary length and multi-precision and, more particularly, to
a technology effective if applied to a step division of the RISC
type microcomputer.
[0003] The most serious bottleneck for reducing the number of
machine cycles necessary for executing one instruction is known to
be the decoding of the instruction. In order to speed up this
decoding, it is know effective to adopt an instruction format of
fixed length so that where the boundary of the instruction resides
may be informed before a preceding instruction has been
interpreted. In the so-called "RISC type computer", most
instructions are executed for one cycle by adopting the instruction
format of fixed length and a pipe line of multiple steps. The
conventional RISC computer has used a 32-bit instruction format
without exception. This 32-bit fixed length instruction format is
advantageous in that what register is to be read can be determined
without decoding the operation code by fixing fields in the
instruction formats of a source register and a destination
register, and in that no alignment is required when an immediate
value is decoded. On the contrary, the 32-bit fixed length
instruction format requires 32 bits even no matter simple content
of an instruction might be described. As a result, the number of
bytes occupied by the instruction code is increased to raise a
problem that the ratio of the memory area to be occupied by a
program is accordingly increased. If the memory area occupied by
the program is increased, a memory having a larger capacity has to
be packaged to raise the cost of the microcomputer system, thus
making it difficult to construct a system having an excellent
performance ratio to the cost. Since the RISC processor is given an
architecture for speeding up the executions of instructions by
reducing the number of instructions, there arises a tendency that
the undefined operation codes grow more for the instruction set.
The multiplicity of the undefined operation codes deteriorates the
code efficiency of the object program and degrades the memory using
efficiency the worse.
[0004] The preceding patent application for improving such memory
using efficiency or code efficiency is exemplified by Japanese
Patent Application No. 222203/1990 (corresponding to U.S. patent
application having Ser. No. 07/748,779 filed on Aug. 22, 1991).
This application discloses a concept that the instruction format
has a shorter bit number than that of the data word length. In this
case, however, we have found that the various problems have to be
solved by adopting the fixed length instruction format having a
shorter bit number than the data word length. For example, new
measures for the data processing have to be examined on the case,
in which immediate data having a bit number equivalent to the data
word length are necessary, or on the manner for assigning a branch
destination address such as an absolute address as to the enlarged
program or system structure. On the other hand, the above-specified
application has failed to take any consideration into a relation of
a power of 2 between the data word length and the instruction word
length. Thus, the application has failed to positively prevent such
a misalignment, in which one instruction is present across one word
boundary of the memory, to leave new items such as the memory using
efficiency, the software program simplification or the processing
rate unexamined.
[0005] As a dividing technology to be executed in the microcomputer
or the like, on the other hand, there is well known a division
method, in which the codes of the quotient and the remainder are
determined from the code of a dividend and the code of a divisor to
execute the division with the absolute value of the dividend by a
recovering method or a recovered method until the codes of the
quotient and the remainder are finally corrected. In recent years,
there are disclosed in the coded division several circuits and
methods for executing the divisions in the coded state without
taking the absolute values of the dividend and the divisor. In case
the division is to be executed with the coded dividend and divisor,
either method basically adopts the following procedures.
Specifically, in case the code of the dividend or partial remainder
and the code of the divisor are equal, the result of subtraction of
the divisor from the dividend or partial remainder is used as a new
partial remainder. In case, on the other hand, the code of the
dividend or partial remainder and the code of the divisor are
different, the result of an addition of the divisor to the dividend
or partial remainder is used as a new partial remainder. Thus, the
quotient is determined by repeating the subtractions or additions
sequentially. At this time, in case the dividend is positive or in
case the dividend is not contained by the divisor, a correct answer
can be achieved by executing some quotient or remainder corrections
on the basis of those procedures. In case, however, the dividend is
negative and in case the dividend is contained by the divisor, the
quotient thus determined is smaller than the correct quotient by
the value "1" having an LSB weight toward the smaller absolute
value. This error is caused by deeming the code of the partial
remainder as correct in case the negative dividend or the partial
remainder is subjected to the aforementioned addition or
subtraction so that the partial remainder takes a zero.
[0006] In order to eliminate this error, there have been devised
several dividing circuits which are equipped with means for
detecting that the partial remainder is zero to correct the
quotient. In Japanese Patent Laid-Open No. 165326/1990, for
example, there is disclosed a technique, in which the irrecoverable
dividing means is equipped with a register, which is set when the
arithmetic result (i.e., the partial remainder) on each line is
zero and reset when the value 1 enters the least significant bit on
each line of the dividend, so that the quotient and remainder are
corrected by using the result of the register. According to this
disclosure, a correct coded division is realized by detecting and
correcting the case, in which the partial remainder is zero, by
using the aforementioned set and reset register. In Japanese Patent
Laid-Open No. 171828/1990, on the other hand, there is disclosed
another technique for preventing an erroneous quotient bit from
being outputted in case the dividend is negative, by detecting
whether or not the partial remainder is zero at each step of
determining the quotient bit. In Japanese Patent Laid-Open No.
160235/1984, moreover, there is disclosed a technique which is
equipped with a hardware for detecting the case, in which the
partial remainder is zero, so that the most significant bit of the
partial remainder may be deemed as 1 if the dividend is negative
and if the partial remainder becomes zero in the course of the
division.
[0007] Thus, in the prior art for the division with the coded
dividend and divisor, the quotient bit is corrected by detecting
that the partial remainder is zero. According to this technique,
whether or not the partial remainder is zero has to be decided each
time it is determined, and these decisions have to be accomplished
n-times if the divisor has n bits. Moreover, whether or not the
partial remainder is zero is not determined until all bits are
examined. Therefore, the necessity for a special purpose hardware
is anticipated if one decision is to be speeded up.
SUMMARY OF THE INVENTION
[0008] An object of the present invention is to solve the various
problems accompanying the adoption of a fixed length instruction
format having a smaller bit number than that of a data word length.
A more specific object of the present invention is to provide a
microcomputer which can achieve one or plural items selected from:
that neither the use of immediate data nor the assignment of an
absolute address is restricted even if the bit number of the fixed
length instruction format is less than that of the data word
length; that a description such as a necessary displacement can be
executed in the fixed length instruction format having a limited
bit number; that a contribution is made to the prevention of a
misalignment of the program arrangement on a memory; and that the
code efficiency or memory using efficiency is improved better from
the standpoint of the content of a supporting instruction.
[0009] Another object of the present invention is to provide a
division circuit which can determine a correct quotient easily
without detecting whether or not a partial remainder is 0 at each
dividing step of determining a quotient bit even in case a dividend
is negative. Still another object of the present invention is to
provide a division circuit which can develop a division program
without considering whether the dividend is positive or negative. A
further object of the present invention is to provide a division
circuit which can improve the dividing efficiency with a simple
circuit structure.
[0010] The foregoing and other objects and novel features of the
present invention will become apparent from the following
description to be made with reference to the accompanying
drawings.
[0011] The representatives of the invention to be disclosed herein
will be briefly summarized in the following.
(1) In a microcomputer adopting the general purpose register
method, there is adopted a fixed length instruction format which
has a smaller bit number than that of the maximum data word length
fed to instruction execution means. (2) In order that the bit
number set in the fixed length instruction format may prevent a
misalignment of a program on a memory, the fixed length instruction
format and the maximum data word length may be set to a bit number
of a power of 2. If the maximum data word length is 32 bits, for
example, the instruction format is fixed to 16 bits. (3) In case
the aforementioned relation holds between the maximum word length
of data and the bit number of the instruction format, a plurality
of instruction may be prefetched in a common cycle so as to fetch
the instructions efficiently by making use of an internal bus of a
bit number equal to that of the maximum data word length or to
reduce the bus access number for the instruction fetch. (4) In case
the internal bus is shared between the data transfer and the
instruction fetch, the pipe control may be executed to prefer the
data fetch thereby to delay the whole instruction execution
schedule including an instruction fetch conflicting with that data
fetch, so as to simplify either a processing when the data fetch
and the instruction fetch conflict or a post-processing caused by
the former. (5) In order to simply cope with the state, in which
the uses of the general purpose registers in response to the
instructions before and after the pipe-line execution, the
pipe-line control may be executed, because the general purpose
register method is adopted, by detecting the state, in which the
uses of the general purpose registers in response to the plurality
of instructions to be executed in the pipe-line manner conflicts,
on the basis of the information of a register assigned area
contained in the instruction format, thereby to delay the execution
of an instruction after the register conflicting state on the basis
of the register conflicting state detected and the execution cycle
number of the instruction to be preferentially executed. (6) In
order that the restriction on the bit number of the fixed length
instruction format may not limit the use of immediate data, it is
advisable to support the instruction containing a description for
assigning the immediate data in a data relation for offsetting the
value of a displacement relative to the value of a predetermined
register. (7) Even in the fixed length instruction format having a
restricted bit number, the displacement necessary for the data
processing or the bit number of the immediate data may be maximized
to support an instruction for implicitly assigning a predetermined
general purpose register which is fixed as an operand despite of no
register assigning field in the instruction. (8) Even in the fixed
length instruction format having a restricted bit number, likewise,
the displacement necessary for the processing or the bit number of
the immediate data may be maximized to support an instruction
containing a description for reflecting the truth or false of the
arithmetic result for a specified condition upon a predetermined
status flag. (9) A proper branch destination assigning displacement
length is fixedly assigned in accordance with the kinds of
branching instructions. For a 16 bit fixed length instruction
format, the displacement of a condition branching instruction is
fixed at 8 bits, and the displacements of a subroutine branching
instruction and an unconditional branching instruction are fixed to
12 bits. (10) In case a dividend is negative in a coded division, a
preliminary processing is executed by subtracting the value "1"
having a weight of the LSB of the dividend from the dividend. This
dividend is an integer if its LSB weight is 1. In case the dividend
is a number having a fixed point, no substantial influence will
arise even if the division is executed by assuming it to be an
integer. This is because the point may be later adjusted. Hence,
there arises no actual harm even if the intermediate calculations
are executed while deeming the dividend as an integer by assuming
the weight of the LSB of the dividend to be 1. In the following
description, the dividend will be deemed as an integer unless
otherwise especially specified so. (11) Noting that the code bit is
1 for a negative dividend and 0 for a positive or zero dividend,
the subtraction of a code bit (i.e., the MSB) is subtracted from
the dividend is the subtraction of 1 from a negative dividend. This
calculation can be deemed as a transformation from a
negative-integer in a complement expression of 2 to a complement
expression of 1. In this way, the preliminary processing for the
dividend can be executed without considering whether the dividend
is positive or negative. FIG. 35 shows a transformation state, in
which the number 1 is subtracted from a negative integer of 4 bits,
for example. Since an extra 1 bit is necessary for transforming the
minimum value of a complement of 2 of a finite bit number into a
complement of 1, an extension of 1 bit is executed, if necessary.
Since a partial remainder may be positive, the aforementioned
transformation for a negative integer is extended all over integers
to introduce a new integer expression. For example, an expression
shown in FIG. 36 is adopted within a range of coded integers of 4
bits. If an arbitrary integer is expressed by a number ZZ which is
calculated by subtracting 1 from that integer, the expression of
the ZZ, which has been transformed by subtracting 1 from an integer
using a complement of 2, can be deemed equal to a complement of 1
in an integer no more than 0 and can be expressed in an integer no
less than 0 by a number which is smaller by 1 than the intrinsic
value. At this time, the code bit of 0 is 1 as for a negative
number. (12) In order to hold the quotient and the partial
remainder (or rest) in the procedure of the coded division, the
quotient (or quotient bit) and the rest (or partial remainder) may
be latched in single storage means such as one register so that the
number of processing steps for transferring the quotient bit or
partial remainder to be calculated or used for the calculations to
the register or the like may be reduced. (1) According to the means
described above, the adoption of a 16 bit fixed length instruction
format for a 32 bit data word length makes it possible to grasp the
decision of where an instruction boundary resides, before a
preceding instruction is completed, like the RISC machine of the
prior art having the 32 bit fixed length instruction format in the
point that the instruction format has the fixed length, thereby to
warrant an advantage such as a simplification of the instruction
decoding. (2) The program capacity is smaller than that of the
case, in which the 32 bit fixed length instruction format is
adopted. Specifically, in the RISC architecture for speeding up the
executions of instructions by reducing the kinds of them, there is
a tendency that many undefined operation codes are in the
instruction set. If the instruction length is halved at this time
from that of the prior art, the using efficiency of the program
memory is improved. (3) The various problems intrinsic to the
adoption of a fixed length instruction format having a smaller bit
number than that of a data word length are solved by the facts:
that neither the use of immediate data nor the assignment of an
absolute address is restricted even if the bit number of the fixed
length instruction format is less than that of the data word
length; that a description such as a necessary displacement can be
executed in the fixed length instruction format having a limited
bit number; that a contribution is made to the prevention of a
misalignment of the program arrangement on a memory; and that the
code efficiency or memory using efficiency is improved better from
the standpoint of the content of a supporting instruction. (4)
According to the means for the aforementioned coded division, the
quotient is determined by: subtracting the value 1 having the
weight of the LSB of a dividend from the dividend in case the
dividend is negative; predicting the code of a quotient; adding and
subtracting a divisor to and from the dividend or partial remainder
while depending upon whether the exclusive OR between the code of
the dividend or partial remainder and the code of the divisor is 0
or 1 to exemplify the quotient bit by the exclusive OR between the
code of the partial remainder and the code of the divisor; and
correcting the quotient of the complement of 1 into a complement of
2 in case the quotient is negative. (5) In case the aforementioned
dividend is negative, the subtraction of the value 1 having the
weight of the LSB of the dividend from the dividend is equivalent
to the preliminary processing for expressing the value 0 such that
all the bits and the code bits are expressed by 1. This preliminary
processing makes it unnecessary to detect that the partial
remainder is 0 in case the dividend is negative. As a result, the
divisions including the overflow check or the correction of the
remainder can be controlled on the basis of information such as the
code bit of the first dividend, the code bit of the partial
remainder, the code bit of the divisor and the code bit of the
quotient. This can simplify the hardware and software of the
divisions and can effect an application to the coded divisions of
arbitrary length and arbitrary accuracy. In addition, the register
for latching the partial remainder can be shifted to a more
significant side by 1 bit, and the processing for applying means
for shifting in the quotient bit can be speeded up.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 is a block diagram showing one example of a system
making use of a microcomputer MCU according to one embodiment of
the present invention;
[0013] FIG. 2 is a block diagram showing a microcomputer according
to one embodiment of the present invention;
[0014] FIG. 3 is a diagram for conceptionally explaining a pin
arrangement for a package of a microcomputer according to the
present embodiment;
[0015] FIG. 4 is an explanatory diagram showing one example of the
relation between the data word length and the instruction word
length to the bus width in the microcomputer according to the
present embodiment;
[0016] FIG. 5 is a block diagram showing one example an internal
block of a central processing unit, especially its instruction
control system included in the microcomputer of the present
embodiment;
[0017] FIG. 6 is a block diagram showing the structure of one half
of an execution unit of the central processing unit;
[0018] FIG. 7 is a block diagram showing the structure of the
remaining half of the execution unit of the central processing
unit;
[0019] FIG. 8 is a diagram for explaining one example of a stage of
a pipe-line processing by the central processing unit;
[0020] FIG. 9 is a diagram for explaining one example of a
pipe-line sequence in a register conflicting state;
[0021] FIG. 10 is a diagram for explaining another example of a
pipe-line sequence in a register conflicting state;
[0022] FIG. 11 is a diagram for explaining one example of a pipe
control sequence in case a data fetch and an instruction fetch
conflict;
[0023] FIG. 12 is an operation timing chart showing one example
when a plurality of cycle instructions are executed;
[0024] FIG. 13 is an explanatory diagram showing a table of one
half of data transfer instructions to be executed in the
microcomputer of the present embodiment;
[0025] FIG. 14 is an explanatory diagram showing a table of the
remaining half of data transfer instructions to be executed in the
microcomputer of the present embodiment;
[0026] FIG. 15 is an explanatory diagram showing a table of logical
operation instructions to be executed by the microcomputer of the
present embodiment;
[0027] FIG. 16 is an explanatory diagram showing a table of one
half of arithmetic operation instructions to be executed by the
microcomputer of the present embodiment;
[0028] FIG. 17 is an explanatory diagram showing a table of the
remaining half of arithmetic operation instructions to be executed
by the microcomputer of the present embodiment;
[0029] FIG. 18 is an explanatory diagram showing a table of
instructions to be executed by the microcomputer of the present
embodiment;
[0030] FIG. 19 is an explanatory diagram showing a table of
branching instructions to be executed by the microcomputer of the
present embodiment;
[0031] FIG. 20 is an explanatory diagram showing a table of one
half of system control instructions to be executed by the
microcomputer of the present embodiment;
[0032] FIG. 21 is an explanatory diagram showing a table of the
remaining half of system control instructions to be executed by the
microcomputer of the present embodiment;
[0033] FIG. 22 is a diagram for explaining the description types of
FIGS. 13 to 21;
[0034] FIG. 23 is an explanatory diagram showing a table of
addressing modes in the mnemonic designations shown in FIGS. 13 to
21;
[0035] FIG. 24 is an explanatory diagram showing one example of the
relations between the displacement lengths of branch instructions
and the appearance frequency of instructions having the
displacement lengths;
[0036] FIG. 25 is an explanatory diagram showing one example of the
relations between the displacement lengths of branch always
instructions and the appearance frequency of instructions having
the displacement lengths;
[0037] FIG. 26 is an explanatory diagram showing one example of the
relations between the displacement lengths of subroutine call
instructions and the appearance frequency of instructions having
the displacement lengths;
[0038] FIG. 27 is an explanatory diagram showing one example of the
relations between the displacement lengths of jump instructions or
jump subroutine instructions and the appearance frequency of
instructions having the displacement lengths;
[0039] FIG. 28 is a diagram for explaining the structure of a
register of an example as a programmer's model;
[0040] FIG. 29 is a conceptional diagram showing the principle of a
preliminary processing for a dividend in a coded division according
to the present invention;
[0041] FIG. 30 is a diagram for explaining one principle example of
the coded division processing in case of negative/negative;
[0042] FIG. 31 is a diagram for explaining one principle example of
the coded division processing in case of negative/positive;
[0043] FIG. 32 is a diagram for explaining one principle example of
the coded division processing in case of positive/positive;
[0044] FIG. 33 is an explanatory view showing in a general form the
entirety of the basic promises or processing procedures of the
coded division according to the present invention;
[0045] FIG. 34(A) is a diagram for explaining the manner of a
pre-correction of a dividend, and FIG. 34(B) is a diagram for
explaining a prediction of the code of a quotient;
[0046] FIG. 35 is a diagram for explaining one example of the
pre-correction of a negative dividend;
[0047] FIG. 36 is a diagram for explaining an example of the
expression of a partial remainder after the pre-correction of
subtracting 1 from the negative dividend;
[0048] FIG. 37(A) is a diagram for explaining one example how to
extract an addition/subtraction command in the coded dividing
procedure, and FIG. 37(B) is a diagram for explaining one example
how to extract a quotient bit;
[0049] FIG. 38 is a diagram for explaining one example how to
correct the quotient and the remainder;
[0050] FIG. 39 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of -8/-3;
[0051] FIG. 40 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 39;
[0052] FIG. 41 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of -8/3;
[0053] FIG. 42 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 41;
[0054] FIG. 43 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of -9/-3;
[0055] FIG. 44 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 43;
[0056] FIG. 45 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of -9/3;
[0057] FIG. 46 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 45;
[0058] FIG. 47 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of 8/3;
[0059] FIG. 48 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 47;
[0060] FIG. 49 is a diagram for explaining a specific processing
procedure for the pre-correction and the dividing processing in a
coded division of 8/-3;
[0061] FIG. 50 is a diagram for explaining a specific processing
procedure of a post-processing continued from the processing of
FIG. 49;
[0062] FIG. 51 is a block diagram showing one embodiment of an
operation unit for a coded division;
[0063] FIG. 52 is a logical circuit diagram showing one example of
an arithmetic logical operation circuit, an operation circuit and
an operation control circuit shown in FIG. 51;
[0064] FIG. 53 is a detailed diagram for explaining one example of
an instruction description for the coded division;
[0065] FIG. 54 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction EOR R0,R0 of FIG.
53;
[0066] FIG. 55 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction SL16 R1 of FIG.
53;
[0067] FIG. 56 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIVOS R0,R2 of
FIG. 53;
[0068] FIG. 57 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction MOVT R3 of FIG.
53;
[0069] FIG. 58 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction SUBC R0,R2 of
FIG. 53;
[0070] FIG. 59 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIVOS R1,R2 of
FIG. 53;
[0071] FIG. 60 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIV1 R1,R2 of
FIG. 53;
[0072] FIG. 61 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction MOV R2,R4 of FIG.
53;
[0073] FIG. 62 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction EXTS.W R2,R2 of
FIG. 53;
[0074] FIG. 63 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction ROTCL R2 of FIG.
53;
[0075] FIG. 64 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction ABDC R0,R2 of
FIG. 53;
[0076] FIG. 65 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIVOS R0,R4 of
FIG. 53;
[0077] FIG. 66 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction MOVT R0 of FIG.
53;
[0078] FIG. 67 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction EOR R3,R0 of FIG.
53;
[0079] FIG. 68 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction ROTCR R0 of FIG.
53;
[0080] FIG. 69 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIVOS R1,R4 of
FIG. 53;
[0081] FIG. 70 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction ROTCR R4 of FIG.
53;
[0082] FIG. 71 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction DIV1 R1,R4 of
FIG. 53;
[0083] FIG. 72 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction SR16 R4 of FIG.
53;
[0084] FIG. 73 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction ADD R3,R4 of FIG.
53;
[0085] FIG. 74 is a diagram for explaining the operations of the
circuits of FIG. 51 for executing the instruction EXTS.W R4,R4 of
FIG. 53:
[0086] FIG. 75(A) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 54, FIG. 75(B) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 55, and FIG. 75(C) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 56;
[0087] FIG. 76(D) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 57, FIG. 76(E) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 58, and FIG. 76(F) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 59;
[0088] FIG. 77(G) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 60, and FIG. 77(H)
is a diagram for explaining the state of a register corresponding
to the operations of FIG. 62;
[0089] FIG. 78(I) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 63, FIG. 78(J) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 64, and FIG. 78(K) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 65;
[0090] FIG. 79(L) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 66, FIG. 79(M) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 67, and FIG. 79(N) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 68;
[0091] FIG. 80(O) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 69, FIG. 80(P) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 70, and FIG. 80(Q) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 71;
[0092] FIG. 81(R) is a diagram for explaining the state of a
register corresponding to the operations of FIG. 72, FIG. 81(S) is
a diagram for explaining the state of a register corresponding to
the operations of FIG. 73, and FIG. 81(T) is a diagram for
explaining the state of a register corresponding to the operations
of FIG. 74;
[0093] FIG. 82(A) is a flow chart showing the entirety of a coded
dividing processing explained in FIGS. 54 to 74, and FIG. 82(B) is
a flow chart showing a pre-processing of the same;
[0094] FIG. 83(A) is a flow chart showing the detail of the
division 1 of FIG. 82, and FIG. 83(B) is a flow chart showing the
processing of a division step;
[0095] FIG. 84(A) is a flow chart showing the detail of the
entirety of the post-processing of FIG. 82, and FIG. 84(B) is a
flow chart showing the processing of a quotient correction;
[0096] FIG. 85(A) is a flow chart showing the detail of first
remainder correcting means of the post-processing of FIG. 84, and
FIG. 85(B) is a flow chart showing the processing of second
remainder processing means;
[0097] FIG. 86 is a diagram for explaining one example of an
instruction description for a coded division of 8 bits/8 bits;
[0098] FIG. 87 is a diagram for explaining one example of an
instruction description for a coded division of 64 bits/32
bits;
[0099] FIG. 88 is a diagram for explaining one example of an
instruction description for a coded division of 32 bits/32
bits;
[0100] FIG. 89 is a diagram for explaining one example of an
instruction description for a coded division of 16 bits/16
bits;
[0101] FIG. 90 is a diagram for explaining one example of an
instruction description for a coded division of 16 bits/8 bits;
and
[0102] FIG. 91 is a diagram for explaining one example of an
instruction description for a coded division of 32 bits/16
bits.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0103] The present invention will be described in the following in
connection with the embodiments thereof in the order of items which
are broadly itemized into: a microcomputer adopting an instruction
form a of fixed length having a smaller bit number than that of the
maximum data word length; and coded divisions to be executed by
such microcomputer. The contents of the former will be described
under Items [1] to [17] whereas the contents of the latter will be
described under Items [18] to [24].
[0104] [1] Application System of Microcomputer
[0105] FIG. 1 shows one example of a system which makes use of a
microcomputer MCU according to one embodiment of the present
invention. This microcomputer MCU is coupled through an external
control bus ECB, an external data bus EDB and an external address
bus EAB to an external memory EMRY and an external input/output
block EI/O defined by the user and is further connected with a port
input/output bus PIOB to an external equipment EEQ. This external
equipment EEQ is a predetermined device to package the
microcomputer system.
[0106] [2] Block Structure of Microcomputer
[0107] FIG. 2 shows the microcomputer MCU according to one
embodiment of the present invention. The microcomputer MCU, as
shown, is packaged in a single semiconductor substrate such as a
silicon substrate by the well-known semiconductor integrated
circuit manufacture technology. Reference letters CPU appearing in
the Figure designates a central processing unit for controlling the
microcomputer MCU in its entirety. Letters Port/I/O designate an
input/output port to be used for the central processing unit CPU to
input/output a signal, to drive an external display device and to
inspect the state of an external switch. The central processing
unit CPU inputs/outputs by reading/writing a register assigned to a
certain address. Letters Port/Cont designate a port for an
input/output of the data bus. Letters Port/Address designate a port
for an input/output of the address bus. Letters I/O designate such
a peripheral device on the chip of the microcomputer MCU as
includes a serial communication interface, a timer and so on.
Letters DMAC designate a direct memory access (DMA) controller. A
ROM (Read Only Memory) is an instruction memory packaged on-chip
and stores the instructions (i.e., operation programs) of the
central processing unit CPU and a constant table. A RAM (Random
Access Memory) is a memory packaged on-chip and is used as the
working area of the central processing unit CPU or a primary
storage area for data. Letters BSC designate a bus state controller
for controlling the bus access to the inside and outside of the
microcomputer MCU. Letters CACHE designate a cache memory, i.e., a
storage device for latching an instruction, which is anticipated to
be most frequently used by recognizing the access pattern of an
instruction of the central processing unit CPU, to reduce the
frequency for accessing to an application program or the like from
an external memory having a low access rate, thereby to accelerate
the processing. Letters BURST/REFRESH designate a burst/refresh
device for burst control of a continuous data transfer and for
refresh control of a dynamic random access memory (DRAM) and is
applied to a high-speed page mode access, when the DRAM is used as
an external memory, and to a refreshing of the DRAM. Letters edb
designate an internal data bus coupled through a port Port/Data to
the external data EDB, and letters eab designate an internal
address bus coupled through a port Port/Add to the external address
bus EAB. These two internal buses are not coupled to the central
processing unit CPU. On the other hand, characters IDB31-0
designate internal data buses of 32 bits, and IAB23-0 designate
internal address buses of 24 bits. These two internal buses are
coupled to the central processing unit CPU.
[0108] This central processing unit CPU is given an instruction
from the instruction memory ROM or the cache memory CACHE so that
the data issued from the data memory RAM or the external memory
EMRY are subjected to a predetermined processing in accordance with
the given instruction.
[0109] [3] Pin Arrangement of Package of Microcomputer
[0110] FIG. 3 conceptionally shows a pin arrangement of the package
of the aforementioned microcomputer MCU. In the same Figure, free
running timers FRT0 and FRT1, an analog/digital converter A/D, a
digital/analog converter D/A, and serial communication interfaces
SCI0 and SCI1 exemplify the peripheral circuit I/O of FIG. 2, and
corresponding ports PORT1 to PORT4 shown in FIG. 3 are input/output
ports corresponding to individual peripheral devices and
accordingly to the port Port/I/O of FIG. 2. The microcomputer MCU
is filled in a QFP type package of 112 pins. Address buses (A0-23)
of 24 bits are connected with the aforementioned address bus EAB,
and data buses (D0-31) of 32 bits are connected with the
aforementioned data bus EDB. These buses A0-23 and D0-31 are used
when the central processing unit CPU, the direct memory access
controller DMAC or the burst/refresh control block BURST/REFRESH
accesses the external memory EMRY. Clock signals are those for
specifying the basic timing of the instant when the inside of the
microcomputer MCU and its external systems operate synchronously.
If a not-shown quartz oscillator is coupled to terminals EXTAL and
XTAL, for example, it resonates to oscillate with an electric
circuit in the chip of the microcomputer MCU. This chip detects the
oscillating voltage to generate internally synchronizing clocks
.phi.1 and .phi.2, as will be described hereinafter. These clocks
.phi.1 and .phi.2 are non-overlap clock signals which have neither
of their high periods overlapped, although not especially
limitative thereto. At the same time, the microcomputer MCU outputs
a clock signal having a waveform and a phase substantially
identical to those of the signal .phi.1 from its terminal CLK so as
to synchronize its external system and the inside of the LSI. The
control signal includes: an operation mode setting signal and an
interruption inputting signal such as a reset signal (RES) or a
standby signal (STBY); a data bus control signal such as a read
strobe (RD) or a write strobe (WRHH); or a DRAM refresh control or
bus arbitration signal. Letters Vss and Vcc designate a ground
terminal and a power supply terminal. The port PORT1 inputs/outputs
two channels of the control signal DMAC concerning the direct
memory access controller DMAC. The port PORT2 inputs/outputs the
FRT signal for controlling and reading the free running timers FRT0
and FRT1 from the outside of the microcomputer MCU. The port PORT3
inputs/outputs the analog signals which are fed to the
analog/digital converter A/D and the digital/analog converter D/A.
Reference potentials of the analog/digital converter A/D and the
digital/analog converter D/A are fed from terminals AVcc and AVss.
The port PORT4 inputs/outputs the serial communication signals
which belong to three clock, data transmission and data reception
systems for two channels.
[0111] [4] Instruction Word Length and Data Word Length
[0112] FIG. 4 shows one example of the relation of the data word
length and the instruction word length to a bus width (i.e., the
number of signal lines composing a bus) in the microcomputer MCU of
the present embodiment. This microcomputer MCU has an architecture
of RISC type and an instruction form a of fixed length. The buses
such as internal data buses IDB31-0, through which data and
instructions are transferred, are given 32 bits (corresponding to
32 signal lines). At this time, the bit number of later-described
various registers is 32 bits. The data on a memory are arranged at
the units of byte (of 8 bits), word (of 16 bits) and long word (of
32 bits) in a memory area having a width of 32 bits. Addresses are
assigned at the byte unit to the memory. As a result: the byte data
are accessed at the unit of n addresses (n: an integer); the word
data are accessed at the unit of 2n addresses; and the long word
data are accessed at the unit of 4n addresses. Other memory
accesses are deemed to belong to an address error. On the other
hand, instructions are formatted into an instruction format having
a fixed length of 16 bits (corresponding to 16 signal lines). In
short, an instruction of fixed length is composed of bits of the
n-th power of 2, and the relation of m.gtoreq.n holds, if the
number of signal lines composing the bus width is the m-th power of
2.
[0113] In FIG. 4 showing several examples of the aforementioned
instruction format of fixed length of 16 bits: four bits of "rrrr"
designate an assigned field of a source register: four bits of
"RRRR" designate an assigned field of a destination register; bits
of "d - - - dd" designate a displacement; and bits "ii-i" designate
an immediate data. In an instruction format of 16 bits, the
destination register assigned field RRRR falls at the eighth bit
from the fourth bit with reference to the lefthand side of the
format, and the source register assigned field rrrr falls at the
twelfth bit from the ninth bit. The lefthand four bits of the
instruction format are assigned to at least an operation code
assigned field. The instruction system of the microcomputer MCU
allows the destination register assigned field RRRR to be used as a
portion of the operation code assigned field and the source
register assigned field rrrr to be used as a portion of the
displacement or immediate data.
[0114] Thanks to adoption of the instruction format of fixed length
of 16 bits for the data word length of 32 bits, where the
instruction boundary resides can be decided before the end of a
preceding instruction like the RISC machine of the prior art having
the instruction format of fixed length of 32 bits, thereby to
warrant the advantage such as simplification of the instruction
decoding process. In addition, the program capacity can be made
smaller than that of the case in which the instruction format of
fixed length of 32 bits is adopted. In the RISC architecture
intended to accelerate the execution of instructions by reducing
the number of kinds of instructions, there is a tendency that
undefined operation codes increase in an instruction set. If the
instruction length is reduced at this time to one half of the prior
art, the efficiency of using the program memory can be improved.
Thanks to the reduced instruction word length, as compared with the
data word length, the substantially useless bit array can be made
less than that of the case, in which the two word lengths are
equalized, so that the efficiency of using the program memory can
be enhanced. As a result, the efficiency of using the memory for
storing the program can be improved to keep an application field,
which uses a memory having a limited capacity on the board or a
program memory packaged on-chip in the processor, away from
problems such as shortage in the storage capacity of the program
memory at the time of constructing the system or unavoidably large
scale of the memory. Thus, the system cost can be reduced.
[0115] Since, moreover, the instruction format of fixed length of
16 bits has one half of the data word length and bus width of 32
bits, an instruction misalignment to the program memory such that
an instruction of single format is arranged across the boundary of
the memory (or word) occurs less frequently than the case, in which
the instruction word length is shortened by setting the instruction
word length to a fragmentary bit number (e.g., bit number other
than a power of 2) with respect to the bus width or data word
length.
[0116] [5] Instruction Control System of CPU
[0117] FIG. 5 shows one example of the internal block, i.e., its
instruction control system of the aforementioned central processing
unit CPU. Letters IRH and IRL designate individual instruction
buffers (i.e., instruction queues) of 16 bits for latching
instructions of fixed length of 16 bits one by one. These registers
IRH and IRL are individually loaded with the instructions in one
instruction fetch cycle. This is because the instructions are
transferred at the unit of 32 bits through the internal data buses
IDB31-0. These instructions are loaded in the instruction register
IR1 through a multiplexer MPX. The instruction register IR1 has 16
bits. This instruction register IR1 latches the instruction which
is present at the instruction decode stage. In the instruction
register IR1, with reference to the lefthand end indicated as
"RRRR" in accordance with the instruction format of fixed length of
16 bits, the fifth to eighth bits are caused to belong to the
destination register field, and the ninth to twelfth bits indicated
as "rrrr" are caused to belong to the source register field. These
fields are fixed in the instruction field. At this time, as has
been described hereinbefore, the source register field never fails
to be used for selecting the source operand, and the destination
register field never fails to be used for selecting the second
source operand or destination operand. Each register field may mean
a portion of the operation code or the number of a register.
Whether or not the contents of the register assigned fields RRRR
and rrrr are pieces of information for selecting a register is
determined at the left end of the aforementioned instruction format
of fixed length by the contents of the 1st to 4th bit operations
codes. Nevertheless, the values of the register fields RRRR and
rrrr are inputted to and decoded by a source register decoder SRD
and a destination register decoder DRD through the instruction
register IR2.
[0118] The decoded results by the aforementioned source register
decoder SRD and destination register decoder DRD are used to decide
what of general purpose registers R0H and R0L, - - - , and R15H and
R15L contained in an execution unit for arithmetic operations is to
be selected. On the other hand, the values of the register fields
RRRR and rrrr outputted from the aforementioned instruction
register IR2 are fed through temporary latches WBR0 and WBR1 to a
write back register decoder WBRD so that the arithmetic results
obtained by the instruction executions are written for selecting
the general purpose registers in accordance with the decoded
results. Moreover, the values of the register fields RRRR and rrrr,
i.e., the register numbers latched in the aforementioned temporary
latch WBR1 and being used are fed to a register content check block
RCCB so that they are compared with the outputs of the instruction
registers IR1 and IR2 to find out an even (or register conflict),
in which each instruction, e.g., a subsequent instruction accesses
a common register when the instructions sequentially fetched are
executed in the pipe-line manner. The register conflict is fed to a
flag operation & pipe control decoder FO&PCD in response to
the signal S1. If the signal S1 thus asserted is fed to the flag
operation & pipe control decoder FO&PCD, skip controls are
executed in accordance with the number of instruction execution
cycles being done, to cancel or delay the execution cycles of the
instructions using the conflicting registers. In short, when the
flag operation & pipe control decoder FO&PCD outputs the
control signal Skip, the decoding of the instruction to be
subsequently executed is delayed in the source register decoder SRD
and the destination register decoder DRD. As a result, the
execution cycle of a succeeding instruction is started at a timing
after the writing of the conflicting registers is ended by
executing the preceding instruction.
[0119] The instruction latched by the aforementioned instruction
register IR1 is fed to a mapping control block MCB to index the
addresses of a high-speed control read only memory (i.e., Hardware
Sequence ROM) HSC-ROM. This mapping control block MCB has a role to
calculate the entry address of a proper high-speed control read
only memory MHSC-ROM in accordance with the content. The high-speed
control read only memory HSC-ROM has its output composed of two
portions: a micro code field MCF and a pipe control field PCF,
which are latched by a hardware sequence control instruction
register HIR such as a micro instruction register. The former in
the micro instruction field feeds a control signal to the execution
unit EXEC through a shallow decode logic, i.e., an instruction
decoder ID. The latter establishes the sequence of an instruction
having two or more cycles through the flag operation & pipe
control decoder FO&PCD or controls the pipe line. The flag
operation & pipe control decoder FO&PCD has eight flags C,
W, B, L, M, I, S and S for controlling the pipe lines. Moreover,
this flag operation & pipe control decoder FO&PCD has a
status register SR which has a true bit T (as will be shortly
referred to as "T bit") used for condition branching. This T bit is
set to the truth or false of the arithmetic result of selected
conditions described in the instruction, as will be described
hereinafter.
[0120] The content of the aforementioned instruction register IR1
is transferred before an arithmetic execution phase (EX) to the
instruction register IR2 so that whether or not a conflict is
caused between instructions in the pipe line state of later memory
access phase (MA) and write back phase (WB) is checked through the
aforementioned register content check block RCCB, and this result
is outputted as the signal S1. What is stored at this time in the
instruction register IR2 is the value of the register field. The
values of the register fields RRRR and rrrr latched in the
instruction registers IR1 and IR2, as has been described
hereinbefore, are fed to the aforementioned source register decoder
SRD, destination register decoder DRD and write back register
decoder WBRD. These source register decoder SRD, destination
register decoder DRD and write back register decoder WBRD generates
a selection signal for selecting one pair of the sixteen general
purpose registers R0H and R0L, - - - , and R15H and R15L and feeds
it to the execution unit EXEC.
[0121] The memory interface MIF detects whether or not the central
processing unit CPU has to access a memory and whether the memory
is of the read or write type, and feeds a signal necessary for
accessing the memory. On the other hand, an instruction fetch &
instruction register control block IF&IRC has a function to
determine whether or not an instruction fetch from a memory is
necessary and when the contents of the instruction registers IRH
and IRL are to be updated, and to output a necessary signal. The
function of this instruction fetch & instruction register
control block IF&IRC is to output a predetermined control
signal with reference to the state of the pipe line, the state of
the memory and the state of the instruction queues (IRH and IRL)
thereby to control the instruction queue or the instruction fetch.
What features the present embodiment is that the instruction fetch
is carried out at the unit of 32 bits so that it contains two
instructions having an instruction length of 16 bits. This makes it
unnecessary to fetch again the instruction, which has been fetched
simultaneously as the preceding instruction is fetched, in another
phase. These events are totally judged to control when the
instruction fetch is to be executed. The instruction fetch &
instruction register control block IF&IRC is constructed as an
finite state machine, and a detailed description of the structure
of this machine will be omitted because the structure per se is
well known in the art.
[0122] Incidentally, letters IMB appearing in FIG. 5 designate a
buffer for sending immediate data contained in an instruction to
the execution unit EXEC. Moreover, the instruction queues IRH and
IRL and the latch timing of the instruction register IR1 are
synchronized with the aforementioned clock signal .phi.1. The latch
timings of the instruction register IR2, the micro instruction
register MIR and the registers WBR0 and WBR1 and the output timing
of the signal S1 by the aforementioned register content check block
RCCB are synchronized with the aforementioned clock signal
.phi.2.
[0123] Since the data bus width is 32 bits whereas the fixed length
instruction is 16 bits, there are provided two instruction buffers
IRH and IRL. Despite of this provision, however, the number of
instruction buffers is determined depending upon how many fixed
length instructions can be transferred within the data bus width,
for example: four instruction buffers in case of a fixed length
instruction of 8 bits; and eight instruction buffers in case of a
fixed length instruction of 4 bits.
[0124] [6] Execution Unit of CPU
[0125] FIGS. 6 and 7 show one example of the execution unit EXEC of
the central processing unit CPU. In the two Figures, buses
indicated at A, B, C and D are commonly connected. The execution
unit EXEC includes: an instruction fetch block IFB and a general
purpose block GRB for fetching an instruction and updating a
program counter; an operation block OPB for addition/subtraction
and shift operations; and memory access block MAB and a
multiplication block MULT for accessing a memory and aligning data.
These individual blocks are coupled to one another through the four
data buses A, B, C and D having a width of 32 bits.
[0126] The aforementioned instruction buffers (or instruction
queues) IRH and IRL, multiplexer MPX and instruction register IR1
forming part of the aforementioned instruction fetch block IFB are
shown in the block structure of FIG. 5 separately of the execution
unit EXEC but may be contained in the execution unit EXEC, as shown
in FIG. 6. An immediate buffer IMB is a logic for cutting and
bit-shift, if necessary, immediate data. Letters PCH and PCL
designate program counters for latching addresses for fetching an
instruction. An arithmetic unit high AUH and an arithmetic unit low
AUL are adders capable of performing an addition of 32 bits for
updating the program counters. A procedure address register high
PRH and a procedure address register low PRL are procedure address
registers for latching return addresses for a function call. A
vector base register high VBRH and a vector base register low VBRL
are used as storage areas of an interrupt vector area for latching
the base addresses. A global base register high GBRH and a global
base register low GBRL are used as storage registers for the base
address of the I/O. A break register high BRH and a break register
low BRL are used as storage registers for return destination
addresses from the break routine.
[0127] The aforementioned general purpose register block GRB
includes sixteen general purpose registers of 32 bit length, as
indicated at R0H and R0L to R15H and R15L. In the aforementioned
operation block OPB, a shifter high SFTH and a shifter low SFTL are
hardware for bit shifts and rotations. An arithmetic logic unit
high and an arithmetic logic unit low are operators for arithmetic
logical operations. Letters SWP&EXT designate a hardware for
executing a swap instruction, a code (or sign) extension or a zero
extension. An aligner ALN is a hardware for aligning the data which
are accessed in byte or word from a memory or I/O. A memory read
buffer high MRBH and a memory read buffer low MRBL are temporary
registers for latching the data which are read from a memory. A
memory write buffer high MWBH and a memory write buffer low MWBL
are temporary registers for latching data to be written in a
memory. A memory address buffer high MABH and a memory address
buffer low MABL are temporary registers for latching addresses at
the time of a memory access. A MULT buffer MLTB is a temporary
register for transferring a multiplier and a multiplicant to the
multiplication block MULT.
[0128] The connection relations of the inside and outside of the
central processing unit CPU through the buses are as follows.
Specifically, letters MTBL and MTBH are bilateral special purpose
buses for connecting the multiplication block MULT. In FIGS. 6 and
7, letters IDBH and IDBL correspond to the data buses IDB31-0 of
FIG. 2, and letters IABH and IABL correspond to the address buses
IAB23-0 of FIG. 2. The values of the aforementioned program
counters PCH and PCL are outputted to the address buses IABH and
IABL, and the instruction buffers IRH and IRL fetch the data from
the data buses IDBH and IDBL so that the outputs of the temporary
registers MWBH and MWBL are fed to the data buses IDBH and IDBL.
The temporary registers MRBH and MRBL input the data from the data
buses IDBH and IDBL and the special purpose buses MTBH and MTBL.
The address informations latched by the temporary registers MABH
and MABL are outputted to address buses IABH and IABL. The
multiplying temporary register MLTB has its output fed to the
special purpose buses MTBH and MTBL.
[0129] [7] Pipe Line Stage by CPU
[0130] FIG. 8 shows one example of a stage of a pipe line
processing by the central processing unit CPU. This central
processing unit CPU has a basic pipe line structure of five stages
having the following basic phases:
[0131] IF: Instruction Fetch;
[0132] ID: Instruction Decode;
[0133] Ex: Execute;
[0134] MA: Memory Access; and
[0135] WB: Write-Back.
In FIG. 8 showing one example of the execution content of each pipe
stage, the Address Bus correspond to the address buses IAB23-0 of
FIG. 2, and the Data Bus correspond to the IDB31-0 of the same.
Letters IR of FIG. 8 correspond to the instruction buffers IRH and
IRL of FIGS. 6 and 5. In FIG. 8, letters A-Bus, B-Bus, C-Bus and
D-Bus are the A bus, B bus, C bus and D bus of FIG. 7,
respectively. Likewise, letters MAB and MRB of FIG. 8 are the MABH,
MABL, MRBH and MRBL of FIG. 7.
[0136] [8] Pipe Line Sequence in Register Conflicting State
[0137] The pipe line sequence in the aforementioned register
conflicting state will be described with reference to FIG. 9. First
of all, the meanings of signals shown in the same Figure will be
described in the following. The waveforms of the aforementioned
non-overlap two-phase clock signals .phi.1 and .phi.2 acting as
operation reference clock signals are shown at the top of FIG. 9.
One cycle is defined as a period starting from the rise of the
clock signal .phi.1 and ending the next rise of the signal .phi.1.
Subsequently, the states of an address bus and a data bus are
shown. Next letters IRLatch designate a latch signal of an
instruction buffer (IR(32 bits) or IRH and IRL). The IRLatch
presents an input latch signal waveform of the IR1 register. The
IR1 (16 bits) latches the instruction which is present at an
instruction decode stage. The aforementioned hardware sequence
control instruction register HIR is a register for latching a
partially decoded micro code, a sequence information or a pipe line
control information. Letters Reg. Content Flag appearing in FIG. 9
designate a flag indicating it necessary to check the conflict
between an LOAD instruction and an instruction using the execution
unit EXEC. This conflict is checked in a 4th cycle to set a Content
Flag (or C flag). At the same time, there is set a LOAD Flag (or L
flag) indicating it necessary to load an operand. Likewise, there
is set in the 4th cycle a Bus Cycle Flag (or B flag) indicating a
bus operation necessary. This flag indicates whether or not the bus
cycle is being executed. An instruction fetch inhibit flag (i.e.,
IF Inhibit Flag: I Flag) is one indicating that an instruction
fetch is interrupted and replaced by a data access. A skip signal
(i.e., Skip Sig.) is a flag meaning that a processing to be
executed in the execution unit EXEC in that cycle is canceled. The
Execution indicates a processing to be executed in the execution
unit EXEC. The Reg. Write is a signal to be written in a register.
In response to the Reg. Write in the ordinary operation, the
destination register, as instructed, latches through the C-Bus. At
the time of executing the LOAD instruction and the MULT
instruction, the destination register, as instructed, latches
through the D-Bus. In this meaning, the signal Reg. Write is shown
as divided those for the C-Bus and the D-Bus in the timing chart so
that the writing operation is executed in preference of the C-Bus
if the two signals Reg. Write for the C-Bus and D-Bus conflict in
the same register. In short, only the write from the C-Bus is
executed. The signal written in the 5th cycle, as indicated dotted
lines, indicates the write in the register which is inhibited by
the Skip Sig. The MAB means a memory address bus for outputting an
address when a data access is executed. The MRB Latch meaning a
memory read buffer is a signal for latching data. The PC indicates
the value of a program counter.
[0138] FIG. 9 is a timing chart exemplifying the sequences between
LOAD instructions (LOAD @R1, R2) and ADD instructions (ADD R2, R3).
The register R2 for the LOAD instruction to latch the data and the
register R2 for the ADD instruction to use are so common that the
value of the register R2 is used for the operations between its
value determined if the instruction execution is performed in the
ordinary pipe line flow. In this example, what timing the pipe line
control is to be executed at is shown over seven cycles when the
uses of the registers R2 conflict. The lowermost column indicates
the situations of execution of the pipe line. Since the register R2
of the destination of the LOAD instruction and the source register
R2 of the ADD instruction conflict, a stall (or delay) occurs at
the 5th cycle, as shadowed. For this stall, it becomes necessary at
first to detect whether or not the register conflicting state takes
place and to recognize how many cycle the execution cycle (EX) is
to be delayed for avoiding the register conflict. The former
detection is carried by asserting the signal S1 outputted by the
aforementioned register content check block RCCB for comparing the
register selecting information contained in the preceding
instruction outputted by the aforementioned register WBR1 and the
register selecting information (e.g., the information contained in
the ADD instruction for selecting the register R2 according to this
example) contained in the succeeding instruction. The latter
recognition can be achieved from the decoded result of the
operation code. Since the number of the execution cycle (EX) of the
LOAD instruction is one in the shown example, the stall occurs only
in the 5th cycle.
[0139] FIG. 10 shows another example of the pipe line sequence in
the register conflicting state. FIG. 10 is a timing chart
exemplifying the sequences among the MULT instructions (MUL R1, R2)
as multiplying instructions, the ADD instructions (ADD R4, R3) and
the SUB instructions (SUB R3, R2). The register R2 for the MUL
instruction to latch the data and the register R2 to be used by the
SUB instructions are common. Unless the register conflicting state
is reflected upon the pipe line sequences, it occurs that the
register R2 is used for another operation before its value is
determined if the instruction is executed. In the present example,
what timing the control of the pipe line is executed at in case of
such conflict of register uses is shown over seven cycles. The
format of expression of the present Figure is similar to that of
FIG. 9 and illustrates the executions of multiplications in four
cycles, although not detailed. The MULT instructions are executed
in four stages EX, ML, ML and ML. The multiplier can execute the
multiplications for latching the result of 16 b*16 b in 32 b in the
four cycles. These calculations can be executed by determining the
partial product of 16 b*4 b and their cumulative sum for each
cycle. In case of this example, the SUB instruction is fetched in
the register R1 with a delay of 2 cycles from the MULT instruction,
and the execution cycle (EX) of the SUB instruction is delayed by
two cycles because the MULT instruction are multiplied in the four
cycles EX, ML, ML and ML.
[0140] [9] Pipe Line Sequence at Memory Access Conflicting Time
[0141] FIG. 11 shows a pipe control sequence exemplifying the case,
in which a data fetch from a memory and an instruction fetch
conflict. In this case, the data fetch is preferred so that the
instruction execution schedule containing a conflicting instruction
fetch is shifted in its entirety. For this control, the instruction
fetch wait flag (IF Wait Flag) is set to delay the start of the
instruction fetch cycle while the load flag (LOAD Flag) and the bus
cycle flag (Bus Cycle Flag) are conflicting.
[0142] [10] Sequence of Instruction Execution of Plural Cycles
[0143] FIG. 12 is a timing chart showing one example when a
plurality of cycle instructions are executed. Here will be
explained by way of example an instruction "AND.B #imm, @R1" or a
kind of AND instructions (i.e., logical product). This is an
instruction for calculating the logical product between the 8 bit
data of a memory selected relative to the register R1 and the 8 bit
immediate data. This AND.B instruction is a plurality cycle
instructions to be executed in response to the macro instruction 1,
the micro instruction 1 and the micro instruction 2. The
aforementioned macro instruction 1 is an instruction for fetching a
byte operand from the area of a memory, which is selected according
to the content of the register R1. The aforementioned micro
instruction 1 is an instruction for taking an AND of the
aforementioned byte operand and the immediate data. The
aforementioned micro instruction 2 is an instruction for writing
the byte operand in the area of a memory, which is selected
according to the content of the register R1.
[0144] The execution content of the aforementioned AND.B
instruction is described in the C language:
TABLE-US-00001 ANDM(int i)/*AND.B#imm:8, @R1*/ { long temp;
tenp=(long)Read_Byte(R[1]); temp&=(long)i; Write_Byte(R[1],
temp); PC+=2; }.
With reference to this description, there are idle cycles between
the ID (Instruction Decode) stage and the EX (Execution) stage of
the micro instruction 1 and between the .mu.-IF (Micro Instruction
Fetch) stage and the ID stage of the micro instruction 2. This is
because the operand fetched at the MA (Memory Access) stage of the
macro instruction 1 has to be used at the EX (Execution) stage of
the micro instruction 1.
[0145] [11] Instruction Assignment of CPU
[0146] The instructions to be assigned to the central processing
unit CPU are: data transfer instructions shown in FIGS. 13 and 14;
logical operation instructions shown in FIG. 15; arithmetic
operation instructions shown in FIGS. 16 and 17; shift instructions
shown in FIG. 18; branch instructions shown in FIG. 19; and system
control instructions shown in FIGS. 20 and 21. FIG. 22 explains the
description formats of FIGS. 13 to 21. According to these formats,
the items of the instructions in FIGS. 13 to 21 are mnemonically
indicated. The addressing modes in this mnemonic indications are
tabulated in FIG. 23. As apparent from the various instruction
codes, all of the integer calculations, branching methods and
control instructions of the general purpose register system can be
selected even in the 65,536 combinations which can be expressed in
the instruction format of fixed length of 16 bits. The decoding can
be realized with less logical expressions by devising the bit
assignments to group instructions of similar functions. An
instruction array having the operation code starting from "1111" is
wholly reserved so that calculations of single or double accuracy
can be selected in conformity with the IEEE floating point
standards.
[0147] [12] Displacement Length of Branch Instruction
[0148] FIGS. 24, 25, 26 and 27 plot the relations between the
displacement lengths of branch instructions and instructions in
various programs extracted as samples and the appearance
frequencies of the instructions having those displacement lengths.
FIGS. 24 and 25 relate to conditional branch instructions (i.e.,
branch instructions) and unconditional branch instructions (i.e.,
branch always instructions); FIG. 26 relates to subroutine call
instructions; and FIG. 27 relates to jump instructions or jump
subroutine instructions. Here, the "branch" is to select one of
numerous instruction sets which can be selected in the execution of
a computer program. The "jump" means a departure from the implicit
or specific execution order of instructions, which is actually done
in the execution of the computer program. The "displacement" is
used to select a jumped address. For the more bit number of the
displacement length, therefore, the farther address can be jumped
to.
[0149] The frequency distributions of the displacement in response
to the branch instructions, as shown in FIGS. 24 to 26, are the
data which were obtained by analyzing the various programs of
Microcomputer H8/500 of Hitachi, Ltd. These Figures illustrate the
distributions of the displacement values of the individual kinds of
the branch instructions used. The abscissa indicates the log 2
values of the used displacement values. At the righthand of the
origin 0, the log 2 {i.e., displacement} is expressed by a positive
integer (1, 3, 5, 7, - - - ) in case the displacement value is
positive. At the lefthand, the -log 2 {i.e., -displacement} is
expressed by a negative number for a displacement having a negative
value. The ordinate indicates the appearance frequency at the unit
of %. The data were sampled for nine different programs.
[0150] As could be apparent from FIGS. 24 and 25, the branch
instructions and the branch always instructions having the higher
appearance frequencies are distributed the closer to the center so
that the distribution can be substantially covered with a
displacement of 8 bits. It could also be found that the
distribution of the subroutine call instructions of FIG. 26 can be
wholly covered with a displacement field of 12 to 13 bits although
it is considerably wide. In case of the jump instructions or jump
subroutine instructions shown in FIG. 27, moreover, the value of
the abscissa takes such a displacement as is defined to mean the
difference between the address, at which the jump instruction is
present, and the address of the jump destination. It could be found
that the jump destination is also far.
[0151] In the microcomputer MCU of the present embodiment, the
displacement of the conditional branch instructions is fixed at 8
bits, and the displacement of the subroutine branch instructions
and the unconditional branch instructions is fixed at 12 bits so
that those instructions are confined in the instruction format of
fixed length of 16 bits. In the various branch instructions shown
in FIG. 19, for example: the individual instructions BC, BT and BF
are made to belong to the conditional branch instructions; the
instruction BSR in the same Figure is made to belong to the
subroutine branch instructions; and the instruction BRA is made to
belong to the unconditional branch instructions. The detailed
contents of the individual instructions should be referred to the
description items of instructions, as follows.
[0152] In the modular programming method for preparing a program as
a set of relatively small subroutines (or functions), the
conditional branch instructions will jump within the functions.
Since most functions have a size as large as several hundreds
bytes, the distribution can be substantially covered with the
displacement of 8 bits. On the other hand, the subroutine branch
has a tendency to jump to the outside of a function itself, i.e.,
to a far place so that it requires a displacement of a larger bit
number than that of the condition branch instruction. The
unconditional branch may be used for calling another function at
the last of functions so as to accelerate the program. Since it
seems advantageous that the unconditional branch be handled
similarly to the subroutine branch condition, the bit number of the
displacement is equalized to that of the subroutine branch. Thus,
the fixed assignment of the proper displacement length according to
the kind of the branch instruction contributes to realization of
the instruction format of fixed length of 16 bits without any
substantial trouble.
[0153] [13] Processing of Immediate Data
[0154] In case the instruction format of 16 bit fixed length is
adopted, it is not practical to limit all the immediate values to
16 bits or less in view of the fact that the data word length is 32
bits. In the present embodiment, a method of using the value of a
register such as the program counter PC and the relative address is
adopted so as to select the immediate values of 16 bits or more
within one instruction format.
[0155] The instructions for the immediate processing are
exemplified by the load instructions shown in FIG. 13, such as
MOV.W@(disp, PC)Rn or MOV.L@(disp, PC)Rn. These instructions are
those for storing the immediate data in the general purpose
register Rn. If the data are words/long words, there are referred
to the data in a table stored in the address which is specified by
adding the displacement to the program counter PC. If the data are
words, the displacement is shifted leftward by 1 bit to 9 bits so
that the relative distance from the table is changed from -256 to
+254 bytes. The program counter PC is the head address which is
behind the present instruction by two instructions. This makes it
necessary to arrange the word data at the boundary of 2 bytes. If
the data are the long words, the displacement is shifted leftward
by 2 bits to 10 bits so that the relative distance from the operand
is changed from -512 to +508 bytes. The program counter PC is the
head address which is behind the present instruction by two
instructions, but its less significant 2 bits are corrected to B
and 00. This makes it necessary to arrange the long word data at
the boundary of 4 bytes.
[0156] [14] Implicit Register Selection
[0157] The implicit register selection is said to select a general
purpose register fixed as an operand not-withstanding that no
register selecting field is present in an instruction. The general
purpose register, as specified herein, is used for determining a
memory address, for example, or for storing the data fetched from a
memory. The instruction for this implicit register selection can be
exemplified by the MOV @(disp, R1)R0 or MOV R0, @(disp, R1), as
shown in FIG. 14. As is apparent from the codes corresponding to
the instruction in the same Figure, the instruction contains only
the operation code and the displacement dddddddd of 8 bits but not
the register selecting field. This displacement is used for
determining a memory address together with the value of the
implicitly selected register R1. Thanks to this implicit register
selection, even in an instruction requiring the value of the
register and the displacement, the instruction word length can be
restricted within 16 bits without any reduction in the bit number
required as the displacement,
[0158] [15] Functionally Composite Instruction
[0159] The functionally composite instruction can be exemplified by
a bit operation instruction such as AND.B #imm, @R1 shown in FIG.
15. This instruction is one composed of three instructions for
taking a logical product (i.e., AND operation) between the 8 bit
data of a memory selected relative to the register R1 selected
implicitly like before and the immediate data of 8 bits to execute
the reading of the memory, the AND operation and the write return
of the result of the AND operation in said memory. The operation of
this kind appears highly frequently in controlling the packaged
devices, and the adoption of such functionally composite
instruction in the instruction format of 16 bit fixed length
contributes to an improvement in the code efficienty.
[0160] [16] Truth/False Setting Instruction for Selected
Condition
[0161] An instruction for setting the truth/false of the arithmetic
result for a selected condition can be exemplified by eight kinds
of CMP instructions shown in FIG. 16, for example. These are
instructions for comparing operands to set the comparison result to
the T (True) bit of the aforementioned status register SR. For
example, the instructions as designated at COMP/EQ, Rm and RnFF
compare whether or not the values of the registers Rm and Rn are
equal, and set the T bit to 1, if YES, but clear the same to 0. By
assigning the T bit to the status register so that the operation of
setting the truth/false for the compared result to the T bit may be
executed in response to one instruction of the instruction format
of 16 bit fixed length, the next instruction such as the
aforementioned conditional branch instruction BT for the operation
based on the resultant truth/false may refer directly to the T bit.
Thus, the description of the condition necessary for the arithmetic
result according to the pre-ceding instruction need not be made in
said BT instruction itself so that the area of the displacement
necessary for the BT instruction can be accordingly enlarged in the
limited instruction format of fixed length. As a result, this
structure contributes to realization of the instruction format of
16 bit fixed length.
[0162] [17] List of Instructions
[0163] The featuring ones of the instructions of having the formats
of 16 bit fixed length have been representatively described
hereinbefore. In order to clarify the whole aspect of the
instruction format of 16 bit fixed length, all the instructions of
the microcomputer of the present embodiment will be further
described sequentially in the alphabetical order. The descriptions
of the individual instructions include the names of instructions,
the formats (wherein "imm" and "disp" designate numerical values or
symbols) expressed by the input formats of the assembler, the notes
for using the instructions, the descriptions of the operations
expressed by the C language, the operation examples (indicating the
states before and after the instruction executions) exemplified
assembler-mnemonically, and the codes. Before the descriptions of
the individual instructions, here will be described the register
structures as the programmer's models to be noted when a program is
to be executed, with reference to FIG. 28. The registers as the
programmer's models are exemplified not only by the aforementioned
general purpose registers R0 (i.e., R0H, R0L) to R15 (i.e., R15H,
R15L) but also by control registers such as a status register SR, a
procedure register PR (i.e., PRH, PRL), a global base register GBR
(BGRH, GBRL), a program counter PC (PCH, PCL), a vector base
register VBR (VBRH, VBRL) or a break register BR (BRH, BRL). In the
example of FIG. 28: the register R0 is an accumulator; the register
R1 is an index register; and the register R15 is a stack pointer.
In the status register SR of FIG. 28: the M/Q bit is referred to in
the DIV instruction; the I bit is a mask bit; the sign "-" is a
reserved bit; the D bit is referred to in the PASS instruction; the
C bit is one reflecting on the
carry/borrow/overflow/underflow/shift-out; and the T bit is one
expressing the truth (1) and the false (0), as has been described
hereinbefore.
[0164] The descriptions of the operations, whose contents are
indicated in C, assume the use of the following resources, although
not especially limitative thereto:
[0165] Next, embodiments of the coded divisions to be executed by
using the microcomputer or the like thus far described will be
described in the following.
[0166] [18] Principle of Pre-Processing of Dividend in Coded
Division
[0167] FIG. 29 conceptionally shows the principle of a
pre-processing of a dividend in a coded division according to the
present embodiment. In the coded division expressed by Y
(Quotient)=X (Dividend)/3 (Divisor), for example, the value (X-1),
i.e., the difference obtained by subtracting 1 from the dividend X
is used as a dividend if the dividend is negative. Conceptionally,
the division is processed in the state, in which the coordinate of
the quotient Y is shifted leftward by 1, as shown in the same
Figure. Thus, it is needless unlike the prior art to decide whether
or not the partial remainder is zero, at each time in the course of
the operation for determining the quotient and to provide a
hardware for the decision. When an accurate rest is to be
determined, the rest determined at last is corrected.
[0168] [19] Processing Procedure of Principle Example of Coded
Division
[0169] FIG. 30 shows the processing procedure of a principle
example of the coded division in case the dividend is negative. In
the same Figure, the division of -9/-3 is an example. The number
"-9" is expressed by "110111" in a complement of 2, and the number
"-3" is expressed by "101". Since the dividend is negative, the
value "110110" obtained by subtracting 1 from -9 is used as the
dividend. The code of the quotient is determined (*1) from the
exclusive OR of the code "1" of the dividend and the code "1" of
the divisor. The first calculation of the partial remainder is
executed by adding or subtracting the dividend "110110" and the
value "1101" extended from the code bit of the divisor to the more
significant side (i.e., to the left), while the digits of the code
bits are equalized. The calculation is the subtraction, if the
exclusive OR of the two code bits are 0, and the addition if the
exclusive OR is 1 (*2). The subtraction is executed in case of this
example. As a result, the first partial remainder "000010" is
obtained. The quotient corresponding to the first partial remainder
is given (*3) by the inverted logical value of the exclusive OR
between the most significant bit of the partial remainder and the
code bit of the divisor. Likewise, the quotient bits are
sequentially determined. In case an accurate rest is necessary, the
value 1 is added to the final remainder in accordance with this
example. In case the division is executed while leaving the
dividend at the value "110111" as it is, as shown at the lower hide
in the same Figure, a correct quotient bit is not determined as its
because all the bits of the remainder are set to "0". Therefore,
whether or not all the bits of the partial remainder is "0" is
decided each time the partial remainder is calculated. If YES, the
logical value of the quotient bit has to be inverted. Incidentally,
FIG. 31 shows one example of a coded division in case of
negative/positive, and FIG. 32 shows individual examples of the
coded divisions in cases of positive/positive and
positive/negative.
[0170] [20] Whole Processing Procedure of Coded Division
[0171] FIG. 33 is a general format showing the entirety of the
basic assumptions or processing procedures of a coded division
according to the present embodiment, which seem to have been
schematically understood from the description thus far made.
(1) A correction is made for a dividend. Specifically, the value 1
is subtracted from the dividend, as shown in FIG. 34(A), if the
dividend is negative. This processing could be individually
executed by examining the code of the dividend, but the method of
extracting the code bit of the dividend to subtract the code bit
from the dividend is adopted in the present embodiment. In other
words, the operation of subtracting the code bit or the MSB of the
dividend is adopted as a pre-processing of the division. Since the
MSB of the dividend is 1 if the dividend is negative, the value 1
is subtracted from the dividend. Since the dividend has a MSB of 0
if positive, it is left as it is. Thus, by adopting the processing
of subtracting the MSB from the dividend having the MSB, the
division program can be prepared without considering whether the
dividend is positive or negative. Since, moreover, such decision is
not required, the division processing is speeded up, and still the
better the division itself can be executed by using a common
circuit notwithstanding whether the dividend is positive or
negative.
[0172] Here, the value to be subtracted from the dividend is
understood to have the weight of the LSB of the dividend. The bit
position or digit of the dividend, from which the aforementioned
value "1" is to be subtracted, is the least significant bit (LSB)
of the dividend. The reason why we dare to make such description is
to consider the case, in which the dividend has a fixed point, as
has been described hereinbefore. Moreover, noting that the code bit
is 1 if the dividend is negative and 0 if positive, it is the
subtraction of 1 from the negative dividend if the code bit (i.e.,
the MSB of the dividend) is subtracted from the dividend having the
code bit. This could be deemed as a transformation from the
negative integer expressed in the complement of 2 into the
complement of 1. Thus, the pre-processing for the dividend can be
executed without considering whether the dividend is positive or
negative. FIG. 35 shows the state of transformation, in which the
value 1 is subtracted from a negative integer of 4 bits. Since
extra 1 bit is necessary for transforming the minimum of the
complement of 2 of a finite bit number into a complement of 1, a 1
bit extension is executed if necessary. Since the partial remainder
may be positive, on the other hand, the aforementioned
transformation for the negative integer is extended all over the
integer to introduce an expression of a new integer. An expression
shown in FIG. 36 is adopted within a range of a coded integer of 4
bits, for example. Incidentally, if an arbitrary integer is
expressed by ZZ in the expression, in which the value 1 is
subtracted from that number, the expression ZZ, which has been
subjected to a transformation of subtracting 1 from the integer
using a complement of 2, can be deemed as identical to the
complement of 1 so that it can be expressed by a number 0 or more,
which is smaller by 1 than the intrinsic value. At this time, the
code bit of 0 is 1 as in a negative number.
(2) The code of a quotient is determined from a dividend and a
divisor, as shown in FIG. 34(B). Specifically, the code of the
quotient is predicted from the exclusive OR between the code of the
dividend and the code of the divisor. (3) Quotient bits are made
while determining the partial remainders sequentially. The addition
and subtraction commands for determining the partial remainder are
determined in accordance with FIG. 37(A). Specifically, if the
exclusive OR between the code Q of the partial remainder (or
dividend) and the code M of the divisor is 0, the subtraction is
commanded to subtract the divisor schematically from the partial
remainder (or dividend). If the exclusive OR between the code Q of
the partial remainder (or dividend) and the code M of the divisor
is 1, the addition is commanded to add the divisor schematically to
the partial remainder (or dividend). The quotient bit is obtained,
as shown in FIG. 37(B), by inverting the result of the exclusive OR
between the code bit of the partial remainder after the
aforementioned subtraction or addition and the code bit of the
divisor.
[0173] Here will be described in more detail the method of
calculating the quotient bit. The summed contents of the quotient
bit calculating method are classified into the following a), b), c)
and d), as shown in FIG. 37(B):
a) Case of A/B (A.gtoreq.0, B>0, A and B: complements of 2)
[0174] As is well known in the art, the quotient bit is set to 1,
if the code bit of the partial remainder is 0, and to 0 if the code
bit of the partial remainder is 1.
b) Case of A/B (A.gtoreq.0, B<0, A and B: complements of 2)
[0175] Since the quotient is negative, how to make the quotient bit
is inverted from the case of (a). In short, the quotient bit is set
to 0, if the code bit of the partial remainder is 0, and to 1 if
the code bit of the partial remainder is 1. The quotient is a
complement of 1. The quotient is finally transformed into a
complement of 2, as will be described in a later-described item
(4), if all the quotient bits are determined.
c) Case of A/B (A<0, B<0, A and B: complements of 2)
[0176] The weight 1 of the LSB of the dividend is subtracted in
advance from the dividend having the LSB. Negative expressions of
the dividend and the present embodiment are complements of 1, and
the positive expression is smaller than the intrinsic value by the
weight 1 of the LSB. The code bit MSB is set to 1, if less than 0,
and to 0 if more than 0. Since the quotient is positive, the
quotient bit is set to 1, if the code bit MSB of the present
embodiment is 1, and to 0 if the code bit MSB of the present
embodiment is 0.
d) Case of A/B (A<0, B>0, A and B: complements of 2)
[0177] The weight 1 of the LSB of the dividend is subtracted in
advance from the dividend having the LSB. Negative expressions of
the dividend and the present embodiment are complements of 1, and
the positive expression is smaller than the intrinsic value by the
weight 1 of the LSB. The code bit MSB is set to 1, if less than 0,
and to 0 if more than 0. Since the quotient is negative, how to
make the quotient bit is inverted from that of the case (c). The
quotient bit is set to 1, if the code bit MSB of the present
embodiment is 1, and to 0 if the code bit MSB of the present
embodiment is 0. The quotient is finally transformed into a
complement of 2, as will be described in a later-described item
(4), if all the quotient bits are determined,
(4) The quotient obtained in the aforementioned item (3) may not
always be an accurate value due to its code. This is because the
quotient is a complement of 1 when its code determined in the
aforementioned item (2) is 1. As a result, the final quotient is
determined in accordance with the code of the aforementioned
quotient and the quotient bit. Since the quotient is expressed, if
negative (wherein the code bit of the quotient is 1), by a
complement of 1, as shown in FIG. 38, a correction is executed by
adding 1 to the quotient obtained in the item (3) to transform it
into a complement of 2. Thus, a correct quotient is determined.
Moreover, a remainder correction for the final present embodiment
is executed, as shown in FIG. 38.
[0178] [21] Specific Examples of Coded Division
[0179] FIGS. 39 and 40 show a specific example of the processing
which adopts the aforementioned basic procedures of the coded
division. The shown example is directed to a coded division of
-8/-3, which will be described as using a general purpose register
of 6 bits so as to facilitate their understanding. FIG. 40 shows
the processing to be executed subsequent to the final processing
shown in FIG. 39, and the descriptions in the column direction are
made identical to those of FIG. 39. In these Figures, characters R0
to R4 designate individual general purpose registers of 6 bits, and
letters Q, M and T designate bit flags in the control registers or
status registers. Of these: the letter Q designates the bits for
latching the codes of the dividends or partial remainders; the
letter M designates the bits for latching the codes of the
divisors; and the letter T designates the bits for latching the
quotient bits or carries. At the lefthand ends of the Figures,
there are described the instruction codes and the operands, and the
contents of the general purpose registers and the bit flags are
shown in the corresponding columns. In the descriptions indicating
the contents of the general purpose registers and the bit flags,
the underlined contents mean that they are updated by executing the
corresponding instructions. Letter X designates the bits having
their values unfixed. Under this item, the processing of the coded
division will be sequentially described, and examples of the
symbols to be used in the description will be enumerated in the
following: [0180] .rarw.: to latch; [0181] MSB (Rn): the MSB (Most
Significant Bit) of the register Rn; [0182] LSB (Rn): the LSB
(Least Significant Bit) of the register Rn; [0183] : operator
indicating an exclusive OR; [0184] Rn<<=1: a leftward shift
of the value of the register Rn by 1 bit; [0185] Rn>>=1: a
rightward shift of the value of the register Rn by 1 bit; [0186]
(Q:Rn): a binary number of 7 bits made by adding the Q bit to the
MSB of the register Rn; [0187] (M:Rn): a binary number of 7 bits
made by adding the M bit to the MSB of the register Rn; [0188]
.about.: an operator indicating a negation (bit inversion); [0189]
Clockwise Rotation of (Rn:T): that the value of the register Rn is
shifted rightward while shifting the T bit in the MSB of the
register Rn to latch the LSB of the shifted-out value in the T bit;
and [0190] Counterclockwise Rotation of (Rn:T): that the value of
the register Rn is shifted leftward while shifting the T bit in the
LSB of the register Rn to latch the MSB of the shifted-out value in
the T bit.
(1) EOR R0,R0
[0190] [0191] R0.rarw.0: the values of the register R0 are wholly
set to 0.
(2) SL3 R1
[0191] [0192] the less significant 3 bits (divisor) of the register
R1 are shifted leftward to more significant 3 bits.
(3) DIVOS R0,R2
[0192] [0193] Q.rarw.MSB (R2), M.rarw.MSB(R0)=0, T.rarw.Q M=Q 0=Q.
[0194] Hence, the codes of the dividends are latched in the T
bits.
(4) MOVT R3
[0194] [0195] R3.rarw.T. The codes of the dividends are latched in
the LSB (R3). These codes are required for determining the
rests.
(5) SUBC R0,R2
[0195] [0196] R2.rarw.(R2-T). The complement of 2 is transformed
into a complement of 1. This is equivalent to that the value 1 is
subtracted from the dividend latched in the R2, if the dividend is
negative. As a matter of fact, this processing is to subtract the
value of the code bit MSB of a dividend from the dividend. Hence,
it is needless to detect whether the dividend is positive or
negative, so that a common instruction can be executed in either
case. In other words, there is eliminated the processing flow, in
which a branching is made to subtract 1 if the dividend is
negative.
(6) DIVOS R1,R2
[0196] [0197] Q.rarw.MSB(R2): the code of the dividend is obtained
in the Q bit; [0198] M.rarw.MSB(R1): the code of the divisor is
obtained in the M bit; [0199] T.rarw.Q M: the code of the quotient
is obtained.
(7) DIV1 R1,R2
[0200] The instruction DIV1 R1,R2 between ".arepeat 3" and ".aendr"
is repeated three times.
[0201] In each execution cycle of the instruction DIV1:
[0202] a subtraction instruction is issued for Q M=0, and an
addition instruction is issued for Q M=1;
[0203] the Q bit is obtained by Q.rarw.MSB(R2); the dividend of the
R2 is shifted leftward by 1 bit by R2<<=1; and the T bit (the
code of the quotient at this time) is latched in the LSB of the R2
by LSB(R2).rarw.T;
[0204] the operation is executed according to the
addition/subtraction commands by (Q:R2).rarw.(Q:R2).+-.(M:R1);
and
[0205] the quotient bit is latched in the T bit by T.rarw..about.(Q
M).
[0206] By executing the instruction DIV1 three times: code of the
last partial remainder is introduced into the Q bit; the least
significant bit of the quotient is introduced into the T bit; the
last partial remainder is introduced into the more significant 3
bits of the R2; and the quotient is introduced into the less
significant 3 bits of the same. The code of the quotient obtained
in the T bit by the (6) DIVOS R1,R2 is introduced into the less
significant 3rd bit.
(8) MOV R2,R4
[0207] The R2 is copied to the R4. This is to determined the rest
by making use of the R4.
(9) EXTS.W R2,R2
[0208] The less significant 3rd bit is code-extended to the more
significant 3 bits. This code indicates the code of the
quotient.
(10) ROTCL R2
[0209] The (R2:T) is rotated counterclockwise. Specifically, the
value of the register R2 is shifted leftward while shifting the T
bit in the LSB of the register R2 to latch the MSB of the
shifted-out value in the T bit. As a result, the quotient is
latched in the less significant 3 bits of the R2, and the code of
the quotient is latched in the T bit.
(11) ADDC R0,R2
[0210] A complement of 1 is transformed into a complement of 2 by
R2.rarw.R2+T. Specifically, immediately before execution of this
instruction, the quotient is latched by the R2, and its code is
latched in the T bit. As a result, the complement of 1 is
transformed, if latched by the R2, into the complement of 2 by
adding the value of the T bit to the value of the R2. Since T=0
when the quotient is negative, the value of the R2 is transformed
from the complement of 1 to the complement of 2 by adding the T.
Thus, a correct quotient is determined.
(12) DIVOS R0,R4
[0211] The MSB (the code of the rest) of the R4 is latched in the Q
bit by Q.rarw.MSB(R4);
[0212] The MSB of the R0 (=0) is latched in the M bit by
M.rarw.MSB(R0); and
[0213] the exclusive OR between the Q bit and the M bit, i.e., the
Q bit (the code of the rest) is latched in the T bit by T.rarw.Q
M=Q 0=Q, so that the code of the rest is obtained at the T bit.
(13) MOVT R0
[0214] The code of the rest before correction, which is latched in
the T bit, is latched in the LSB of the R0 by R0.rarw.T. This is
used to correct the rest.
(14) EOR R3,R0
[0215] The result of the exclusive OR between the code of the
dividend and the code of the rest before correction is latched in
the LSB of the R0 by R0.rarw.R3 R0.
(15) ROTCR R0
[0216] By the clockwise rotation of (R0:T), the value of the
register R0 is shifted rightward while shifting the T bit in the
MSB of the register R0 to latch the LSB of the shifted-out value in
the T bit. As a result, the result of the exclusive OR between the
code of the dividend and the code of the rest before correction is
introduced into the T bit.
(16) BF L1
[0217] If the value of the T bit is 0, a branching is made to the
label L1. No correction of the rest is necessary because the codes
of the dividend and the rest are identical for T=0.
(17) DIVOS R1, R4
[0218] The code of the rest before correction is latched in the Q
bit by Q.rarw.MSB(R4);
[0219] The code of the divisor is latched in the M bit by
M.rarw.MSB(R1); and
[0220] The result of the exclusive OR between the Q bit and the M
bit is latched in the T bit by T.rarw.Q M.
(18) ROTCR R4
[0221] By the clockwise of (R4:T), a processing is executed for
negating the leftward shift of the following DIV1 instruction.
(19) DIV1 R1,R4
[0222] A subtraction command is issued for Q M=0, and an addition
command is issued for Q M=1;
[0223] The Q bit is obtained by Q.rarw.MSB(R4); the value of the R4
is shifted leftward by 1 bit by R4<<=1: and the T bit (having
the result of the exclusive OR between the code of the divisor and
the code of the rest before correction at this time) is latched in
the LSB of the R4 by LSB(R4).rarw.T;
[0224] The 7 bits summed of the M bit and the value of the R1 are
added to or subtracted from the 7 bits summed of the Q bit and the
value of the R4 by (Q:R4).rarw.(Q:R4).+-.(M:R1) in accordance with
the decision result for the aforementioned addition/subtraction,
and the result is latched in the Q bit and the R4; and
[0225] The value inverted from the result of that exclusive OR is
latched in the T bit by T.rarw..about.(Q M).
(20) SR3 R4
[0226] The more significant 3 bits (corresponding to the rest) of
the R4 are shifted rightward to the less significant 3 bits of the
R4.
(21) ADD R3,R4
[0227] The R3 latches the code of the dividend. The R4 latches the
rest before correction. Since the code of a dividend is subtracted
from the dividend by the aforementioned instruction (5) of SUBC
R0,R2, the correct rest is obtained at the less significant 3 bits
of the R4 by adding the R3 to the R4, that is, by transforming the
rest, if a complement of 1, into a complement of 2.
(22) EXTS.W R4,R4
[0228] The more significant side of the R4 for latching the
corrected rest in the less significant 3 bits is code-extended to
determine the final rest with the total 6 bits.
[0229] Here in the foregoing descriptions of FIGS. 39 and 40, in
the repetition of three times of the DIV1 instruction, both the
quotient and the rest are latched in the R2, and the value of this
R2 is shifted leftward (R2<<=1) bit by bit at each time of
execution of the DIV1 instruction. If, in this regard, it is
necessary as in the operation method of the prior art to decide
whether or not all the bits of the partial remainder are 0, in case
the dividend is negative, the decision has to be executed
relatively complicatedly by changing at each time the digit
position of the partial remainder to be decided in the R2. In the
operation method, therefore, in which whether or not all the bits
of the partial remainder are 0 has to be decided as in the prior
art in case the dividend is negative, the decision need not be
executed by changing the digit position of the partial remainder at
each time if the quotient and the rest are latched in different
registers. In this modification, on the contrary, the number of
transfer instructions to be executed for latching the quotient and
the rest in the different registers is increased. Since, in case of
the present embodiment, it is needless to decide at each time
whether or not all the bits of the partial remainder are 0, the
number of instructions to be executed can be reduced by latching
both the quotient and the rest in the R2, to facilitate the
speed-up of the processing of the coded division.
[0230] Incidentally: FIGS. 41 and 42 show a specific example of the
processing of a coded division of -8/3; FIGS. 43 and 44 show a
specific example of the processing of a coded division of -9/-3;
FIGS. 45 and 46 show a specific example of the processing of a
coded division of -9/3; FIGS. 47 and 48 show a specific example of
the processing of a coded division of 8/3; and FIGS. 49 and 50 show
a specific example of the processing of a coded division of 8/-3.
These contents are different from those of FIGS. 39 and 40 in the
values of the dividend and the divisor, and their detailed
description will be omitted.
[0231] [22] Operation Unit for Coded Division
[0232] FIG. 51 shows one embodiment of the operation unit capable
of executing the aforementioned coded division. This operation unit
can be grasped as a different expression which is so modified from
the general purpose register block GRB and the operation block OPB
shown in FIGS. 6 and 7 as to facilitate the explanation of the
coded division. In FIG. 51, the operation unit is represented by
five general purpose registers R0 to R4. The register R2 is used to
latch a dividend or partial remainder, and the register R1 is used
to latch a divisor. Numeral 3 designates a control bit register
(i.e., third control bit latch means) for latching the code bit of
a quotient or a quotient bit temporarily. This control bit register
3 will be shortly referred to the "T bit" in the following, Numeral
4 designates a shifter which is made responsive to the command of a
shift control signal to shift in the aforementioned T bit to the
less significant bit or the most significant bit through a selector
circuit 14 and to shift out the most significant bit or the least
significant bit to a selector circuit 15. In response to the
command of a shift control signal, moreover, this shifter logically
shifts either the more significant 16 bits of a 32 bit input to the
less significant 16 bits or the less significant 16 bits to the
more significant 16 bits, and outputs it. Numeral 5 designates a
control bit register (i.e., first control bit latch means) for
playing the role of a bit which is added to a higher bit than the
most significant bit of the dividend or partial remainder. This
control bit register will be shortly referred to as the "Q bit".
Numeral 6 designates a control bit register (i.e., second control
bit latch means) for playing the role of a bit which is added to a
higher bit than the most significant bit of the divisor. This
control bit register 6 will be shortly referred to as the "M bit".
Numeral 7 designates an operation control circuit for instructing
an addition/subtraction to an arithmetic logical operation circuit
8. This numeral 8 designates an arithmetic logical operation
circuit of 32 bits. This arithmetic logical operation circuit 8 can
add or subtract the input of a B port to or from the input of an A
port in accordance with the command of the operation control
circuit 7 and can output the result to a bus linked to the dividend
register R2 or the like, and executes an arithmetic logical
operation with carry or borrow flags. The arithmetic logical
operation circuit 8 is further enabled not only to output the input
MSB (Most Significant Bit) of the B port to the M bit but also to
execute operations such as an addition, a subtraction with carry,
an addition with carry, an exclusive OR (EOR) or a logical AND.
Numeral 9 designates an operation circuit for adding or subtracting
the value of the control bit register 6 to or from the value of the
control bit register 5 together with the carry or borrow of the
arithmetic logical operation circuit 8. Numeral 10 designates can
calculate the negation between the result of the operation circuit
9 and the exclusive OR of the control bit register to output the
result to the selector circuit 12 and can calculate the exclusive
OR between the value of the control bit register 5 and the value of
the control bit register 6 to output the result to the selector
circuit 12. Numeral 11 designates a selector circuit for selecting
the input of the control bit register 5 and for selecting either of
the output from the shifter through the selector circuit 15 or the
output from the operation circuit 9. The numeral 12 designates the
selector circuit for selecting any of the carry or borrow of the
arithmetic logical operation circuit 8, the operation result of the
operation circuit 10 and the output of the selector circuit 15 to
output the selected one to the control bit register 3 or the
operation circuit 9. Numeral 13 designates a selector circuit for
selecting and outputting either of the selector circuit 11 for
selecting the input to the control bit register 5 and the selector
circuit 13 for selecting the input to the operation circuit 9.
Numeral 16 designates a selector circuit for feeding the output of
the control register 3 to the arithmetic logical operation circuit
8 or the selector circuit 14. Numeral 17 designates a code
extension circuit which has its input connected with the B port of
the arithmetic logical operation circuit 8. This code extension
circuit 17 can execute a zero extension, too.
[0233] FIG. 52 shows one example of the arithmetic logical
operation circuit 8, the operation circuit 9, the operation circuit
10 and the operation control circuit 7, which are shown in FIG. 51.
The operation control circuit 7 is constructed, as shown at (b) of
the same Figure, to include a two-input type exclusive OR circuit
and an exclusive OR circuit having two inputs for the output of the
former and a control signal. The operation circuit 7 outputs the
output of the former exclusive OR circuit as it is, if the control
signal is 0, and negates (inverts) and outputs the output of the
former exclusive OR circuit if the control signal is 1. The
operation control circuit 10 is constructed, as shown at (d) in
FIG. 52, to include a two-input type exclusive OR circuit and an
exclusive OR circuit having two inputs for the output of the former
and a control signal. The operation circuit 10 outputs the output
of the former exclusive OR circuit as it is, if the control signal
is 0, and negates (inverts) and outputs the output of the former
exclusive OR circuit if the control signal is 1. As shown at (a) in
FIG. 52, the arithmetic logical operation circuit 8 is equipped
with full adders of 32 bits, as its logics for additions and
subtractions are representatively shown. Characters B00 to B31
designate B port inputs; characters A00 to A31 designate A port
inputs; characters C/B designate carry/borrow; and letters SUB
designate the output of the operation control circuit.
[0234] [23] Examples of Operation of Operation Unit for Coded
Division
[0235] FIG. 53 shows one example of an instruction array for a
coded division. The description shown in the same Figure is to
determine the quotient and the remainder (or rest) by executing a
coded division of 32 bits/16 bits using the circuit shown in FIG.
51. In this division, the dividend of coded 32 bits is latched by
the register R2, and the divisor of coded 16 bits is latched in the
register R1, as expressed in the following:
R2/R1=R2 - - - R4.
The quotient is latched in the register R2, and the remainder is
latched in the register R4.
[0236] FIGS. 54 to 74 show the operations of the circuit of FIG. 51
sequentially when the instructions of FIG. 53 are sequentially
executed, and FIGS. 75 to 81 likewise show the operations
sequentially while stressing the states of the registers. With
reference to these Figures, the operations of the operation units
will be described sequentially at the unit of instruction for the
coded division. Incidentally, in the following description, it is
assumed that the 32 bit data are divided by the 16 bit data, as has
been described hereinbefore. It is also assumed that the dividend
and the divisor are given as complements of 2 having code bits as
their most significant bits and that the quotient is also given as
a complement of 2. In this description, the detection of the
overflow of the quotient is not executed. In case the dividend is
the negative minimum of the complement of 2, the processing
procedure is different from the intended algorithm. In this case,
the overflow never fails to occur so that the quotient is not
warranted. The detection of the overflow is executed, if necessary,
in advance. As the prerequisite for executing the instruction array
of FIG. 53, the 16 bit coded divisor is latched in the register R1,
and the dividend is latched in the register R2. The registers are
used as the working registers. The quotient is latched in the
register R2.
[0237] (1) EOR R0,R0
[0238] As shown in FIGS. 54 and 75, the working register R0 has its
value set to 0 by executing this instruction. This instruction is
not necessary if the value of the R0 is already 0. In FIG. 54, the
shifter 4 and the code extension circuit 17 are not operated to
output the input therethrough. The arithmetic logical operation
circuit 8 takes an exclusive OR between the A port input and the B
port input bit by bit. Thus, all the bits of the value of the
register R0 is set to 0.
[0239] (2) SL16 R1
[0240] As shown in FIGS. 55 and 75, by executing this instruction,
the divisor latched in the divisor register R1 is shifted
(leftward) to a bit more significant by 16 bits, and the value 0 is
shifted in the less significant 16 bits. The leftward shift of 16
bits is executed by the shifter 4. The arithmetic logical operation
circuit 8 outputs the A port input therethrough.
[0241] (3) DIVOS R0,R2
[0242] In response to this instruction, as shown in FIGS. 56 and
75: the MSB of the register R2 is latched in the Q bit; the MSB of
the register R0 is latched in the M bit; and the exclusive OR
between the Q bit and the M bit is latched in the T bit. Since the
value of the register R0 is set to 0 at this time, the T bit
latches the MSB of the dividend latched by the register R2. In this
processing, the shifter 4 feeds the input MSB to the selector
circuit 15. The code extension circuit 17 outputs the input
therethrough. The arithmetic logical operation circuit 8 outputs
the MSB of the B port input. The operation of the exclusive OR
between the Q bit and the M bit is executed by the operation
circuit 10.
[0243] (4) MOVT R3
[0244] In response to this instruction, as shown in FIGS. 57 and
76, the value of the T bit, i.e., the code of the dividend is
latched in the register R3. This is because the code bit of the
dividend is stored for determining the rest. In this processing,
the arithmetic logical operation circuit 8 adds the value of the T
bit to the bit array of 32 bits of each bit 0 and outputs it.
[0245] (5) SUBC R0,R2
[0246] In response to this instruction, as shown in FIGS. 58 and
76, the register R0 is subtracted with carry from the register R2.
The T bit is the carry bit. Since the register R0 is 0, the
complement of 2 is transformed into that of 1 by subtracting the T
bit (i.e., the code bit of the dividend) from the register R2. In
this processing, the shifter 4 and the code extension circuit 17
output their inputs therethrough. The arithmetic logic operation
circuit 8 subtracts the B port input and the C/B input from the A
port input and outputs the subtraction result and the C/B. In other
words, the R0 is subtracted with carry from the dividend register
R2 in response to the SUBC instruction. The carry is recognized as
identical to the control bit register 3. Since the R0 has the value
of 0, the value of the control bit register 3 is subtracted from
the dividend register R2. Thus, the processing of subtracting the
value of the code bit of a dividend from the dividend is ended. As
a result of this processing, the dividend is left as it is, if it
is 0 or more, and is expressed by the complement of 1 if it is
negative. FIG. 35 shows an example exemplifying how the expression
of the dividend is changed by the correction, if the dividend is
negative and of 4 bits. If the aforementioned correction is applied
to the minimum "1000" of the coded complement of 2 of 4 bits, the
expression requires 5 bits such as "10111". Since, in the present
embodiment, the dividend is expressed by a coded complement of 2 of
32 bits, the expression requires 33 bits if the aforementioned
correction is applied to the minimum of the coded complement of 2
of 32 bits. Although the expression can be made with the 33 bits
having the control bit register 3 as the most significant bit, the
present embodiment does not go so far. This is because the case of
an overflow may be detected and precluded in advance, although the
overflow never fails to occur to make it impossible to obtain a
correct quotient if the dividend is the minimum of the coded
complement of 2 of 32 bits.
[0247] (6) DIVOS R1,R2
[0248] In response to this instruction, as shown in FIGS. 59 and
76: the MSB (code bit) of the dividend latched in the register R2
is latched in the Q bit; the MSB (code bit) of the divisor latched
in the register R1 is latched in the M bit; and an exclusive OR
between the Q bit and the M bit is taken and latched as the code of
the quotient in the T bit. This operation is warranted if no
overflow is caused by the execution of the instruction SUBC R0,R2
preceding by one. At this time, the shifter 4 outputs the MSB of
the 32 bit input. The code extension circuit 17 outputs its input
therethrough. The arithmetic logical operation circuit 8 outputs
the MSB of the B port input. The exclusive OR operation is executed
by the operation circuit 10. In response to this DIVOS instruction,
the three control bit registers are initialized. The first operand
of the DIVOS instruction is set with the divisor register R1, and
the second operand is set with the R2, i.e., the dividend register
R2. The DIVOS instruction inputs the first operand to the
arithmetic logical operation circuit 8 to latch the MSB of the
first operand in the control bit register 6. In parallel with this
processing, the DIVOS instruction causes the shifter 4 to shift out
the MSB of the second operand and to latch it in the control bit
register 5 through the selector circuit 15 and the selector circuit
11. The values of the control bit register 5 and the control bit
register 6 are latched even after the end of the DIVOS instruction.
The value of the control bit register 5 is inputted through the
selector circuit 13 ton the operation circuit 10. The value of the
control bit register 6 is inputted to the operation circuit 10.
This operation circuit 10 calculates the aforementioned two input
exclusive ORs and latch the result in the control bit register 3
through the selector circuit 12. The value of the control bit
register 3 is latched even after the end of the DIVOS instruction.
The R1 of the first operand and the R2 of the second operand are
not rewritten.
[0249] This DIVOS instruction causes the code bit of the dividend
to be latched in the control bit register 5, the code bit of the
divisor to be latched in the control bit register 6, and the
exclusive OR of the control bit register 5 and the control bit
register 6 to be latched in the control bit register 3. The values
of the control bit register 5 and the control bit register 6 are
used to decide whether the addition or the subtraction is to be
executed to the first step of a subsequent division. The control
bit register 6 is used as a code extension unit of the divisor in
the subsequent division. The value of the control bit register 3
indicates the code of the quotient. In case this quotient is
negative, it is transformed into a complement of 2 once it has been
determined as a complement of 1. In case the minimum of a 16 bit
coded complement of 2 is the quotient, 17 bits are required for the
expression of a complement of 1. It is the value of the control bit
register 3 immediately after the end of the present DIVOS
instruction that becomes the code bit of the complement of 1 of 17
bits.
[0250] In case the dividend takes the minimum of a 32 bit coded
complement of 2, the dividend register R2 is given the positive
maximum by the aforementioned correction of the subtraction of 1 so
that the value of the control bit register 5 immediately after the
end of the DIVOS instruction is 0. Since the control bit register 5
intrinsically receives the code bit of the dividend, its value
should be 1. In case, therefore, the dividend takes the minimum of
the 32 bit coded complement of 2, the control procedure is
different from that of the intrinsic intention. As has been noted
above, the overflows never fails to occur in case the dividend
takes the minimum of the 32 bit coded complement of 2. However,
this overflow case may be detected in advance and precluded. In the
following, no special consideration is taken into the case, in
which the dividend takes the minimum of the 32 bit coded complement
of 2.
[0251] (7) DIV1 R1, R2
[0252] In the description of FIG. 53, the instruction ".arepeat 16"
is a micro instruction of an assembler, which means that an
instruction between ".arepeat 16" and ".aendr" is extended sixteen
times. Thus, the DIV1 instruction is repeated sixteen times to
effect the substantial division. The R1 of the first operand of the
DIV1 instruction is a divisor register, and the R2 of the second
operand of the DIV1 instruction is a dividend register. In FIGS. 60
and 77, the execution of the DIV1 instruction of one time is
roughly classified into the processings (i), (ii), (iii) and
(iv).
(i) At first, the values of the control bit register 5 and the
control bit register 6 are fetched by the operation control circuit
7 to calculate the negation of the exclusive OR between the two
inputs. This result is fed to the arithmetic logical operation
circuit 8, which latches the value as an operation command. This
operation command is directed to a subtraction, if the result of
the exclusive OR is 1, and an addition if the result is 0. (ii)
Next, the value of the dividend register R2 is inputted to the
shifter 4. The shifter 4 shifts the inputted 32 bits by 1 bit to
the more significant bits. Simultaneously with this, the value of
the control bit register 3 is shifted in the LSB, and the
shifted-out MSB bit is fed through the selector circuit 15 to the
selector circuit 11 and latched in the control bit register 5.
(iii) Next, the 33 bits, which are prepared by adding the control
bit register to the most significant bit of the divisor register
R1, are added to or subtracted from the 33 bits which are prepared
by adding the value of the control bit register 5 to the most
significant bit of the 32 bit output of the shifter 4. An addition
is executed, if the addition command is fed in the processing (i),
and a subtraction is executed if the subtraction command is fed in
the processing (i). The addition/subtraction between the 32 bit
output of the shifter 4 and the value of the divisor register R1
are executed by the arithmetic logical operation circuit 8. As a
result, the carry or borrow established by the arithmetic logical
operation circuit 8 is fed through the selector circuit 12 to the
operation circuit 9. The operation result of the 32 bits obtained
by the arithmetic logical operation circuit 8 is latched in the
dividend register R2. The addition/subtraction between the control
bit register 5 and the control bit register 6 are executed with the
carry or borrow, which was established in the arithmetic logical
operation circuit 8, by the operation circuit 9. The result of the
operation circuit 9 is the code bit of the partial remainder. This
code of the partial remainder is fed in one way to the selector
circuit 11 and latched in the control bit register 5 and is
inputted in the other to the operation circuit 10. (iv) The
operation circuit 10 calculates the negation of the exclusive OR
between the code of the partial remainder and the value of the
control bit register 6. The result is fed to the selector circuit
12 and is latched in the control bit register 3. The value of the
control bit register 3 at this time is the quotient bit.
[0253] Immediately after the DIV1 instruction has been repeated
sixteen times: the last partial remainder is in the control bit
register 5; the least significant bit of the quotient is in the
control bit register 3; the last partial remainder is in the more
significant 16 bits of the dividend register R2; and the more
significant 16 bits of the quotient of 17 bits are in the less
significant 16 bits.
[0254] (8) MOV R2,R4
[0255] In response to this instruction, as shown in FIG. 61, the
value of the register R2 is released to the register R4 so that the
last partial remainder latched in the more significant 16 bits of
the register R2 may not be broken by the means for determining the
quotient.
[0256] (9) EXTS.W R2,R2
[0257] The code of the quotient outputted to the T bit in response
to the aforementioned DIVOS instruction is brought to the position
of the code bit of the less significant 16 bits of the register R2
by repeating the aforementioned DIV1 instruction by sixteen times.
The instruction EXTS.W R2,R2 code-extends the code bit of the less
significant 16 bits to the more significant 16 bits, as shown in
FIGS. 62 and 77. In this processing, the code extension circuit of
FIG. 62 code-extends the less significant 16 bits to 32 bits.
Specifically, in response to the EXTX.W instruction, the codes of
the less significant 16 bits of the dividend register R2 are
extended to the more significant 16 bits. Since the code bit of the
quotient determined in the foregoing processing (6) DIVOS R1,R2 is
latched in the code bit of the less significant 16 bits of the
dividend register R2, this quotient code is extended to the more
significant 16 bits.
[0258] (10) ROTCL R2
[0259] The T bit has the last quotient bit that has been determined
at the sixteenth DIV1 instruction. In response to the ROTCL R2, as
shown in FIGS. 63 and 78, the shifter 4 is used to shift the T bit
in the LSB of the register R2. Simultaneously with this, the value
of the register R2 is shifted leftward to output the shifted out
MSB (code bit) to the T bit. Specifically, the least significant
bit of the quotient latched in the control bit register 3 is
shifted in the dividend register R2. The shifted-out code bit is
latched in the control bit register 3. At this time, the quotient
is latched in the dividend register R2. If the control bit register
3 has the value 0, that is, if the quotient is positive, no
correction is necessary. On the contrary, if the control bit
register 3 has the value 1, that is, if the quotient is negative,
the quotient has to be transformed into a complement of 2 because
it is expressed in a complement of 1.
[0260] (11) ADDC R0,R2
[0261] Immediately before this instruction is executed, the
register R2 latches the quotient, and the T bit latches the code of
the quotient. In response to this ADDC instruction, as shown in
FIGS. 64 and 78, the value of the T bit is added to the value of
the register R2 to transform the complement of 1 latched in the
register R2 into a complement of 2. Because T=0 if the quotient is
positive, the value of the register R2 is not changed even if the T
is added. Because T=1 if the quotient is negative, the value of the
register R2 is transformed from the complement of 1 into the
complement of 2 by adding the T. As a result, a correct quotient is
determined. In this processing, the arithmetic logical operation
circuit 8 subtracts the B port input from the A port input and
further subtracts the T bit (carry/borrow) to latch the borrow in
the T bit. In short, the ADDC instruction is an addition
instruction with carry. The control bit register 3 is recognized as
identical to the carry, and the ADDC instruction adds the register
R0 having the value 0 and the control bit register 3 to the
dividend register R2. The value of the dividend register R2 is
unchanged from that before the execution of the ADDC instruction,
if the control bit register 3 has the value 0, but the quotient
latched in the dividend register R2 is transformed from the
complement of 1 into the complement of 2 if the control bit
register 3 has the value 1. As a result, a correct quotient can be
obtained.
[0262] In FIG. 53, the following instructions DIVOS to EXTS.W of
the aforementioned instruction ADDC are necessary for determining
the rest.
[0263] (12) DIVOS R0,R4
[0264] This instruction is to latch the MSB (code of the rest) of
the register R4 in the T bit. Specifically: the MSB of the register
R4 is introduced into the Q bit; the MSB of the register R0 is
introduced into the M bit; and the exclusive OR between the Q bit
and the M bit is introduced into the T bit, as shown in FIGS. 65
and 78. Since the register R0 has the value 0 at this time, as has
been described hereinbefore, the M bit is 0, and the value (code of
the rest) of the Q bit is introduced as it is into the T bit. In
this processing, the shifter 4 outputs the MSB of the input to the
Q bit. The code extension circuit 17 outputs its input
therethrough. The arithmetic logical operation circuit 8 outputs
the MSB (code bit) of the B port input as the M bit. The operation
circuit 10 takes and outputs the exclusive OR of the two
inputs.
[0265] (13) MOVT R0
[0266] In response to this instruction, as shown in FIGS. 66 and
79, the value (code of the rest before correction) of the T bit is
latched in the register R0. In this processing, the arithmetic
logical operation circuit 8 adds the value of the T bit to the 32
bit data of all bits and outputs the addition to the register
R0.
[0267] (14) EOR R3,R0
[0268] In response to this instruction, as shown in FIGS. 67 and
79, an exclusive OR is taken between the content of the register R3
and the content of the register R0. In this processing, the shifter
4 and the code extension circuit 17 output their inputs
therethrough. The arithmetic logical operation circuit 8 takes an
exclusive OR for each bit between the A port input and the B port
input and outputs it to the register R0.
[0269] (15) ROTCR R0
[0270] In response to the aforementioned instruction EOR, the LSB
of the register R0 is set to 1, if the code of the dividend and the
code of the rest (before correction) are different, and to 0 if the
codes are identical. In response to the instruction ROTCR R0, as
shown in FIGS. 68 and 79, the LSB of the register R0 is latched in
the T bit. In this processing, the shifter 4 shifts the value of
the register R0 leftward, while shifting the T bit in the MSB, and
latches the shifted-out LSB in the T bit. The arithmetic logical
operation circuit 8 outputs the A port input therethrough.
[0271] (16) BF L1
[0272] This instruction instructs that the value of the T bit is
branched, if at 0, into an instruction having the label L1, and
that the next instruction DIVOS of this BF instruction is executed
if the value of the T bit is at 1.
[0273] (17) DIVOS R1,R4
[0274] This instruction causes the rest to be corrected together
with the instruction ROTCR and the instruction DIV1, which are to
be executed subsequent to that instruction. At this time, the rest
before correction is latched in the more significant 16 bits of the
register R4, and the divisor is latched in the more significant 16
bits of the register R1. An addition is executed, if the codes of
the two are different, and a subtraction is executed if identical.
Thus, in response to said DIVOS instruction, as shown in FIGS. 69
and 80, the code of the rest (before correction) is latched in the
Q bit, and the code of the divisor is latched in the M bit so that
they may be used for deciding the addition/subtraction in the
later-described instruction DIV1. The T bit latches the result of
an exclusive OR between the Q bit and the M bit. In this
processing, the shifter 4 outputs its input MSB to the Q bit. The
code extension circuit 17 outputs its input therethrough. The
arithmetic logical operation circuit 8 outputs the MSB (code bit)
of the B port input. The operation circuit 10 takes and outputs an
exclusive OR between the two inputs.
[0275] (18) ROTCR R4
[0276] In response to the later-described instruction DIV1, for an
addition or subtraction after the leftward shift, the value of the
register R4 is rotated clockwise to cancel that leftward shift.
This state is shown in FIGS. 70 and 80. In this processing, the
shift shifts the value of the register R4 rightward while shifting
the T bit in the MSB and latches the shifted-out LSB as the T bit.
The arithmetic logical operation circuit 8 outputs the A port input
therethrough.
[0277] (19) DIV1 R1,R4
[0278] This instruction DIV1 is roughly classified into the
following processings (i), (ii), (iii) and (iv), as shown in FIGS.
71 and 80.
(i) At first, the Q bit of the control bit register 5 and the M bit
of the control bit register 6 are fetched in the arithmetic control
circuit 7 to calculate the negation of the exclusive OR of the two
inputs. This result is fed to the arithmetic logical operation
circuit 8, which latches that value as an operation command. This
operation command is a subtraction command, if the result of the
aforementioned exclusive OR is 1 (i.e., if the code of the rest
before correction and the code of the divisor are identical), and
an addition command, if the same is 0 (i.e., if the code of the
rest before correction and the rest of the divisor are different).
(ii) Next, the value of the register R4 is inputted to the shifter
4. This shifter 4 shifts the value of the register R4 leftward by 1
bit, while shifting the T bit in the LSB of the value of the
register R4, and latches the shifted-out MSB in the Q bit. (iii)
Next, the 33 bits of the addition of the M bit and the value of the
register R1 are added to or subtracted from the 33 bits of the
addition of the Q bit and the value of the register R4, and the
result is latched in the Q bit and the register R4. The
addition/subtraction between the output of the shifter 4 and the
value of the register R1 are executed by the arithmetic logical
operation circuit 8. As a result, the carry or borrow established
by the arithmetic logical operation circuit 8 is fed through the
selector circuit 12 to the operation circuit 9. This operation
circuit 9 inputs that carry/borrow and executes the
addition/subtraction of the Q bit and the M bit in accordance with
the carry/borrow. (iv) The operation circuit 10 calculates the
negation of the value calculated by the aforementioned operation
circuit 9, i.e., an exclusive OR between the Q bit and the M bit.
This result is latched through the selector circuit 12 in the T
bit.
[0279] (20) SR16 R4
[0280] In response to this instruction, as shown in FIGS. 72 and
81, the more significant 16 bits (corresponding to the rest) of the
register R4 are shifted rightward to the less significant 16 bits
of the register R4. The shift processing is executed by the shifter
4.
[0281] (21) ADD R3,R4
[0282] The register R3 latches the code of the dividend in response
to the aforementioned instruction MOVT R3. Since the code (MSB) of
the dividend is subtracted from that dividend in response to the
aforementioned instruction (5) SUBC R0,R2, the rest latched in the
register R4 may have to be corrected so as to determined the
correct rest. In response to the instruction ADD R3,R4, the code
(R3) of the dividend is added to the rest before correction. In
this processing, s shown in FIGS. 73 and 81, the shifter 4 and the
code extension circuit 17 output their individual inputs
therethrough. The arithmetic logical operation circuit 8 adds the B
port input to the A port input and outputs the addition result and
the carry. The addition result is latched in the register R4, and
the correct rest is latched in the less significant 16 bits of said
register R4.
[0283] (22) EXTS.W R4,R4
[0284] In response to this instruction, as shown in FIGS. 74 and
81, the more significant side of the register R4 having the correct
rest latched in the less significant 16 bits is code-extended to
determine the final rest of whole 32 bits. In this processing, the
code extension circuit 17 extends the code at the 16th bit from the
less significant side of the input to the more significant 16 bits.
The arithmetic logical operation circuit 8 outputs the B port input
therethrough toward the register R4.
[0285] The coded division processing having been described with
reference to FIGS. 54 to 74 is roughly classified, if summarized in
a flow chart, into the pre-processing, division 1 and
post-processing, as shown in FIG. 82(A), and the processing of the
aforementioned division 1 is to repeat the division step sixteen
times, as shown in FIG. 83(A). The content of the pre-processing is
shown in FIG. 82(B); the content of the processing of the division
step is shown in FIG. 83(B); and the content of the post-processing
is shown in FIG. 85. In this post-processing, there are executed a
quotient correction, first partial remainder correction means, and
second partial remainder correction means. The processing of the
quotient correction is shown in FIG. 84(B); the first partial
remainder correction means is shown in FIG. 85(A); and the second
partial remainder correction means is shown in FIG. 85(B). The
contents of the individual flow charts will be easily understood
from the description thus far made, although any further
description is not made.
[0286] The quotient and the rest are latched in the common register
R2 in the example according to the instruction description of FIG.
53 but may be latched in different registers. If the quotient is to
be latched in the not-shown register R5, for example, in the
description of FIG. 53, the instruction MOV R0,R5 is inserted to
the next of the instruction EOR R0,R0, and the instruction ROTCL R5
is inserted before the instruction DIV1 R1,R2 so that these
instructions DIV1 R1,R2 and instruction ROTCL are repeated sixteen
times. Then: the instruction EXTS.W R2,R2 may be changed into the
instruction EXTS.W R5,R5; the next instruction ROTCL R2 may be
changed into the instruction ROTCL R5; and the next instruction
ADDC R0,R2 may be changed into the instruction ADDC R0,R5.
[0287] Incidentally, FIGS. 86 to 91 show other examples of
modification of the instruction description for the coded division.
These modes omit the description of the correction processing
relating to the rest. The SL8 Rn instruction is one for shifting
the register Rn leftward by 8 bits. The individual bits of the less
significant 8 bits of the Rn after the instruction execution are 0.
The EXTS.B Rn,Rm instruction is one for code-extending the less
significant 8 bits of the Rn to 32 bits and to latch the 32 bits in
the Rm. These contents will be easily understood from the
description of the foregoing embodiments although no detailed
description is made.
[0288] [24] DIVOS/DIVOU/DIV1 (Step Division) Instruction
[0289] Here will be described the DIVOS instruction used in the
foregoing description, and the examples of the operation and use of
the DIV1 instruction. The contents to be described share the
prerequisites in the aforementioned item [17] List of Instructions.
However, these contents are different in detail in the operation
examples expressed by the C language from the DIV1 instruction
contained in the Item.
TABLE-US-00002 Format: DIV1 Rm,Rn DIVOS Rm,Rn DIVOU Description:
The content of 32 bits of the general purpose register Rn is
divided at one step with the content of the Rm, and the result of 1
bit is latched in the T bit. The instruction DIVOS is a coded
division ini- tialization instruction for latching the MSB of the
dividend (Rn) in the Q bit, the MSB of the divisor (Rm) in the M
bit, and the EOR of the M bit and the Q bit in the T bit. The DIVOU
instruction is a codeless division initialization instruction for
clearing the M/Q/T bits to 0. The quotient is obtained by releas-
ing the instruction DIV1 (in combination with the ROTCL, if
necessary) by the number of bits of the di- visor. During this
repetition, an intermediate result is latched in the assigned
register and the M/Q/T bits. If these are unnecessarily rewritten
by a soft- ware, the operation result cannot be warranted. There
are not prepared the detection of a zero division and an overflow
and the operation of the partial remain- der. The division sequence
can be referred to the following examples of use. Operation: extern
unsigned char Q,M,T; extern unsigned long PC,R[16] DIVOU( ) /*
DIVOU */ { M=Q=T=0; PC+=2; } DlVOS(long m, long n) /* DIVOS Rm,Rn
*/ { if ((R[n] & 0x80000000)==0) Q=0; else Q=l; if ((R[m] &
0x80000000)==0) M=0; else M=1; T=!(M==Q); PC+=2; } DIV1(long m,long
n) /* DIV1 Rm,Rn */ { unsigned long tmp0; unsigned char old_q,
tmp1; old_q=Q; Q=(unsigned char)((0x80000000 & R[n])!=0);
R[n]<<=1; R[n] | =(unsigned long)T; switch (old_q){ case 0:
switch(M){ case 0: tmp0=R[n]; R[n]-=R[m]; tmp1=(R[n]>tmp0);
switch(Q){ case 0: Q=tmp1; break; case 1: Q=(unsigned
char)(tmp1==0); break; } break; case 1: tmp0=R[n]; R[n]+=R[m];
tmp1=(R[n]<tmp0); switch(Q){ case 0: Q=(unsigned char)(tmp1==0);
break; case 1: Q=tmp1; break; } break; } break; case 1: switch(M){
case 0: tmp0=R[n]; R[n]+=R[m]; tmp1=(R[n]<tmp0); switch(Q){ case
0: Q=tmp1; break; case 1: Q=(unsigned char)(tmp1==0); break; }
break; case 1: tmp0=R[n]; R[n]-=R[m]; tmp1=(R[n]>tmp0);
switch(Q){ case 0: Q=(unsigned char)(tmp1==0); break; case 1:
Q=tmp1; break; } break; } break; } T=(Q==M); PC+=2; } Example 1 of
Use: R1(32bits) + no code R0(16bits) = R1(16bits): SL16 RO; divisor
is set to the more sig- nificant 16 bits, and the less significant
16 bits is set to 0. TEST R0,R0; zero division is checked. TEST
R0,R0 is an instruction for set- ting the T bit to 1, if the OR
between R0 and R0 is 0, and to 0 if 1. BT ZERO_DIV; branches into
ZERO_DIV, if T = 0. CMP/HS R0,R1; overflow is checked. T bit is set
to 1 if R0 .ltoreq. R1 without code. BT OVER_DIV; DIVOU;
initialization of flag .arepeat 16; DIV1 R0,R1; repeat 16 times
.aendr; ROTCL R1; EXTU.W R1,R1; R1 = quotient Example 2 of Use:
R1:R2(64bits) + no code R0(32bits) = R2(32bits): TEST R0,R0; zero
division is checked. BT ZERO_DIV; CMP/HS R0,R1; overflow is
checked. BT OVER_DIV; DIVOU; initialization of flag .arepeat 32;
ROTCL R2; repeat 32 times DIV1 R0,R1; .aredr; ROTCL R2; R2 =
quotient Example 3 of Use: R1(16bits) + no code R0(1.6bits) =
R1(16bits): SL16 R0; divisor is set to the more sig- nificant 16
bits, and the less significant 16 bits is set to 0. EXTS.W R1,R1;
dividend is code-extended to 32 bits. EOR R2,R2; R2 = 0 DIVOS
R2,R1; SUBC R2,R1; decremented by -1 if dividend is negative. DIVOS
R0,R1; initialization of flag .arepeat 16; DIV1 R0,R1; repeat 16
times .aendr; EXTS.W R1,R1; R1 = quotient (expression of com-
plement of 1) ROTCL R1; ADDC R2,R1; incremented by +1, if code bit
of MSB of quotient is at 1, and transformed into expression of
complement of 2. EXTS.W R1,R1; R1 = quotient (expression of com-
plement of 2) Example 4 of Use: R2(32bits) + no code R0(32bits) =
R2(32bits): EOR R3,R3; DIVOS R3,R2; SUBC R1,R1; dividend is
code-extended to 64 bits (R1: R2) SUBC R3,R2; decremented by -1 if
dividend is negative. DIVOS R0,R1; initialization of flag .arepeat
32; ROTCL R2; repeat 32 times DIV1 R0,R1; .aendr; ROTCL R2; R2 =
quotient (expression of com- plement of 1) ADDC R3,R2; incremented
by +1, if code bit MSB of quotient is at 1, and transformed into
expression of complement of 2. ; R2 = quotient (expression of com-
plement of 2)
[0290] Although our invention has been described specifically in
connection with the embodiments thereof, it should not be limited
thereto but can naturally be modified in various manners without
departing from the scope thereof.
[0291] For example, the data word length and the bit number of the
fixed length instruction format should not be limited to the data
word length of 32 bits and the 16 bit fixed length instruction
format but can be individually modified by bit numbers of powers of
2. The coded division can also be applied to the 32 bit 3-operand
RISC instruction. The control for the coded division can be
executed by not only the microprogram method but also a wired logic
forming a special purpose operation circuit. If, in the coded
division, there is no special instruction such as the
aforementioned DIV1 instruction, this situation can be coped with
by forming a similar processing into a subroutine in response to
another instruction.
[0292] Although the description thus far made is directed to the
case in which our invention is applied to a microcomputer having a
program ROM packaged therein and presenting the field of
application backgrounding the invention, the invention should not
be limited thereto but can also be applied widely to a
microcomputer containing neither the program ROM nor its peripheral
circuit. In addition, the foregoing descriptions have been
described in case the coded division is applied to the non-recovery
method, but they can naturally be applied to the recovery
method.
[0293] The effects to be obtained by the representatives of the
invention disclosed herein will be briefly described in the
following.
(1) In a microcomputer adopting the general purpose register
method, there is adopted a fixed length instruction format which
has a smaller bit number than that of the maximum data word length
fed to instruction execution means. As a result, there is achieved
an effect that it is possible to provide a microprocessor which has
a small program capacity or a high using efficiency of program
memory and a low system cost while enjoying the advantage of
simplification of such an instruction decoding as exemplified in
the RISC machine of the prior art having a fixed length instruction
format of 32 bits or the like. (2) The fixed length instruction
format and the maximum data word length are set to a bit number of
a power of 2 so that the maximum data word length is 32 bits, for
example, the instruction format is fixed to 16 bits. Thus, another
effect achieved is that either the instruction or the data can be
extended over the ROM/RAM having an identical bit structure while
pre-venting the misalignment of the program on the memory and
holding the consistency with the general memory commercially
available. (3) When the aforementioned fixed length instruction
format and the aforementioned maximum data word length are to be
individually set to the bit numbers of powers of 2, a plurality of
instructions efficiently can be efficiently fetched by the use of
an internal bus of a bit number equal to that of the maximum data
word length, and the bus access number for the instruction fetch
can be reduced by prefetching the instructions in a common cycle.
(4) In case the internal bus is shared between the data transfer
and the instruction fetch, the pipe control is executed to prefer
the data fetch thereby to delay the whole instruction execution
schedule including an instruction fetch conflicting with that data
fetch, if the data fetch and the instruction fetch for the memory
conflict. (5) A further effect achieved is that the restriction on
the bit number of the fixed length instruction format is enabled
not to limit the use of immediate data by supporting the
instruction-containing a description for assigning the immediate
data in a data relation for offsetting the value of a displacement
relative to the value of a predetermined register. (6) A further
effect achieved is that, even in the fixed length instruction
format having a restricted bit number, the displacement necessary
for the processing or the bit number of the immediate data can be
maximized by supporting an instruction for implicitly assigning a
predetermined general purpose register which is fixed as an operand
despite of no register assigning field in the instruction. (7) A
further effect achieved is that the displacement necessary for the
processing or the bit number of the immediate data can be
maximized, even for the fixed length instruction format having a
limited bit number, by supporting an instruction containing a
description for reflecting the truth or false of the arithmetic
result for a specified condition upon a predetermined status flag.
(8) Thanks to these effects, it is possible to solve the various
problems accompanying the adoption of the fixed length instruction
format having a smaller bit number than that of the data word
length. For example: neither the use of immediate data nor the
assignment of an absolute address is restricted even if the bit
number of the fixed length instruction format is less than that of
the data word length; a description such as a necessary
displacement can be executed in the fixed length instruction format
having a limited bit number; a contribution is made to the
prevention of a misalignment of the program arrangement on a
memory; that the code efficiency or memory using efficiency is
improved better from the standpoint of the content of a supporting
instruction. (9) The conflicting state between the uses of the
general purpose registers in response to the instructions before
and after the pipe-line execution making use of the general purpose
register method, can be simply coped with by detecting the register
conflicting state in the general purpose register on the basis of
the information of a register assigned area contained in the
instruction format and by adopting the pipe-line control means for
relatively delaying execution of the subsequent instructions on the
basis of the detection result and the instruction execution cycle
number. (10) For a 16 bit fixed length instruction format, the
displacement of a condition branching instruction is fixed at 8
bits, and the displacements of a subroutine branching instruction
and an unconditional branching instruction are fixed to 12 bits. As
a result, a proper branching destination can be assigned according
to the kinds of the branching instruction without exerting
substantial affections upon the actual operation while the
instruction format length being restricted. (11) In case a dividend
is negative, a preliminary processing is executed by subtracting
the value "1" having a weight of the LSB of a dividend from the
dividend itself so that the division can be executed with the codes
unlike the prior art, in which whether or not the partial remainder
is 0 is decided at each time. As a result, the division can be
executed at a high speed. In other words, effects similar to or
better than those of the prior art, in which the division is
speeded up by providing a special purpose hardware for deciding
whether or not the partial remainder is 0 at a shorter number of
steps, can be realized without increasing the scale of the
hardware. (12) In case a division with codes of multiple length (or
arbitrary length) is to be executed in the prior art for deciding
whether or not the partial remainder is 0 at each time, the
decision of partial remainder=0 has to be executed in accordance
with the bit number (e.g., 8 bits, 18 bits, 32 bits or 64 bits) of
the partial remainder so that the amounts of the software and
hardware will increase in proportion to that bit number. In this
regard, since the present invention requires no decision of partial
remainder=0, the multi-length (or arbitrary length) coded division
or the coded decision of arbitrary length and arbitrary accuracy
can be easily coped with out increasing the software amount and the
hardware amount. (13) By adopting the operation of subtracting the
code bit or the MSB of the dividend as a pre-processing of the
division, the division program can be prepared without considering
whether the dividend is positive or negative. Since such decision
is not required, the dividing speed can be raised, and the division
itself can be executed by making use of a common circuit despite
whether the dividend is positive or negative. (14) Since the
decision of excess subtraction or addition of the divisor to or
from the partial remainder and the calculation of the quotient bit
can be executed only from the MSB of the dividend or the partial
remainder and the MSB of the divisor, the hardware for the division
can be further simplified. Since, moreover, the decision of excess
subtraction or addition of the divisor from or to the partial
remainder, the decision of the addition/subtraction and the
calculation of the quotient bit can be executed only from the MSB
of the divided or the partial remainder and the MSB of the divisor,
an easy application can also be made to the division of arbitrary
length. Since, still moreover, the decision of the
addition/subtraction at the division step can be executed only by
the MSB, the common division step can be used for the coded and
codeless divisions by initializing the division. (15) When the
quotient and rest are to be latched in a single dividend register
while being shifted, the decision of partial remainder=0 has to be
executed in the prior art by changing the digit positions of the
partial remainder to be decided, at each time. On the basis of this
fact, the prior art is restricted by the complicated processing and
an elongated processing time. However, the present invention is
subjected to neither such restriction nor another restriction, in
which the transfer instructions to be executed for latching the
quotient and the rest in different registers are increased. As a
result, the coded division can be further speeded up with ease.
* * * * *