U.S. patent application number 12/193811 was filed with the patent office on 2008-12-18 for epitaxial wafers, method for manufacturing of epitaxial wafers, method of suppressing bowing of these epitaxial wafers and semiconductor multilayer structures using these epitaxial wafers.
This patent application is currently assigned to NGK Insulators, Ltd.. Invention is credited to Takashi Egawa, Masahiro Sakai, Mitsuhiro Tanaka.
Application Number | 20080308909 12/193811 |
Document ID | / |
Family ID | 34117898 |
Filed Date | 2008-12-18 |
United States Patent
Application |
20080308909 |
Kind Code |
A1 |
Sakai; Masahiro ; et
al. |
December 18, 2008 |
EPITAXIAL WAFERS, METHOD FOR MANUFACTURING OF EPITAXIAL WAFERS,
METHOD OF SUPPRESSING BOWING OF THESE EPITAXIAL WAFERS AND
SEMICONDUCTOR MULTILAYER STRUCTURES USING THESE EPITAXIAL
WAFERS
Abstract
A technique for suppressing the bowing of an epitaxial wafer is
provided. The epitaxial wafer is prepared by successively
epitaxially growing a target group III-nitride layer, an interlayer
and another group III-nitride layer on a substrate with a buffer
layer. The interlayer is mainly composed of a mixed crystal of GaN
and InN expressed in a general formula (Ga.sub.xIn.sub.y)N
(0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, x+y=1) (or a crystal of
GaN), and does not contain Al. The interlayer is epitaxially formed
at a lower growth temperature than those of the group III-nitride
layers, more specifically at a temperature in a range of at least
350.degree. C. to not more than 1000.degree. C.
Inventors: |
Sakai; Masahiro;
(Nagoya-Shi, JP) ; Tanaka; Mitsuhiro; (Handa-Shi,
JP) ; Egawa; Takashi; (Nagoya-Shi, JP) |
Correspondence
Address: |
BURR & BROWN
PO BOX 7068
SYRACUSE
NY
13261-7068
US
|
Assignee: |
NGK Insulators, Ltd.
Nagoya City
JP
|
Family ID: |
34117898 |
Appl. No.: |
12/193811 |
Filed: |
August 19, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10909477 |
Aug 2, 2004 |
|
|
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12193811 |
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Current U.S.
Class: |
257/615 ;
257/E21.09; 257/E21.108; 257/E29.089; 428/212; 438/483 |
Current CPC
Class: |
H01L 21/0242 20130101;
H01L 21/02458 20130101; H01L 21/02576 20130101; H01L 21/0254
20130101; H01L 21/02579 20130101; C30B 29/403 20130101; Y10T
428/24942 20150115; C30B 25/20 20130101; H01L 21/0237 20130101;
H01L 21/0262 20130101; H01L 21/02661 20130101; H01L 21/02505
20130101 |
Class at
Publication: |
257/615 ;
428/212; 438/483; 257/E29.089; 257/E21.09 |
International
Class: |
H01L 29/20 20060101
H01L029/20; B32B 7/00 20060101 B32B007/00; H01L 21/20 20060101
H01L021/20 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 4, 2003 |
JP |
2003-205728 |
Jun 16, 2004 |
JP |
2004-178644 |
Claims
1. An epitaxial wafer comprising: a) a substrate; b) at least two
group III-nitride layers epitaxially formed on said substrate; and
c) at least one group III-nitride interlayer, which substantially
does not contain Al, epitaxially formed directly between and in
contact with each of said at least two group III-nitride layers;
wherein said at least one group III-nitride interlayer has a lower
crystallinity than said at least two group III-nitride layers; and
wherein said at least one group III-nitride interlayer functions as
a stress relaxation layer.
2. An epitaxial wafer comprising: a) a substrate; b) at least two
group III-nitride layers epitaxially formed on said substrate; and
c) at least one group III-nitride interlayer, which substantially
does not contain Al, epitaxially formed directly between and in
contact with each of said at least two group III-nitride layers;
wherein a growth temperature of said at least one group III-nitride
interlayer is lower than a growth temperature of each of said at
least two group III-nitride layers; wherein said at least one group
III-nitride interlayer has a lower crystallinity than each of said
at least two group III-nitride layers; and wherein a thickness of
said at least one group III-nitride interlayer is at least 10 nm
and not more than 70 nm.
3. An epitaxial wafer comprising: a) a substrate; b) at least two
group III-nitride layers epitaxially formed on said substrate; and
c) at least one group III-nitride interlayer, which is
substantially composed of GaN and which substantially does not
contain Al, epitaxially formed directly between and in contact with
each of said at least two group III-nitride layers; wherein a
growth temperature of said at least one group III-nitride
interlayer is lower than a growth temperature of each of said at
least two group III-nitride layers; and wherein said at least one
group III-nitride interlayer has a lower crystallinity than each of
said at least two group III-nitride layers.
4. An epitaxial wafer comprising: a) a substrate; b) at least two
group III-nitride layers epitaxially formed on said substrate; and
c) at least one group III-nitride interlayer, which substantially
does not contain Al, epitaxially formed directly between and in
contact with each of said at least two group III-nitride layers;
wherein a growth temperature of said at least one group III-nitride
interlayer is lower than a growth temperature of each of said at
least two group III-nitride layers; wherein said at least one group
III-nitride interlayer has a lower crystallinity than each of said
at least two group III-nitride layers; and wherein a buffer layer
is interposed between said substrate and one of said at least two
group III-nitride layers which is closest to said substrate.
5. A semiconductor multi-layer structure comprising: a) an
epitaxial wafer comprising a-1) a substrate, a-2) at least two
group III-nitride layers epitaxially formed on said substrate, and
a-3) at least one group III-nitride interlayer, which substantially
does not contain Al, epitaxially formed directly between and in
contact with each of said at least two group III-nitride layers,
wherein said at least one group III-nitride interlayer has a lower
crystallinity than each of said at least two group III-nitride
layers and functions as a stress relaxation layer; and b) group
III-nitride semiconductor layers formed on said epitaxial wafer;
wherein a growth temperature of said at least one group III-nitride
interlayer is lower than a growth temperature of each of said at
least two group III-nitride layers.
6. A method for manufacturing an epitaxial wafer comprising the
steps of: a) a first step of epitaxially forming at least two group
III-nitride layers on a substrate; and b) a second step of
epitaxially forming at least one group III-nitride interlayer,
which functions as a stress relaxation layer and which does not
substantially contain Al, during an intermediate stage of said
first step so that said at least one group III-nitride interlayer
is directly between and in contact with each of said at least two
group III-nitride layers; wherein said at least one group
III-nitride interlayer has a lower crystallinity than each of said
at least two group III-nitride layers; and wherein a growth
temperature of said at least one group III-nitride interlayer is
lower than a growth temperature of each of said at least two
group-III nitride layers.
7. The epitaxial wafer according to claim 1, wherein a growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
8. The epitaxial wafer according to claim 2, wherein said growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
9. The epitaxial wafer according to claim 3, wherein said growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
10. The epitaxial wafer according to claim 4, wherein said growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
11. The epitaxial wafer according to claim 5, wherein said growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
12. The epitaxial wafer according to claim 6, wherein said growth
temperature of said at least one group III-nitride interlayer is in
a range of 400-650.degree. C.
13. The epitaxial wafer according to claim 1, wherein a thickness
of said at least one group III-nitride interlayer is in a range of
at least 15 nm to less than 50 nm.
14. The epitaxial wafer according to claim 2, wherein said
thickness of said at least one group III-nitride interlayer is in a
range of at least 15 nm to less than 50 nm.
15. The epitaxial wafer according to claim 3, wherein a thickness
of said at least one group III-nitride interlayer is in a range of
at least 15 nm to less than 50 nm.
16. The epitaxial wafer according to claim 4, wherein a thickness
of said at least one group III-nitride interlayer is in a range of
at least 15 nm to less than 50 nm.
17. The epitaxial wafer according to claim 5, wherein a thickness
of said at least one group III-nitride interlayer is in a range of
at least 15 nm to less than 50 nm.
18. The epitaxial wafer according to claim 6, wherein a thickness
of said at least one group III-nitride interlayer is in a range of
at least 15 nm to less than 50 nm.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 10/909,477, filed Aug. 2, 2004, which claims
the benefit of Japanese Application No. 2003-205728, filed Aug. 4,
2003, and Japanese Application No. 2004-178644, filed Jun. 16,
2004, the entireties of which are incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The present invention relates to a technique for suppressing
the bowing of an epitaxial wafer prepared by forming a group
III-nitride multilayer film on a substrate.
[0004] 2. Description of the Background Art
[0005] Group III-nitride semiconductors such as GaN-based compound
semiconductors have a wide band gap, a high breakdown voltage and
high saturation electron velocity compared with other
semiconductors. Therefore, the group III-nitride semiconductors
have frequently been studied as the material for optical devices
such as light-emitting diodes, laser diodes (LDs) and
photodetectors, and for electronic devices such as
high-electron-mobility transistors (HEMTs) and hetero bipolar
transistors (HBTs).
[0006] It is difficult to grow large-size bulk single-crystal
GaN-based compound semiconductors. Therefore, sapphire or SiC
substrates commonly are used for the growth of the GaN-based
material by metal-organic chemical vapor deposition (MOCVD).
However, a mismatch of the lattice constants between the GaN-based
compound semiconductor and the substrates is so large that a
high-quality epitaxial layer can not be obtained by directly
forming the target GaN-based compound semiconductor on the
substrate. Therefore, a technique for forming a buffer layer of AlN
or GaN has been widely employed. The buffer layers are formed on
the substrate in advance of formation of the epitaxial layer of the
GaN-based compound semiconductor. For example, Japanese Patent
Application Laid-Open Gazette No. 8-8217 (1998) discloses a
technique of forming a buffer layer consisting of
Al.sub.X1Ga.sub.1-X1N (0.ltoreq.X1.ltoreq.1) prepared at a
temperature growing no high-quality single crystal between a target
epitaxial layer and a substrate.
[0007] FIG. 14 is a schematic view of an epitaxial wafer prepared
by using this technique of forming a buffer layer. As understood
from FIG. 14, an epitaxial wafer 5 is prepared by epitaxially
growing a target group III-nitride layer 53 on a prescribed
substrate 51 with a buffer layer 52. For example, an
(Al.sub.xGa.sub.y)N (0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1,
x+y=1) layer (low-temperature-deposited buffer layer having low
crystallinity) of 20 nm to 50 nm in thickness formed by MOCVD at a
temperature of 400.degree. C. to 600.degree. C. or an AlN layer
(high-temperature-grown buffer layer having high crystallinity) of
about 1 .mu.m in thickness formed by MOCVD at a temperature of at
least 1000.degree. C. or more can be applied for the buffer layer
52. A target group III-nitride layer 53 is epitaxially formed on
the buffer layer 52 by MOCVD at a temperature of 1000.degree. C. to
1300.degree. C. Thus, a high-quality epitaxial single crystalline
layer can be formed on a substrate by forming a target group
III-nitride layer with a buffer layer.
[0008] According to the conventional art, however, the epitaxial
wafer provided with the group III-nitride layer on its surface may
experience bowing due to the difference of the thermal expansion
coefficients of between the group III-nitride layer and the
substrate. This bowing disturbs the vacuum chuck properties during
transfer steps or reduces the exposure accuracy in a
photolithography step. Further, this bowing may cause cracking on
the epitaxial wafer. Therefore, a technique for suppressing the
bowing of the epitaxial wafer is strongly demanded.
SUMMARY OF THE INVENTION
[0009] The present invention relates to a technique for suppressing
the bowing of an epitaxial wafer obtained by forming a group
III-nitride multilayer film on a substrate.
[0010] An epitaxial wafer according to a first aspect of the
present invention comprises a substrate, at least two group
III-nitride layers epitaxially formed on the substrate and at least
one group III-nitride interlayer, epitaxially formed between at
least two group III-nitride layers, substantially containing no Al.
The growth temperature for the group III-nitride interlayer is
lower than the growth temperature for each of at least two group
III-nitride layers. Thus, bowing of the epitaxial wafer can be
suppressed. When this epitaxial wafer is used, the chance of the
vacuum chuck failing during a transfer step decreases and the
exposure accuracy etc. in a photolithography step can be improved.
Further, the epitaxial wafer can be prevented from cracking.
[0011] An epitaxial wafer according to a second aspect of the
present invention comprises a substrate, at least two group
III-nitride layers epitaxially formed on the substrate and at least
one group III-nitride interlayer, epitaxially formed between at
least two group III-nitride layers, substantially containing no Al,
wherein the group III-nitride interlayer functions as a stress
relaxation layer. When this epitaxial wafer is used, the chance of
the vacuum chuck failure during a transfer step decreases and the
exposure accuracy in a photolithography step can be improved.
Further, the epitaxial wafer can be prevented from cracking.
[0012] An epitaxial wafer according to a third aspect of the
present invention comprises a substrate, at least two group
III-nitride layers epitaxially formed on the substrate and at least
one group III-nitride interlayer group, epitaxially formed between
at least two group III-nitride layers, substantially containing no
Al and including at least one first interlayer formed at a first
forming temperature and a plurality of second interlayers
alternately stacked with at least one first interlayer and formed
at a second growth temperature lower than the first growth
temperature. The second growth temperature is also lower than the
growth temperature for each of at least two group III-nitride
layers. Thus, bowing of the epitaxial wafer can be suppressed. When
this epitaxial wafer is used, the chance of the vacuum chuck
failing during a transfer step decreases and the exposure accuracy
in a photolithography step can be improved. Further, the epitaxial
wafer can be prevented from cracking.
[0013] An epitaxial wafer according to a fourth aspect of the
present invention comprises a substrate, at least two group
III-nitride layers epitaxially formed on the substrate and at least
one group III-nitride interlayer group, epitaxially formed between
at least two group III-nitride layers, substantially containing no
Al and including at least one first interlayer and a plurality of
second interlayers formed at a growth temperature different from
that of the first interlayer and alternately stacked with at least
one first interlayer, wherein the group III-nitride interlayer
group functions as a stress relaxation layer. Thus, bowing of the
epitaxial wafer can be suppressed. When this epitaxial wafer is
used, the chance of the vacuum chuck failing during a transfer step
decreases and the exposure accuracy in a photolithography step can
be improved. Further, the epitaxial wafer can be prevented from
cracking.
[0014] The present invention is also directed to a method for
manufacturing of an epitaxial wafer and a semiconductor multilayer
structure.
[0015] The foregoing and other objects, features, aspects and
advantages of the present invention will become more apparent from
the following detailed description of the present invention when
taken in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0016] FIG. 1 is a schematic view of an epitaxial wafer 1 according
to an embodiment of the present invention.
[0017] FIG. 2 is a schematic view of a manufacturing apparatus 2
for the epitaxial wafer 1 according to the embodiment.
[0018] FIG. 3 illustrates a method for manufacturing of an
epitaxial wafer 100 according to Example 1.
[0019] FIG. 4 illustrates a method of forming a semiconductor
multilayer structure according to Example 1.
[0020] FIG. 5 illustrates a method of defining a bowing value BW of
a sample S1.
[0021] FIG. 6 illustrates a method for manufacturing of an
epitaxial wafer 200 according to Comparative Example 1.
[0022] FIG. 7 illustrates a method of forming a semiconductor
multilayer structure according to Comparative Example 1.
[0023] FIG. 8 illustrates a method for manufacturing of an
epitaxial wafer 300 and a method of forming a semiconductor
multilayer structure according to Comparative Example 2.
[0024] FIG. 9 shows dependence of a bowing value BW on the
thickness of an interlayer every type of interlayer.
[0025] FIG. 10 shows dependence of the bowing value BW on the
growth temperature of the interlayer.
[0026] FIG. 11 illustrates a method for manufacturing of an
epitaxial wafer 400 according to Example 7.
[0027] FIG. 12 illustrates a method of forming a semiconductor
multilayer structure according to Example 7.
[0028] FIG. 13 illustrates a portion of a GaN intermediate layer
group 414 shown in FIG. 11 in an enlarged manner.
[0029] FIG. 14 is a schematic view of an epitaxial wafer 5
manufactured according to the conventional art.
DETAILED DESCRIPTION OF THE INVENTION
Multilayer Structure of Epitaxial Wafer
[0030] A multilayer structure of an epitaxial wafer 1 according to
an embodiment of the present invention is described with reference
to the schematic view shown in FIG. 1.
[0031] The epitaxial wafer 1 has a multilayer structure obtained by
inserting an interlayer functioning as a stress relaxation layer in
the group III-nitride layer 53 of the epitaxial wafer 5 according
to the conventional art. More specifically, the epitaxial wafer 1
is prepared by successively epitaxially growing a group III-nitride
layer 13, an intermediate layer 14 and another group III-nitride
layer 15 on a substrate 11 with a buffer layer 12.
[0032] The material for the substrate 11 is not particularly
restricted, and can be properly selected from single crystals of
sapphire, ZnO, LiAlO.sub.2, LiGaO.sub.2, MgAl.sub.2O.sub.4,
(LaSr)(AlTa)O.sub.3, NdGaO.sub.3, MgO, Si, SiC, GaAs, AlN, GaN,
AlGaN, ZrB.sub.2 and the like, for example. The thickness of the
substrate 11, which is not particularly restricted either, is
preferably set to 220 .mu.m to 1000 .mu.m, for example.
[0033] The buffer layer 12 is epitaxially grown on the substrate 11
for relaxing lattice mismatching between the substrate 11 and the
group III-nitride layer 13. For example, an
(Al.sub.xGa.sub.yIn.sub.z)N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1, x+y+z=1) layer
(low-temperature-deposited buffer layer having low crystallinity)
of 5 nm to 50 nm in thickness formed by MOCVD at a temperature of
400.degree. C. to 1000.degree. C. or an (Al.sub.xGa.sub.yIn.sub.z)N
(0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1,
x+y+z=1) layer (high-temperature-grown buffer layer having high
crystallinity) of about 20 nm to 3.0 .mu.m in thickness formed by
MOCVD at a temperature of at least 1000.degree. C. or more can be
applied for the buffer layer 12. The group III-nitride layer 13 is
epitaxially formed on the buffer layer 12 by MOCVD at a temperature
of 1000.degree. C. to 1300.degree. C. The group III-nitride layer
13 consists of a mixed crystal of AlN, GaN and InN expressed in a
general formula (Al.sub.xGa.sub.yIn.sub.z)N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1, x+y+z=1) (or a crystal of
GaN), and preferably contains at least 50% of GaN (y.gtoreq.0.5),
more preferably at least 80% of GaN (y.gtoreq.0.8). This group
III-nitride layer 13 may contain a donor or an acceptor such as Mg,
Be, Zn, Si or Ge, to be provided with p-type or n-type
semiconductor conductivity.
[0034] The interlayer 14 formed on the group III-nitride layer 13
is mainly composed of a mixed crystal of GaN and InN expressed in a
general formula (Ga.sub.xIn.sub.y)N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, x+y=1) (or a crystal of GaN), and does not
contain Al. While the group III-nitride layer 15 is formed on the
interlayer 14 by a method that is similar to that used for the
group III-nitride layer 13, the interlayer 14 is epitaxially formed
at a lower growth temperature compared with those of the group
III-nitride layers 13 and 15. Concretely, the growth temperature
for the interlayer 14 is less than 1000.degree. C. The interlayer
14, which may or may not be single crystal, is epitaxially grown at
a growth temperature that is lower than those for the group
III-nitride layers 13 and 15 to have a reduced crystallinity
compared to the group III-nitride layers 13 and 15 due to the
introduction of defects. The interlayer 14 having low crystallinity
is inserted between the group III-nitride layers 13 and 15 so as to
relax thermal stress caused on the epitaxial wafer 1 due to the
difference of the thermal expansion coefficients between the
substrate 11 and the group III-nitride layers 13 and 15, whereby
bowing of the epitaxial wafer 1 can consequently be suppressed. If
the crystallinity of the interlayer 14 is excessively reduced,
however, the quality of the group III-nitride layer 15 is badly
influenced. Therefore, the growth temperature of the interlayer 14
is preferably at least 350.degree. C. The thickness of the
interlayer 14 is preferably in the range of at least 10 nm and not
more than 70 nm, particularly in the range of at least 15 nm and
not more than 50 nm.
[0035] As described later, the interlayer 14 may be a single layer,
or may include a plurality of layers. Further, each of the group
III-nitride layers 13 and 15 may also be a single layer or may
include a plurality of layers. Various semiconductor multilayer
structures can be formed on the epitaxial wafer 1 prepared in the
aforementioned manner, as described later in more detail with
reference to the Examples.
Manufacturing Apparatus
[0036] A manufacturing apparatus 2 for the epitaxial wafer 1
according to this embodiment is a so-called "MOCVD apparatus." The
manufacturing apparatus 2 is constituted to be capable of feeding a
source gas for forming epitaxial layers onto the main surface of
the substrate 11. The manufacturing apparatus 2 is now described
with reference to the sectional view shown in FIG. 2.
[0037] The manufacturing apparatus 2 comprises a flow channel 31
for introducing a reactive gas into the main surface of the
substrate 11. The flow channel for a reactive gas set in an
airtight reaction vessel 21 has two outer ends forming an inlet 22
and an outlet 24 for the reactive gas, respectively. The flow
channel for reactive gas 31 is further provided with an opening 31h
for bringing the reactive gas into contact with the main surface of
the substrate 11.
[0038] Pipelines L1 and L2 are connected to the outlet 22 provided
outside the reaction vessel 21. The pipeline L1 is employed for
supplying ammonia gas (NH.sub.3), nitrogen gas (N.sub.2) and
hydrogen gas (H.sub.2).
[0039] On the other hand, the pipeline L2 is employed for supplying
TMA (trimethylaluminum: Al(CH.sub.3).sub.3), TMG (trimethylgarium:
Ga(CH.sub.3).sub.3), TMI (trimethylindium: In(CH.sub.3).sub.3),
CP.sub.2Mg (cyclopentadienyl magnesium: Mg(C.sub.5H.sub.5).sub.2,
silane gas (SiH.sub.4), nitrogen gas and hydrogen gas. Supply
sources 24d to 24g for TMA, TMG, TMI and CP.sub.2Mg are connected
to the pipeline L2.
[0040] The supply sources 24d to 24g for TMA, TMG, TMI and
CP.sub.2Mg are connected to a nitrogen gas supply source 24b for
bubbling. The supply sources 24d to 24g for TMA, TMG, TMI and
CP.sub.2Mg are also connected to a hydrogen gas supply source
24c.
[0041] In the manufacturing apparatus 2, hydrogen (H.sub.2),
nitrogen (N.sub.2) or a gas mixture thereof functions as carrier
gas. The gas flow rates of all gas supply systems are controlled
through a flowmeter.
[0042] A vacuum pump 27 is connected to the outlet 24 for forcibly
discharging gas from the reaction vessel 21.
[0043] The reaction vessel 21 is provided therein with a base table
28 for receiving the base 11 to be formed with epitaxial layers and
a support shaft 29 supporting the base table 28 in the reaction
table 21. The temperature of the base table 28 can be controlled
through a heater 30. In the manufacturing apparatus 2, the
temperature of the base table 28 in close contact with the
substrate 11 is varied thereby varying the growth temperatures for
the epitaxial layers. In other words, the growth temperatures for
the epitaxial layers formed according to MOCVD can be variably
controlled through the heater 30.
EXAMPLES
[0044] Specific procedures for manufacturing epitaxial wafers
according to inventive Examples 1 to 6 and Comparative Examples 1
and 2 using MOCVD are now described. Methods for forming
semiconductor multilayer structures on these epitaxial wafers are
also described with reference to Examples 1 to 6 and Comparative
Examples 1 and 2.
Example 1
[0045] A method for manufacturing an epitaxial wafer 100 including
a GaN interlayer, which is grown at 500.degree. C. and does not
substantially contain Al according to Example 1 is described with
reference to the process flow chart shown in FIG. 3, and a method
for forming a semiconductor multilayer structure on this epitaxial
wafer 100 is described with reference to the process flow chart
shown in FIG. 4. The process flow charts shown in FIGS. 3 and 4 are
model diagrams conceptually illustrating the states of the
epitaxial wafer 100 in respective steps, and hence, the thicknesses
of layers illustrated in these figures do not necessarily reflect
the thickness ratios in the practical epitaxial wafer 100. This
also applies to subsequent process flow charts.
[0046] According to Example 1, a substantially circular C-plane
single-crystal two-inch-diameter 330-.mu.m-thick sapphire substrate
was employed as a substrate 111. In advance of formation of
epitaxial layers on the main surface of the substrate 111, the
substrate 111 was cleaned with a mixed solution of sulfuric acid
(H.sub.2SO.sub.4) and hydrogen peroxide water (H.sub.2O.sub.2).
Then, the substrate 111 was placed on the base table 28 provided in
the reaction vessel 21 and subjected to thermal cleaning. This
thermal cleaning was performed by heating the base 111 to
1200.degree. C. with the heater 30 while hydrogen gas was fed into
the flow channel for reactive gas 31 under atmospheric pressure at
a mean velocity of 2 m/sec., and the state of 1200.degree. C. was
held for 10 minutes ([a] in FIG. 3).
[0047] After termination of the thermal cleaning, the temperature
of the base 111 was reduced to 500.degree. C., for introducing a
gas mixture of TMG and ammonia gas into the flow channel for
reactive gas 31 so that the mean velocity was 2 m/sec. Thus, a
low-temperature-deposited buffer layer 112 of GaN having a
thickness of 30 nm was epitaxially formed on the substrate 111 ([b]
in FIG. 3).
[0048] Then, the substrate 111 was heated to 1180.degree. C. for
introducing a gas mixture of TMG and ammonia gas into the flow
channel for reactive gas 31 so that the mean velocity was 4 m/sec.
Thus, a GaN layer 113 having a thickness of 0.5 .mu.m was
epitaxially formed on the low-temperature-deposited buffer layer
112 ([c] in FIG. 3). Then, the temperature of the base 111 was
reduced to 500.degree. C., for introducing a gas mixture of TMG and
ammonia gas from the reactive gas supply pipe 22 into the reaction
vessel 21 so that the mean velocity was 2 m/sec. Thus, a GaN
interlayer 114 having a thickness of 20 nm and having lower
crystallinity than the GaN layer 113 was epitaxially formed on the
GaN layer 113 ([d] in FIG. 3). Further, the base 111 was again
heated to 1180.degree. C., for introducing a gas mixture of TMG and
ammonia gas into the flow channel for reactive gas 31 so that the
mean velocity was 4 m/sec. Thus, a GaN layer 115 having a thickness
of 2.48 .mu.m was epitaxially formed on the GaN interlayer 114 ([e]
in FIG. 3). It follows that the GaN interlayer 114 having low
crystallinity was formed between the GaN layers 113 and 115 through
the steps [c] to [e] in FIG. 3.
[0049] Steps for forming a semiconductor multilayer structure on
the epitaxial wafer 100 prepared through the aforementioned steps
are now described.
[0050] First, a gas mixture of TMA, TMG and ammonia gas was
introduced into the flow channel for reactive gas 31 for forming an
epitaxial layer 116 of 7 nm in thickness having a composition of
Al.sub.0.25Ga.sub.0.75N ([a] in FIG. 4). Then, a gas mixture of
silane gas, TMA, TMG and ammonia gas was introduced into the flow
channel for reactive gas 31 for forming an epitaxial layer 117
having a thickness of 15 nm and having a basic composition of
Al.sub.0.25Ga.sub.0.75N doped with Si ([b] in FIG. 4). The
epitaxial layer 117 was an n-type semiconductor layer due to the Si
serving as a donor. Further, a gas mixture of TMA, TMG and ammonia
gas was introduced into the flow channel for reactive gas 31, for
forming another epitaxial layer 118 having a thickness of 3 nm and
having a composition of Al.sub.0.25Ga.sub.0.75N ([c] in FIG.
4).
[0051] A sample S1 prepared in the aforementioned manner was
removed from the reaction vessel 21 and the bowing value BW was
measured to be 15 .mu.m. As shown in FIG. 5, the bowing value BW
was defined by the maximum lift quantity on a wafer surface, i.e.,
the distance of projection of a wafer surface WS from a horizontal
position HR.
Comparative Example 1
[0052] A method for manufacturing of an epitaxial wafer 200
including an AlN interlayer grown at 500.degree. C. according to
Comparative Example 1 is described with reference to the process
flow chart shown in FIG. 6, and a method of forming a semiconductor
multilayer structure on this epitaxial wafer 200 is described with
reference to the process flow chart shown in FIG. 7. The process
flow according to Comparative Example 1 was identical to that
according to Example 1, except that an AlN interlayer was formed
through a step [d] in FIG. 6.
[0053] First, a low-temperature-deposited buffer layer 212 of GaN
having a thickness of 30 nm and a GaN layer 213 having a thickness
of 0.5 .mu.m were epitaxially formed on a base 211 that was similar
to that used in Example 1, under the same conditions as those in
Example 1 ([b] and [c] in FIG. 6). Then, the temperature of the
base 211 was reduced to 500.degree. C. for introducing a gas
mixture of TMA and ammonia gas into the flow channel for reactive
gas 31 so that the mean velocity was 2 m/sec. Thus, an AlN
interlayer 214 having a thickness of 20 nm and having lower
crystallinity than the GaN layer 213 was epitaxially formed on the
GaN layer 213 ([d] in FIG. 6). Further, an epitaxial layer 215
having a thickness of 2.48 .mu.m, another epitaxial layer 216
having a thickness of 7 nm and having a composition of
Al.sub.0.25Ga.sub.0.75N, still another epitaxial layer 217 having a
thickness of 15 nm and having a basic composition of
Al.sub.0.25Ga.sub.0.75N doped with Si, and a further epitaxial
layer 218 having a thickness of 3 nm and having a composition of
Al.sub.0.25Ga.sub.0.75N were formed under the same conditions as
those in Example 1 ([d] in FIG. 6 to [c] in FIG. 7).
[0054] A sample S2 prepared in the aforementioned manner was
removed from the reaction vessel 21 and the bowing value BW was
measured to be 39 .mu.m using the same measuring method as that in
Example 1.
Comparative Example 2
[0055] A method for manufacturing of an epitaxial wafer 300 without
an interlayer formed at a reduced growth temperature according to
Comparative Example 2 and a method for forming a semiconductor
multilayer structure on this epitaxial wafer 300 are now described
with reference to the process flow chart shown in FIG. 8.
[0056] A low-temperature-deposited buffer layer 312 of GaN having a
thickness of 30 nm was epitaxially formed on a substrate 311
similar to that employed in Example 1 under the same conditions as
those in Example 1 ([b] in FIG. 8). Then, the base 311 was heated
to 1180.degree. C., for introducing a gas mixture of TMG and
ammonia gas into the flow channel for reactive gas 31 so that the
mean velocity was 4 in/sec. Thus, a GaN layer 313 having a
thickness of 3 .mu.m was epitaxially formed on the
low-temperature-deposited buffer layer 312 ([c] in FIG. 8).
Further, an epitaxial layer 314 having a thickness of 7 nm and
having a composition of Al.sub.0.25Ga.sub.0.75N, another epitaxial
layer 315 having a thickness of 15 nm and having a basic
composition of Al.sub.0.25Ga.sub.0.75N doped with Si, and still
another epitaxial layer 316 having a thickness of 3 nm and having a
composition of Al.sub.0.25Ga.sub.0.75N were formed under the same
conditions as those in Example 1 ([d] to [f] in FIG. 8).
[0057] A sample S3 prepared in the aforementioned manner was
removed from the reaction vessel 21 and the bowing value BW was
measured to be 30 .mu.m using the same measuring method as that in
Example 1.
Examples 2 to 5
[0058] Epitaxial wafers according to Examples 2, 3 and 4 correspond
to those obtained by changing the thicknesses of GaN interlayers
similar to that of the epitaxial wafer 100 according to Example 1
from 20 nm to 5 nm, 50 nm and 100 nm, respectively. The epitaxial
wafer according to Example 5 was obtained by changing the epitaxial
formation temperature of a GaN interlayer similar to that of the
epitaxial wafer 100 according to Example 1 from 500.degree. C. to
800.degree. C.
[0059] FIG. 9 shows the dependence of the bowing value BW on the
thicknesses of the GaN interlayers for the respective types (GaN
and AlN) of interlayers according to Examples 1 to 4 and
Comparative Example 1 having interlayers that are grown at a
temperature of 500.degree. C., and a sample according to
Comparative Example 2 without an interlayer. FIG. 10 shows the
dependence of the bowing values BW on the growth temperatures for
the GaN interlayers of Examples 1 to 5 with GaN interlayers having
a thickness of 20 nm and the sample according to Comparative
Example 2 without an interlayer.
Example 6
[0060] While a single GaN interlayer was formed as a stress
relaxation layer in each of Examples 1 to 5, the stress relaxation
layer may alternatively be formed by an interlayer group including
a plurality of layers. A method for manufacturing of an epitaxial
wafer 400 having an interlayer group including a plurality of
layers according to Example 6 is described with reference to the
process flow chart shown in FIG. 11, and a method of forming a
semiconductor multilayer structure on this epitaxial wafer 400 is
described with reference to the process flow chart shown in FIG.
12.
[0061] A low-temperature-deposited buffer layer 412 of GaN having a
thickness of 30 nm and a GaN layer 413 having a thickness of 0.5
.mu.m were epitaxially formed on a base 411 similar to that used in
Example 1 under the same conditions as those in Example 1 ([b] and
[c] in FIG. 11). Then, a GaN interlayer group 414 was epitaxially
formed on the GaN layer 413 ([d] in FIG. 11). The GaN interlayer
group 414 was prepared by alternately stacking low-temperature
interlayers each having a thickness of 20 nm, formed at a growth
temperature of 500.degree. C. lower than that for the GaN layer
413, and high-temperature-grown interlayers each having a thickness
of 25 nm, formed at a growth temperature of 1180.degree. C. FIG. 13
shows the GaN interlayer group 414 in an enlarged manner, for
illustrating the stacked state. As shown in FIG. 13, five pairs of
low-temperature-deposited and high-temperature-grown interlayers L1
and H1, L2 and H2, L3 and H3, L4 and H4 and L5 and H5 are stacked
in the GaN interlayer group 414 according to Example 6.
[0062] A method of forming the GaN interlayer group 414 is now
described. The method of forming the GaN interlayer group 414
includes two steps of:
[0063] setting the temperature of the wafer 411 to 500.degree. C.
for introducing a gas mixture of TMG and ammonia gas into the flow
channel for reactive gas 31 so that the mean velocity is 2 m/sec.
thereby epitaxially forming a low-temperature-deposited interlayer
having a thickness of 20 nm and having low crystallinity (step A);
and
[0064] setting the temperature of the wafer 411 to 1180.degree. C.
for introducing a gas mixture of TMG and ammonia gas into the flow
channel for reactive gas 313 so that the mean velocity is 4 m/sec.
thereby epitaxially forming a high-temperature-grown interlayer
having a thickness of 25 nm and having low crystallinity (step
B).
[0065] According to Example 6, steps A and B were repeated five
times thereby epitaxially forming the GaN interlayer group 414.
[0066] After formation of the GaN interlayer group 414, a GaN layer
415 having a thickness of 2.48 .mu.m, an epitaxial layer 416 having
a thickness of 7 nm and having a composition of
Al.sub.0.25Ga.sub.0.75N, another epitaxial layer 417 having a
thickness of 15 nm and having a basic composition of
Al.sub.0.25Ga.sub.0.75N doped with Si, and still another epitaxial
layer 418 having a thickness of 3 nm and having a composition of
Al.sub.0.25Ga.sub.0.75N were formed under the same conditions as
those in Example 1 ([e] in FIG. 11 to [c] in FIG. 12).
[0067] A sample S4 prepared in the aforementioned manner was
removed from the reaction vessel 21 and the bowing value BW was
measured to be 10 .mu.m by using the same measuring method as that
in Example 1.
Comparison of the Examples and the Comparative Examples
[0068] The present invention is now described with reference to a
comparison of Examples 1 to 6 and Comparative Examples 1 and 2.
[0069] As clearly shown in FIG. 9, it was possible to suppress the
bowing of each sample by introducing the GaN interlayer. A
remarkable effect of suppressing the bowing was attained when the
thickness of the interlayer was in a range of at least 10 nm to not
more than 70 nm, and particularly in a range of at least 15 nm to
not more than 50 nm. On the other hand, when an AlN interlayer was
inserted in place of each GaN interlayer, however, the bowing value
BW of each sample increased. Thus, the inserted interlayer
desirably consists of GaN without Al, and the thickness of the GaN
interlayer is desirably in a range of at least 10 nm to not more
than 70 nm, and particularly in a range of at least 15 nm to not
more than 50 nm. It is presumed that the state of bowing is
deteriorated due to the large difference of the lattice constants
or the thermal expansion coefficients between AlN and GaN, when the
interlayer is made of AlN.
[0070] As shown in FIG. 10, the bowing value BW increased as the
growth temperature increased. Therefore, the growth temperature is
preferably lower than that of an adjacent GaN layer, more
specifically in a range of at least 350.degree. C. to not more than
1000.degree. C. More preferably, the growth temperature is at least
400.degree. C. and not more than 650.degree. C.
Modifications
[0071] While the present invention has been described with
reference to the embodiment, the present invention is not
restricted to the specific mode of the aforementioned embodiment
but can be modified in various ways in the range of the invention
according to claims.
[0072] For example, each GaN layer may consist of a mixed crystal
of AlN, GaN and InN expressed in a general formula
(Al.sub.xGa.sub.yIn.sub.z)N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, 0.ltoreq.z.ltoreq.1, x+y+z=1). More generally
stated, the GaN layer may consist of a group III-nitride. It is
allowed to introduce various side components into this group
III-nitride. For example, the group III-nitride may contain
prescribed quantities of Si, Mg, B, Ge, Zn, Be etc., to be provided
with semiconductivity. Further, contaminations that are unavoidably
mixed in manufacturing steps are allowed in a range that does not
essentially change the layer characteristics.
[0073] Similarly, each GaN interlayer or the GaN interlayer group
does not simply substantially contain Al except as a quantity
unavoidably mixed as contaminations. For example, each GaN
interlayer may consist of a mixed crystal of GaN and InN expressed
in a general formula (Ga.sub.xIn.sub.y)N (0.ltoreq.x.ltoreq.1,
0.ltoreq.y.ltoreq.1, x+y=1) (or a crystal of GaN). More generally
stated, each GaN layer may consist of a group III-nitride which is
essentially without Al. It is not necessarily required that the
composition of each GaN interlayer or the GaN interlayer group is
identical to that of each GaN layer, as a matter of course.
[0074] In Example 6, the GaN interlayer group 414 may include a
third layer different from the high-temperature-grown and
low-temperature-deposited interlayers H1 to H5 and L1 to L5. While
the thicknesses of each low-temperature-deposited interlayer and
each high-temperature-grown interlayer were set to 20 nm and 25 nm,
respectively, in Example 6, the thicknesses are not so restricted.
More specifically, an equivalent bowing suppressing effect can be
attained also by setting the thicknesses of each
low-temperature-deposited interlayer and each
high-temperature-grown interlayer to at least 15 nm and not more
than 50 nm, and at least 10 nm and not more than 100 nm,
respectively. Further, an equivalent bowing suppressing effect can
also be attained by setting the growth temperatures for the
low-temperature-deposited and high-temperature-grown interlayers L1
to L5 and H1 to H5 to at least 350.degree. C. and not more than
1000.degree. C. and to at least 800.degree. C. and not more than
1300.degree. C., respectively. The growth temperature for the
high-temperature-grown interlayers H1 to H5 must be higher than
that of the low-temperature-deposited interlayers L1 to L5. More
preferably, the growth temperatures of the
low-temperature-deposited interlayers L1 to L5 and the
high-temperature-grown interlayers H1 to H5 are set to at least
400.degree. C. and not more than 650.degree. C. and to at least
1000.degree. C., respectively.
[0075] While the present invention has been shown and described in
detail, the foregoing description is in all aspects illustrative
and not restrictive. It is therefore understood that numerous
modifications and variations can be devised without departing from
the scope of the invention.
* * * * *