U.S. patent application number 11/755509 was filed with the patent office on 2008-12-04 for discrete trap memory (dtm) mediated by fullerenes.
Invention is credited to Gerhard Poeppel, Georg Tempel.
Application Number | 20080296662 11/755509 |
Document ID | / |
Family ID | 39917513 |
Filed Date | 2008-12-04 |
United States Patent
Application |
20080296662 |
Kind Code |
A1 |
Poeppel; Gerhard ; et
al. |
December 4, 2008 |
Discrete Trap Memory (DTM) Mediated by Fullerenes
Abstract
A discrete trap memory, comprising a silicon substrate layer, a
bottom oxide layer on the silicon substrate layer, a Fullerene
layer on the bottom oxide layer, a top oxide layer on the Fullerene
layer, and a gate layer on the top oxide layer; wherein the
Fullerene layer comprises spherical, elliptical or endohedral
Fullerenes that act as charge traps.
Inventors: |
Poeppel; Gerhard;
(Regensburg, DE) ; Tempel; Georg; (Dresden,
DE) |
Correspondence
Address: |
SLATER & MATSIL LLP
17950 PRESTON ROAD, SUITE 1000
DALLAS
TX
75252
US
|
Family ID: |
39917513 |
Appl. No.: |
11/755509 |
Filed: |
May 30, 2007 |
Current U.S.
Class: |
257/325 ;
257/E21.294; 257/E29.309; 438/591 |
Current CPC
Class: |
G11C 2216/06 20130101;
B82Y 10/00 20130101; Y10S 977/763 20130101; G11C 13/025 20130101;
Y10S 977/773 20130101 |
Class at
Publication: |
257/325 ;
438/591; 257/E29.309; 257/E21.294 |
International
Class: |
H01L 29/792 20060101
H01L029/792; H01L 21/3205 20060101 H01L021/3205 |
Claims
1. An integrated circuit device, comprising: a Fullerene layer
having a plurality of Fullerene molecules, wherein the Fullerene
molecules act as charge traps.
2. The integrated circuit device of claim 1, wherein the plurality
of Fullerenes are spherical or elliptical Fullerenes.
3. The integrated circuit device of claim 1, wherein the plurality
of Fullerenes are endohedral Fullerenes.
4. The integrated circuit device of claim 1, wherein the plurality
of Fullerenes are arranged to form a single layer of
Fullerenes.
5. The integrated circuit device of claim 1, wherein the Fullerenes
are Hetrofullerenes.
6. A discrete trap memory, comprising: a silicon substrate layer; a
bottom dielectric layer on the silicon substrate layer; a Fullerene
layer on the bottom dielectric layer; a top dielectric layer on the
Fullerene layer; and a gate layer on the top dielectric layer.
7. The discrete trap memory of claim 6, wherein the Fullerene layer
further comprises: a plurality of Fullerenes arranged in a single
layer.
8. The discrete trap memory of claim 6, wherein the Fullerene layer
comprises Hetrofullerenes.
9. The discrete trap memory of claim 6, wherein the Fullerene layer
further comprises: a plurality of endohedral Fullerenes that act as
charge traps.
10. The discrete trap memory of claim 6, wherein the Fullerene
layer further comprises: a plurality of spherical or elliptical
Fullerenes that act as charge traps.
11. The discrete trap memory of claim 6, wherein a material forming
the bottom dielectric layer is selected from the group consisting
of: a high-k dielectric; an insulator; a tunnel barrier; an oxide;
silicon oxide; Al.sub.2O.sub.3; HfO.sub.2; SiC; and SiN.
12. The discrete trap memory of claim 6, wherein a material forming
the top dielectric layer is selected from the group consisting of:
a high-k dielectric; an insulator; a tunnel barrier; an oxide;
silicon oxide; Al.sub.2O.sub.3; HfO.sub.2; SiC; and SiN.
13. A method for manufacturing a discrete trap memory device,
comprising: arranging a plurality of Fullerenes on an oxide layer
to form a mask, wherein the oxide layer is exposed through the mask
at gaps between the plurality of Fullerenes; depositing
nano-crystals over the mask; and trapping the nano-crystals in gaps
between the plurality of Fullerenes.
14. The method of claim 13, further comprising: removing the
plurality of Fullerenes, wherein nano-crystals remaining on the
oxide layer act as charge traps in the discrete memory device.
15. The method of claim 14, further comprising: thermally growing
the oxide layer on a silicon substrate; depositing silicon oxide
over the nano-crystals; and forming a gate layer over the silicon
oxide.
16. A method for manufacturing a discrete trap memory device,
comprising: arranging a plurality of Fullerenes on a bottom
dielectric layer to form a mask, wherein the bottom dielectric
layer is exposed through the mask at gaps between the plurality of
Fullerenes; depositing nano-crystals over the mask; and trapping
the nano-crystals in gaps between the plurality of Fullerenes.
17. The method of claim 16, further comprising: removing the
plurality of Fullerenes, wherein nano-crystals remaining on the
bottom dielectric layer act as charge traps in the discrete memory
device.
18. The method of claim 17, further comprising: thermally growing
the bottom dielectric layer on a silicon substrate; depositing a
top dielectric layer over the nano-crystals; and forming a gate
layer over the top dielectric layer.
19. The method of claim 16, wherein a material forming the bottom
dielectric layer is selected from the group consisting of: a high-k
dielectric; an insulator; a tunnel barrier; an oxide; silicon
oxide; Al.sub.2O.sub.3; HfO.sub.2; SiC; and SiN.
20. The method of claim 16, wherein a material forming the top
dielectric layer is selected from the group consisting of: a high-k
dielectric; an insulator; a tunnel barrier; an oxide; silicon
oxide; Al.sub.2O.sub.3; HfO.sub.2; SiC; and SiN.
Description
TECHNICAL FIELD
[0001] The present invention relates generally to discrete trap
memories and, more particularly, to discrete trap memories that use
Fullerenes to hold or place the trapped charge.
BACKGROUND
[0002] Discrete Trap Memories (DTM) contribute substantially to the
development of Flash memory. FIG. 1 is a schematic drawing of DTM
100. Source 101 and drain 102 are formed in substrate 103, which is
typically a silicon layer. Bottom oxide layer 104 is thermally
grown on silicon 103. Nitride layer 105 is deposited on bottom
oxide layer 104 and holds discrete charge traps 106. Top oxide
layer 107 is grown or deposited on nitride layer 105. Gate layer
108, which may be polycrystalline silicon or metal, is deposited on
top oxide layer 107. This structure is well known and is referred
to as SONOS or MONOS. The local potential of the channel, and
therefore the local threshold voltage, will be modified by charging
of the discrete charge traps 106 with electrons. The DTM device 100
operates such that when a voltage higher than the threshold voltage
is applied to gate 108, a percolation path between source 101 and
drain 102 allows current to flow through the device. The course of
the percolation path depends upon the distribution of traps 106 as
described, for example, in D. Ielmini et al., A new channel
percolation model for V.sub.T shift in discrete-trap memories,
Reliability Physics Symposium Proceedings, 42nd Annual 2004,
515-521 (25-29 Apr. 2004 IEEE International), the disclosure of
which is hereby incorporated by reference herein in its
entirety.
SUMMARY OF THE INVENTION
[0003] In accordance with a preferred embodiment of the present
invention, a discrete trap memory comprises a silicon substrate
layer, a bottom dielectric layer on the silicon substrate layer, a
Fullerene layer on the bottom dielectric layer, a top dielectric
layer on the Fullerene layer, and a gate layer on the top
dielectric layer; wherein the Fullerene layer comprises spherical,
elliptical or endohedral Fullerenes that act as charge traps.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] For a more complete understanding of the present invention,
and the advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
[0005] FIG. 1 is a diagram of a known discrete trap memory (DTM)
device;
[0006] FIG. 2A illustrates the distribution of charge traps in a
known DTM;
[0007] FIG. 2B illustrates a trapping layer when threshold voltage
is applied to a DTM;
[0008] FIG. 3A illustrates the distribution of charge traps in a
known DTM;
[0009] FIG. 3B illustrates a trapping layer when threshold voltage
is applied to a DTM;
[0010] FIG. 4 is a diagram of a discrete trap memory device
according to embodiments of the present invention;
[0011] FIG. 5 illustrates Fullerenes arranged in a layer of a
discrete trap memory device according to an embodiment of the
invention;
[0012] FIG. 6 illustrates Fullerenes arranged in a layer of a
discrete trap memory device according to another embodiment of the
invention;
[0013] FIG. 7 illustrates endohedral Fullerenes arranged in a layer
of a discrete trap memory device according to an embodiment of the
invention; and
[0014] FIG. 8 illustrates Fullerenes arranged as a mask layer
according to an embodiment of the invention.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0015] The making and using of the presently preferred embodiments
are discussed in detail below. It should be appreciated, however,
that the present invention provides many applicable inventive
concepts that can be embodied in a wide variety of specific
contexts. The specific embodiments discussed are merely
illustrative of specific ways to make and use the invention, and do
not limit the scope of the invention.
[0016] Known DTMs are limited by the effects of non-uniform
distribution of the trapped charge. The charge distribution effects
the operation and electrical characteristics of the memory.
Referring to FIG. 1, discrete traps 106 are statistically
distributed within nitride layer 105. Accordingly, in some devices
the distribution will be less uniform than in other devices. This
can result in a configuration that will block the percolation path
between the source and the drain or that will require a higher
threshold voltage at the gate to allow a percolation path to
form.
[0017] FIG. 2A illustrates the distribution of charge traps 201 in
a SONOS or MONOS discrete trap memory 200. Charge traps 201 are
distributed non-uniformly in device 200. FIG. 2B illustrates device
200 when a threshold voltage is applied to the gate of device 200.
As shown in FIG. 2B, the distribution of charge traps 201 does not
allow for creation of a percolation path between source 202 and
drain 203.
[0018] FIG. 3A illustrates another discrete trap memory 300 having
a different distribution of charge traps 301. Charge traps 301 are
distributed more uniformly in device 300 compared to device 200.
Accordingly, when a threshold voltage is applied to the gate of
device 300, percolation path 304 is created between source 302 and
drain 303 as shown in FIG. 3B.
[0019] Distribution of charge traps in known DTMs follows Poisson
statistics. The DTMs are restricted by available boundary
conditions as the devices are scaled, for example, from 200
nm.times.200 nm toward 25 nm.times.25 nm. The density of the charge
trap distribution remains the same in the devices independent of
the device size. Accordingly, as the devices are made smaller, the
chance for the charge distribution to block the percolation path or
to allow a permanent percolation path increases. The statistical
characteristics of known DTM devices can be improved by homogeneous
distribution of the charge traps. One method for providing
homogenous distribution of charge traps is to use a nano-mask for
nano-crystals, wherein the nano-mask is developed by means of
proteins. This technique is described, for example, in Shan Tung et
al., Nanocrystal Flash Memory Fabricated with Protein-mediated
Assembly, Electron Devices Meeting, 2005, IEDM Technical Digest,
174-177 (5-7 Dec. 2005 IEEE International) the disclosure of which
is hereby incorporated by reference herein in its entirety.
[0020] The present invention provides a flexible alternative by
which charge traps can be homogenously ordered in DTM using
Fullerenes. Fullerenes can be manufactured in diverse sizes and
forms, such as spherical Fullerenes known as C60, C70, and C240.
Endohedral Fullerenes that have additional atoms, ions, or clusters
enclosed within their inner spheres are also known. For example, a
nitrogen-endowed C60 Fullerene (N@C60) carries individual nitrogen
atoms in their inside. Using these characteristics one can use
Fullerenes to control the density and the distribution of the
charge traps.
[0021] FIG. 4 is a schematic drawing of a new DTM 400. Source 401
and drain 402 are formed in substrate 403, which may be a silicon
layer. Bottom oxide layer 404 is thermally grown on silicon 403.
Instead of the nitride layer that is deposited on the bottom oxide
layer in some known DTMs, one embodiment of the present invention
replaces the nitride with a dense pattern of endohedral Fullerenes
405 that create charge traps 406. Top oxide layer 407 is deposited
on Fullerene layer 405. Gate layer 408, which may be
polycrystalline silicon or metal, is deposited on top oxide layer
407. DTM device 400 operates such that when a threshold voltage is
applied to gate 408, a percolation path between source 401 and
drain 402 allows current to flow through the device. Layer 405 may
be a regular and dense organization of endohedral Fullerenes 406.
Using Fullerenes 406, the present invention removes the
statistical, random distribution of charge traps that are found in
nitride layers of known DTMs and decreases variations in threshold
voltage. In alternative embodiments, other materials may be used in
place of oxide layers 404, 407, such as a high-k dielectric, an
insulator, a tunnel barrier, silicon oxide, Al.sub.2O.sub.3,
HfO.sub.2, SiC, SiN, or other materials.
[0022] By using endohedral Fullerenes, the size and kind of the
charge traps can be controlled and the local effect of the local
traps can be specified. Thus, DTMs with a more precise threshold
voltage and a smaller cell sizes can be manufactured. FIG. 5 is a
top-view diagram of a Fullerene layer in a DTM according to one
embodiment of the present invention. Fullerenes 501 may be
spherical Fullerenes or endohedral Fullerenes. As shown in FIG. 5,
Fullerenes 501 can be closely-spaced, which allows for a more
regular arrangement of the charge traps in the Fullerenes. This
arrangement minimizes variations in threshold voltage by
eliminating the rougher geometric effects that are present in known
nitride DTMs. The more densely packed the Fullerenes are, the less
variation there will be in devices of the same size. DTMs with
densely packed Fullerenes also allow for a more accurate prediction
of a device's characteristics when scaled to different sizes. FIG.
6 illustrates an alternative embodiment in which Fullerenes 601 are
arranged in a more random pattern that is less closely spaced.
[0023] Fullerenes 401 may act as discrete trapping objects as shown
in FIG. 5. Alternatively, as shown in FIG. 7, endohedral Fullerenes
701 holding other atoms 702 can be used as charge traps. In one
embodiment, atoms 702 in Fullerenes 701 may be atoms with a large
electronegativity, such as Flourine, which is an electron acceptor
or electron trap. Elements with a smaller electronegativity, such
as Oxygen, might also be used. Atoms such as Manganese may also be
used as well as clusters of atoms. Different endohedral objects may
cause beneficial effects due to complex orbital structures. In
other embodiments, Heterofullerenes (i.e. Fullerene-type structures
in which other atoms, such as Nitrogen atoms, are substituted for
some of the carbon atoms in the "Fullerens") may be used in place
of Fullerenes 601. Alternatively, Fullerenes compounded from atoms
such as Gold may be used in place of Fullerenes 401.
[0024] FIG. 8 illustrates how Fullerenes 801 may be used as a mask.
Fullerenes 801 may be spherical, elliptical or endohedral. The type
and size of Fullerenes 801 are chosen to control the size of area
802 between adjacent Fullerenes 801. The area 802 is an open space
to underlying layer 803. Fullerenes 801 are used as a mask for the
production of charge traps by using spaces 802 for deposition of
nano-clusters on surface 803 thereby causing charge traps to
develop.
[0025] A discrete trap memory device may be manufactured by
thermally growing an oxide layer on a silicon substrate, arranging
a plurality of Fullerenes on the oxide layer to form a mask,
wherein the oxide layer is exposed through the mask at gaps between
the plurality of Fullerenes, depositing nano-crystals over the
mask, and trapping the nano-crystals in gaps between the plurality
of Fullerenes. The plurality of Fullerenes may be removed so that
nano-crystals remaining on the oxide layer act as charge traps in
the discrete memory device. Silicon oxide may be deposited over the
nano-crystals, and a gate layer formed over the silicon oxide. In
alternative embodiments, other materials may be used in place of
the oxide layer, such as a high-k dielectric, an insulator, a
tunnel barrier, silicon oxide, Al.sub.2O.sub.3, HfO.sub.2, SiC,
SiN, or other materials.
[0026] Although the present invention and its advantages have been
described in detail, it should be understood that various changes,
substitutions and alterations can be made herein without departing
from the spirit and scope of the invention as defined by the
appended claims. Moreover, the scope of the present application is
not intended to be limited to the particular embodiments of the
process, machine, manufacture, composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the
disclosure of the present invention, processes, machines,
manufacture, compositions of matter, means, methods, or steps,
presently existing or later to be developed, that perform
substantially the same function or achieve substantially the same
result as the corresponding embodiments described herein may be
utilized according to the present invention. Accordingly, the
appended claims are intended to include within their scope such
processes, machines, manufacture, compositions of matter, means,
methods, or steps.
* * * * *