U.S. patent application number 12/091448 was filed with the patent office on 2008-11-27 for method and apparatus for processing procedures in selected interlace states in an open state in wireless commnunication system.
This patent application is currently assigned to QUALCOMM INCORPORATED. Invention is credited to Nileshkumar J. Parekh, Rajat Prakash, Faith Ulupinar.
Application Number | 20080293421 12/091448 |
Document ID | / |
Family ID | 37716007 |
Filed Date | 2008-11-27 |
United States Patent
Application |
20080293421 |
Kind Code |
A1 |
Ulupinar; Faith ; et
al. |
November 27, 2008 |
Method and Apparatus for Processing Procedures in Selected
Interlace States in an Open State in Wireless Commnunication
System
Abstract
A method and apparatus for processing procedures in selected
interlace states in an Open state is provided, the method
comprising determining if a SelectedInterlaceOn state is entered,
generating a SelectedInterlaceEnabled indication and placing the
most recent SelectedInterlaceAssignment message in the public
data.
Inventors: |
Ulupinar; Faith; (San Diego,
CA) ; Parekh; Nileshkumar J.; (San Diego, CA)
; Prakash; Rajat; (San Diego, CA) |
Correspondence
Address: |
Amin, Turocy & Calvin LLP
1900 E. 9th Street, 24th Floor, National City Center
Cleveland
OH
44114
US
|
Assignee: |
QUALCOMM INCORPORATED
San Diego
CA
|
Family ID: |
37716007 |
Appl. No.: |
12/091448 |
Filed: |
October 27, 2006 |
PCT Filed: |
October 27, 2006 |
PCT NO: |
PCT/US06/41943 |
371 Date: |
July 25, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
60731126 |
Oct 27, 2005 |
|
|
|
Current U.S.
Class: |
455/446 ;
455/561 |
Current CPC
Class: |
Y02D 30/00 20180101;
Y02D 70/1224 20180101; H04W 52/0235 20130101; H04L 41/083 20130101;
Y02D 70/142 20180101; H04L 41/0869 20130101; H04L 1/0028 20130101;
Y02D 70/1242 20180101; Y02D 70/144 20180101; H04B 17/382 20150115;
H04W 24/10 20130101; Y02D 70/146 20180101; H04L 1/0026 20130101;
Y02D 30/32 20180101; Y02D 30/70 20200801; Y02D 70/162 20180101;
H04L 1/0675 20130101; H04L 1/0003 20130101; H04B 17/318 20150115;
H04L 27/2647 20130101; H04W 88/02 20130101; H04L 41/0803
20130101 |
Class at
Publication: |
455/446 ;
455/561 |
International
Class: |
H04Q 7/20 20060101
H04Q007/20; H04M 1/00 20060101 H04M001/00 |
Claims
1. A method of processing procedures in selected interlace states
in an Open state in wireless communication system, characterized in
that: determining if a SelectedInterlaceOn state is entered;
generating a SelectedInterlaceEnabled indication, and placing a
most recent SelectedInterlaceAssignment message in the public
data.
2. A computer readable medium including instruction stored thereon,
characterized in that: a first set of instructions for determining
if a SelectedInterlaceOn state is entered; a second set of
instructions for generating a SelectedInterlaceEnabled indication;
and a third set of instructions for placing a most recent
SelectedInterlaceAssignment message in the public data.
3. An apparatus operable in a wireless communication system,
characterized in that: means for determining if a
SelectedInterlaceOn state is entered; means for generating a
SelectedInterlaceEnabled indication; and means for placing a most
recent SelectedInterlaceAssignment message in the public data.
4. A method of processing procedures in selected interlace states
in an Open state in wireless communication system, characterized in
that: determining if a SelectedInterlaceOff state is entered; and
generating a SelectedInterlaceDisabled indication.
5. A computer readable medium including instruction stored thereon,
characterized in that: a first set of instructions for determining
if a SelectedInterlaceOff state is entered; and a second set of
instructions for generating a SelectedInterlaceDisabled
indication.
6. An apparatus operable in a wireless communication system,
characterized in that: means for determining if a
SelectedInterlaceOff state is entered; and means for generating a
SelectedInterlaceDisabled indication.
Description
CLAIM OF PRIORITY UNDER 35 U.S.C. .sctn. 119
[0001] The present application for patent claims priority to
Provisional Application Ser. No. 60/731,126, entitled "METHODS AND
APPARATUS FOR PROVIDING MOBILE BROADBAND WIRELESS LOWER MAC", filed
Oct. 27, 2005, assigned to the assignee hereof and expressly
incorporated herein by reference.
BACKGROUND
[0002] 1. Field
[0003] The present disclosure relates generally to wireless
communication and more particularly to methods and apparatus for
processing procedures in selected interlaces states in an Open
state.
[0004] 2. Background
[0005] Wireless communication systems have become a prevalent means
by which a majority of people worldwide have come to communicate.
Wireless communication devices have become smaller and more
powerful in order to meet consumer needs and to improve portability
and convenience. The increase in processing power in mobile devices
such as cellular telephones has lead to an increase in demands on
wireless network transmission systems. Such systems typically are
not as easily updated as the cellular devices that communicate
there over. As mobile device capabilities expand, it can be
difficult to maintain an older wireless network system in a manner
that facilitates fully exploiting new and improved wireless device
capabilities.
[0006] Wireless communication systems generally utilize different
approaches to generate transmission resources in the form of
channels. These systems may be code division multiplexing (CDM)
systems, frequency division multiplexing (PDM) systems, and time
division multiplexing (TDM) systems. One commonly utilized variant
of FDM is orthogonal frequency division multiplexing (OFDM) that
effectively partitions the overall system bandwidth into multiple
orthogonal subcarriers. These subcarriers may also be referred to
as tones, bins, and frequency channels. Each subcarrier can be
modulated with data. With time division based techniques, each
subcarrier can comprise a portion of sequential time slices or time
slots. Each user may be provided with a one or more time slot and
subcarrier combinations for transmitting and receiving information
in a defined burst period or frame. The hopping schemes may
generally be a symbol rate hopping scheme or a block hopping
scheme.
[0007] Code division based techniques typically transmit data over
a number of frequencies available at any time in a range. In
general, data is digitized and spread over available bandwidth,
wherein multiple users can be overlaid on the channel and
respective users can be assigned a unique sequence code. Users can
transmit in the same wide-band chunk of spectrum, wherein each
user's signal is spread over the entire bandwidth by its respective
unique spreading code. This technique can provide for sharing,
wherein one or more users can concurrently transmit and receive.
Such sharing can be achieved through spread spectrum digital
modulation, wherein a user's stream of bits is encoded and spread
across a very wide channel in a pseudo-random fashion. The receiver
is designed to recognize the associated unique sequence code and
undo the randomization in order to collect the bits for a
particular user in a coherent manner.
[0008] A typical wireless communication network (e.g., employing
frequency, time, and/or code division techniques) includes one or
more base stations that provide a coverage area and one or more
mobile (e.g., wireless) terminals that can transmit and receive
data within the coverage area. A typical base station can
simultaneously transmit multiple data streams for broadcast,
multicast, and/or unicast services, wherein a data stream is a
stream of data that can be of independent reception interest to a
mobile terminal. A mobile terminal within the coverage area of that
base station can be interested in receiving one, more than one or
all the data streams transmitted from the base station. Likewise, a
mobile terminal can transmit data to the base station or another
mobile terminal. In these systems the bandwidth and other system
resources are assigned utilizing a scheduler.
[0009] The signals, signal formats, signal exchanges, methods,
processes, and techniques disclosed herein provide several
advantages over known approaches. These include, for example,
reduced signaling overhead, improved system throughput, increased
signaling flexibility, reduced information processing, reduced
transmission bandwidth, reduced bit processing, increased
robustness, improved efficiency, and reduced transmission power
SUMMARY
[0010] The following presents a simplified summary of one or more
aspects in order to provide a basic understanding of such aspects.
This summary is not an extensive overview of all contemplated
aspects, and is intended to neither identify key or critical
elements of all aspects nor delineate the scope of any or all
aspects. Its sole purpose is to present some concepts of one or
more aspects in a simplified form as a prelude to the more detailed
description that is presented later.
[0011] According to an embodiment, a method is provided for
processing procedures in selected interlace states, the method
comprising determining if a SelectedInterlaceOn state is entered,
generating a SelectedInterlaceEnabled indication and placing a most
recent SelectedInterlaceAssignment message in the public data.
[0012] According to another embodiment, a computer readable medium
is described having a first set of instructions for determining if
a SelectedInterlaceOn state is entered, a second set of
instructions for generating a SelectedInterlaceEnabled indication
and a third set of instructions for placing a most recent
SelectedInterlaceAssignment message in the public data.
[0013] According to yet another embodiment, an apparatus operable
in a wireless communication system is described which includes
means for determining if a SelectedInterlaceOn state is entered,
means for generating a SelectedInterlaceEnabled indication and
means for placing a most recent SelectedInterlaceAssignment message
in the public data.
[0014] According to yet another embodiment, a method is provided
for processing procedures in selected interlace states, the method
comprising determining if a SelectedInterlaceOff state is entered
and generating a SelectedInterlaceDisabled indication.
[0015] According to yet another embodiment, a computer-readable
medium is described having a first set of instructions for
determining if a SelectedInterlaceOff state is entered and a second
set of instructions for generating a SelectedInterlaceDisabled
indication.
[0016] According to yet another embodiment, an apparatus operable
in a wireless communication system is described which includes
means for determining if a SelectedInterlaceOff state is entered
and means for generating a SelectedInterlaceDisabled
indication.
[0017] To the accomplishment of the foregoing and related ends, the
one or more aspects comprise the features hereinafter fully
described and particularly pointed out in the claims. The following
description and the annexed drawings set forth in detail certain
illustrative aspects of the one or more aspects. These aspects are
indicative, however, of but a few of the various ways in which the
principles of various aspects may be employed and the described
aspects are intended to include all such aspects and their
equivalents.
BRIEF DESCRIPTION OF THE DRAWINGS
[0018] FIG. 1 illustrates aspects of a multiple access wireless
communication system.
[0019] FIG. 2 illustrates aspects of a transmitter and receiver in
a multiple access wireless communication system.
[0020] FIGS. 3A and 3B illustrate aspects of superframe structures
for a multiple access wireless communication system.
[0021] FIG. 4 illustrates aspect of a communication between an
access terminal and an access network.
[0022] FIG. 5A illustrates a flow diagram of a process used by an
access terminal or an access network.
[0023] FIG. 5B illustrates one or more processors configured for
processing procedures in selected interlace states.
[0024] FIG. 6A illustrates a flow diagram of a process used by an
access network or an access terminal.
[0025] FIG. 6B illustrates one or more processors configured for
processing procedures in selected interlace states.
DETAILED DESCRIPTION
[0026] Various aspects are now described with reference to the
drawings, wherein like reference numerals are used to refer to like
elements throughout. In the following description, for purposes of
explanation, numerous specific details are set forth in order to
provide a thorough understanding of one or more aspects. It may be
evident, however, that such aspect(s) may be practiced without
these specific details. In other instances, well-known structures
and devices are shown in block diagram form in order to facilitate
describing one or more aspects.
[0027] Referring to FIG. 1, a multiple access wireless
communication system according to one aspect is illustrated. A
multiple access wireless communication system 100 includes multiple
cells, e.g. cells 102, 104, and 106. In the aspect of FIG. 1, each
cell 102, 104, and 106 may include an access point 150 that
includes multiple sectors. The multiple sectors are formed by
groups of antennas each responsible for communication with access
terminals in a portion of the cell. In cell 102, antenna groups
112, 114, and 116 each correspond to a different sector. In cell
104, antenna groups 118, 120, and 122 each correspond to a
different sector. In cell 106, antenna groups 124, 126, and 128
each correspond to a different sector.
[0028] Each cell includes several access terminals which are in
communication with one or more sectors of each access point. For
example, access terminals 130 and 132 are in communication base
142, access terminals 134 and 136 are in communication with access
point 144, and access terminals 138 and 140 are in communication
with access point 146.
[0029] Controller 130 is coupled to each of the cells 102, 104, and
106. Controller 130 may contain one or more connections to multiple
networks, e.g. the Internet, other packet based networks, or
circuit switched voice networks that provide information to, and
from, the access terminals in communication with the cells of the
multiple access wireless communication system 100. The controller
130 includes, or is coupled with, a scheduler that schedules
transmission from and to access terminals. In other aspects, the
scheduler may reside in each individual cell, each sector of a
cell, or a combination thereof.
[0030] As used herein, an access point may be a fixed station used
for communicating with the terminals and may also be referred to
as, and include some or all the functionality of, a base station, a
Node B, or some other terminology. An access terminal may also be
referred to as, and include some or all the functionality of, a
user equipment (UE), a wireless communication device, terminal, a
mobile station or some other terminology.
[0031] It should be noted that while FIG. 1, depicts physical
sectors, i.e. having different antenna groups for different
sectors, other approaches may be utilized. For example, utilizing
multiple fixed "beams" that each cover different areas of the cell
in frequency space may be utilized in lieu of, or in combination
with physical sectors. Such an approach is depicted and disclosed
in co-pending U.S. patent application Ser. No. 11/260,895, entitled
"Adaptive Sectorization in Cellular System."
[0032] Referring to FIG. 2, a block diagram of an aspect of a
transmitter system 210 and a receiver system 250 in a MIMO system
200 is illustrated. At transmitter system 210, traffic data for a
number of data streams is provided from a data source 212 to
transmit (TX) data processor 214. In an aspect, each data stream is
transmitted over a respective transmit antenna. TX data processor
214 formats, codes, and interleaves the traffic data for each data
stream based on a particular coding scheme selected for that data
stream to provide coded data.
[0033] The coded data for each data stream may be multiplexed with
pilot data using OFDM, or other orthogonalization or
non-orthogonalization techniques. The pilot data is typically a
known data pattern that is processed in a known manner and may be
used at the receiver system to estimate the channel response. The
multiplexed pilot and coded data for each data stream is then
modulated (i.e., symbol mapped) based on one or more particular
modulation schemes (e.g., BPSK, QSPK, M-PSK, or M-QAM) selected for
that data stream to provide modulation symbols. The data rate,
coding, and modulation for each data stream may be determined by
instructions performed on provided by processor 230.
[0034] The modulation symbols for all data streams are then
provided to a TX processor 220, which may further process the
modulation symbols (e.g., for OFDM). TX processor 220 then provides
N.sub.T modulation symbol streams to N.sub.T transmitters (TMTR)
222a through 222t. Each transmitter 222 receives and processes a
respective symbol stream to provide one or more analog signals, and
further conditions (e.g., amplifies, filters, and upconverts) the
analog signals to provide a modulated signal suitable for
transmission over the MIMO channel. N.sub.T modulated signals from
transmitters 222a through 222t are then transmitted from N.sub.T
antennas 224a through 224t, respectively.
[0035] At receiver system 250, the transmitted modulated signals
are received by N.sub.R antennas 252a through 252r and the received
signal from each antenna 252 is provided to a respective receiver
(RCVR) 254. Each receiver 254 conditions (e.g., filters, amplifies,
and downconverts) a respective received signal, digitizes the
conditioned signal to provide samples, and further processes the
samples to provide a corresponding "received" symbol stream.
[0036] An RX data processor 260 then receives and processes the
N.sub.R received symbol streams from N.sub.R receivers 254 based on
a particular receiver processing technique to provide N.sub.T
"detected" symbol streams. The processing by RX data processor 260
is described in further detail below. Each detected symbol stream
includes symbols that are estimates of the modulation symbols
transmitted for the corresponding data stream. RX data processor
260 then demodulates, deinterleaves, and decodes each detected
symbol stream to recover the traffic data for the data stream. The
processing by RX data processor 218 is complementary to that
performed by TX processor 220 and TX data processor 214 at
transmitter system 210.
[0037] RX data processor 260 may be limited in the number of
subcarriers that it may simultaneously demodulate, e.g. 512
subcarriers or 5 MHz, and such a receiver should be scheduled on a
single carrier. This limitation may be a function of its FFT range,
e.g. sample rates at which the processor 260 may operate, the
memory available for FFT, or other functions available for
demodulation. Further, the greater the number of subcarriers
utilized, the greater the expense of the access terminal.
[0038] The channel response estimate generated by RX processor 260
may be used to perform space, space/time processing at the
receiver, adjust power levels, change modulation rates or schemes,
or other actions. RX processor 260 may further estimate the
signal-to-noise-and-interference ratios (SNRs) of the detected
symbol streams, and possibly other channel characteristics, and
provides these quantities to a processor 270. RX data processor 260
or processor 270 may further derive an estimate of the "operating"
SNR for the system. Processor 270 then provides channel state
information (CSI), which may comprise various types of information
regarding the communication link and/or the received data stream.
For example, the CSI may comprise only the operating SNR. In other
aspects, the CSI may comprise a channel quality indicator (CQI),
which may be a numerical value indicative of one or more channel
conditions. The CSI is then processed by a TX data processor 278,
modulated by a modulator 280, conditioned by transmitters 254a
through 254r, and transmitted back to transmitter system 210.
[0039] At transmitter system 210, the modulated signals from
receiver system 250 are received by antennas 224, conditioned by
receivers 222, demodulated by a demodulator 240, and processed by a
RX data processor 242 to recover the CSI reported by the receiver
system. The reported CSI is then provided to processor 230 and used
to (1) determine the data rates and coding and modulation schemes
to be used for the data streams and (2) generate various controls
for TX data processor 214 and TX processor 220. Alternatively, the
CSI may be utilized by processor 270 to determine modulation
schemes and/or coding rates for transmission, along with other
information. This may then be provided to the transmitter which
uses this information, which may be quantized, to provide later
transmissions to the receiver.
[0040] Processors 230 and 270 direct the operation at the
transmitter and receiver systems, respectively. Memories 232 and
272 provide storage for program codes and data used by processors
230 and 270, respectively.
[0041] At the receiver, various processing techniques may be used
to process the N.sub.R received signals to detect the N.sub.T
transmitted symbol streams. These receiver processing techniques
may be grouped into two primary categories (i) spatial and
space-time receiver processing techniques (which are also referred
to as equalization techniques); and (ii) "successive
nulling/equalization and interference cancellation" receiver
processing technique (which is also referred to as "successive
interference cancellation" or "successive cancellation" receiver
processing technique).
[0042] While FIG. 2 discusses a MIMO system, the same system may be
applied to a multi-input single-output system where multiple
transmit antennas, e.g. those on a base station, transmit one or
more symbol streams to a single antenna device, e.g. a mobile
station. Also, a single output to single input antenna system may
be utilized in the same manner as described with respect to FIG.
2.
[0043] The transmission techniques described herein may be
implemented by various means. For example, these techniques may be
implemented in hardware, firmware, software, or a combination
thereof. For a hardware implementation, the processing units at a
transmitter may be implemented within one or more application
specific integrated circuits (ASICs), digital signal processors
(DSPs), digital signal processing devices (DSPDs), programmable
logic devices (PLDs), field programmable gate arrays (FPGAs),
processors, controllers, micro-controllers, microprocessors,
electronic devices, other electronic units designed to perform the
functions described herein, or a combination thereof. The
processing units at a receiver may also be implemented within one
or more ASICs, DSPs, processors, and so on.
[0044] For a software implementation, the transmission techniques
may be implemented with modules (e.g., procedures, functions, and
so on) that perform the functions described herein. The software
codes may be stored in a memory (e.g., memory 230, 272x or 272y in
FIG. 2) and executed by a processor (e.g., processor 232, 270x or
270y). The memory may be implemented within the processor or
external to the processor.
[0045] It should be noted that the concept of channels herein
refers to information or transmission types that may be transmitted
by the access point or access terminal. It does not require or
utilize fixed or predetermined blocks of subcarriers, time periods,
or other resources dedicated to such transmissions.
[0046] Referring to FIGS. 3A and 3B, aspects of superframe
structures for a multiple access wireless communication system are
illustrated. FIG. 3A illustrates aspects of superframe structures
for a frequency division duplexed (FDD) multiple access wireless
communication system, while FIG. 3B illustrates aspects of
superframe structures for a time division duplexed (TDD) multiple
access wireless communication system. The superframe preamble may
be transmitted separately for each carrier or may span all of the
carriers of the sector.
[0047] In both FIGS. 3A and 3B, the forward link transmission is
divided into units of superframes. A superframe may consist of a
superframe preamble followed by a series of frames. In an FDD
system, the reverse link and the forward link transmission may
occupy different frequency bandwidths so that transmissions on the
links do not, or for the most part do not, overlap on any frequency
subcarriers. In a TDD system, N forward link frames and M reverse
link frames define the number of sequential forward link and
reverse link frames that may be continuously transmitted prior to
allowing transmission of the opposite type of frame. It should be
noted that the number of N and M may be vary within a given
superframe or between superframes.
[0048] In both FDD and TDD systems each superframe may comprise a
superframe preamble. In certain aspects, the superframe preamble
includes a pilot channel that includes pilots that may be used for
channel estimation by access terminals, a broadcast channel that
includes configuration information that the access terminal may
utilize to demodulate the information contained in the forward link
frame. Further acquisition information such as timing and other
information sufficient for an access terminal to communicate on one
of the carriers and basic power control or offset information may
also be included in the superframe preamble. In other cases, only
some of the above and/or other information may be included in this
superframe preamble.
[0049] As shown in FIGS. 3A and 3B, the superframe preamble is
followed by a sequence of frames. Each frame may consist of a same
or a different number of OFDM symbols, which may constitute a
number of subcarriers that may simultaneously utilized for
transmission over some defined period. Further, each frame may
operate according to a symbol rate hopping mode, where one or more
non-contiguous OFDM symbols are assigned to a user on a forward
link or reverse link, or a block hopping mode, where users hop
within a block of OFDM symbols. The actual blocks or OFDM symbols
may or may not hop between frames.
[0050] FIG. 4 illustrates communication between an access terminal
402 and an access network for processing procedures in selected
interlace states in an Open state using a communication link 406.
In a selected interlace mode, the access network sends certain SSCH
blocks to the access terminal on a set of interlaces called the
Selected Interlace Set. This is described in more detail in
Provisional Application Ser. No. 60/731,126, entitled "METHODS AND
APPARATUS FOR PROVIDING MOBILE BROADBAND WIRELESS LOWER MAC", filed
Oct. 27, 2005, assigned to the assignee hereof, and expressly
incorporated herein by reference. The communication link may be
implemented using communication protocols/standards such as World
Interoperability for Microwave Access (WiMAX), infrared protocols
such as Infrared Data Association (IrDA), short-range wireless
protocols/technologies, Bluetooth.RTM. technology, ZigBee.RTM.
protocol, ultra wide band (UWB) protocol, home radio frequency
(HomeRF), shared wireless access protocol (SWAP), wideband
technology such as a wireless Ethernet compatibility alliance
(WECA), wireless fidelity alliance (Wi-Fi Alliance), 802.11 network
technology, public switched telephone network technology, public
heterogeneous communications network technology such as the
Internet, private wireless communications network, land mobile
radio network, code division multiple access (CDMA), wideband code
division multiple access (WCDMA), universal mobile
telecommunications system (UMTS), advanced mobile phone service
(AMPS), time division multiple access (TDMA), frequency division
multiple access (FDMA), orthogonal frequency division multiple
(OFDM), orthogonal frequency division multiple access (OFDMA),
orthogonal frequency division multiple FLASH (OFDM-FLASH), global
system for mobile communications (GSM), single carrier (1.times.)
radio transmission technology (RTT), evolution data only (EV-DO)
technology, general packet radio service (GPRS), enhanced data GSM
environment (EDGE), high speed downlink data packet access (HSPDA),
analog and digital satellite systems, and any other
technologies/protocols that may be used in at least one of a
wireless communications network and a data communications
network.
[0051] FIG. 5A, illustrates a flow diagram of process 500,
according to an embodiment. At 502, it is determined if a
SelectedInterlaceOn state is entered. At 504, a
SelectedInterlaceEnabled indication is generated. At 506, the most
recent SelectedInterlaceAssignment message is placed in the public
data.
[0052] FIG. 5B, illustrates a processor 550 configured to process
Selected interlace states. The processor referred to may be
electronic devices and may comprise one or more processors
configured to process procedures in selected interlace states.
Processor 552 is configured to determine if a SelectedInterlaceOn
state is entered, processor 554 is configured to generate a
SelectedInterlaceEnabled indication and processor 556 is configured
to place the most recent SelectedInterlaceAssignment message in the
public data. The functionality of the discrete processors 552 to
556 depicted in the figure may be combined into a single processor
558. A 5memory 560 is also coupled to the processor 558
[0053] In an embodiment, an apparatus is described which includes
means for determining if a SelectedInterlaceOn state is entered,
means for generating a SelectedInterlaceEnabled indication and
means for placing the most recent SelectedInterlaceAssignment
message in the public data. The means described herein may comprise
one or more processors.
[0054] FIG. 6A illustrates a flow diagram of process 600, according
to another embodiment. At 602, it is determined if a
SelectedInterlaceOff state is entered and at 604, a
SelectedInterlaceDisabled indication is generated.
[0055] FIG. 6B illustrates processor 650 configured to process
Selected interlace states. The processor referred to may be
electronic devices and may comprise one or more processors
configured to process procedures in selected interlace states.
Processor 652 is configured to determine if a SelectedInterlaceOff
state is entered and processor 654 is configured to generate a
SelectedInterlaceDisabled indication. The functionality of the
discrete processors 652 to 654 depicted in the figure may be
combined into a single processor 656. A memory 658 is also coupled
to the processor 656.
[0056] In an embodiment, an apparatus is described which includes
means for determining if a SelectedInterlaceOff state is entered
and means for generating a SelectedInterlaceDisabled indication.
The means described herein may comprise one or more processors.
[0057] Furthermore, embodiments may be implemented by hardware,
software, firmware, middleware, microcode, or any combination
thereof. When implemented in software, firmware, middleware or
microcode, the program code or code segments to perform the
necessary tasks may be stored in a machine readable medium such as
a separate storage(s) not shown. A processor may perform the
necessary tasks. A code segment may represent a procedure, a
function, a subprogram, a program, a routine, a subroutine, a
module, a software package, a class, or any combination of
instructions, data structures, or program statements. A code
segment may be coupled to another code segment or a hardware
circuit by passing and/or receiving information, data, arguments,
parameters, or memory contents. Information, arguments, parameters,
data, etc. may be passed, forwarded, or transmitted via any
suitable means including memory sharing, message passing, token
passing, network transmission, etc.
[0058] Various modifications to these aspects will be readily
apparent to those skilled in the art, and the generic principles
defined herein may be applied to other aspects. Thus, the
description is not intended to be limited to the aspects shown
herein but is to be accorded the widest scope consistent with the
principles and novel features disclosed herein.
* * * * *