U.S. patent application number 12/167157 was filed with the patent office on 2008-11-27 for stacked chip semiconductor device.
This patent application is currently assigned to RENESAS TECHNOLOGY CORP.. Invention is credited to Manabu TSUNOZAKI.
Application Number | 20080290493 12/167157 |
Document ID | / |
Family ID | 34616575 |
Filed Date | 2008-11-27 |
United States Patent
Application |
20080290493 |
Kind Code |
A1 |
TSUNOZAKI; Manabu |
November 27, 2008 |
STACKED CHIP SEMICONDUCTOR DEVICE
Abstract
A stacked chip semiconductor device whose size is substantially
reduced by high density packaging of two or more semiconductor
chips. In the semiconductor device, four semiconductor chips are
stacked over a printed wiring board. The bottom semiconductor chip
has an interface circuit which includes a buffer and an
electrostatic discharge protection circuit. All signals that these
semiconductor chips receive and send are inputted or outputted
through the interface circuit of the bottom semiconductor chip.
Since the other semiconductor chips require no interface circuit,
the semiconductor device is compact.
Inventors: |
TSUNOZAKI; Manabu; (Hino,
JP) |
Correspondence
Address: |
MILES & STOCKBRIDGE PC
1751 PINNACLE DRIVE, SUITE 500
MCLEAN
VA
22102-3833
US
|
Assignee: |
RENESAS TECHNOLOGY CORP.
|
Family ID: |
34616575 |
Appl. No.: |
12/167157 |
Filed: |
July 2, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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10994243 |
Nov 23, 2004 |
7420281 |
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12167157 |
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Current U.S.
Class: |
257/686 ;
257/E23.18; 257/E25.013 |
Current CPC
Class: |
H01L 2224/05554
20130101; H01L 2924/00014 20130101; H01L 2924/15311 20130101; H01L
23/60 20130101; H01L 2224/32225 20130101; H01L 2224/49175 20130101;
H01L 2924/00014 20130101; H01L 24/48 20130101; H01L 2224/48091
20130101; H01L 2924/13091 20130101; H01L 2924/15311 20130101; H01L
2924/00 20130101; H01L 2224/32145 20130101; H01L 2924/00 20130101;
H01L 2924/00 20130101; H01L 2224/45015 20130101; H01L 2924/00012
20130101; H01L 2924/00012 20130101; H01L 2924/00012 20130101; H01L
2224/48145 20130101; H01L 2224/32225 20130101; H01L 2924/207
20130101; H01L 2224/73265 20130101; H01L 2224/48227 20130101; H01L
2924/00 20130101; H01L 2224/48227 20130101; H01L 2224/48227
20130101; H01L 2924/00 20130101; H01L 2924/00 20130101; H01L
2924/00014 20130101; H01L 2224/48145 20130101; H01L 2224/48227
20130101; H01L 2224/45099 20130101; H01L 2224/32225 20130101; H01L
2224/32145 20130101; H01L 24/73 20130101; H01L 2224/48227 20130101;
H01L 24/49 20130101; H01L 2225/06562 20130101; H01L 2224/73265
20130101; H01L 2224/73265 20130101; H01L 2224/32145 20130101; H01L
25/0657 20130101; H01L 2224/73265 20130101; H01L 2924/1301
20130101; H01L 2224/48091 20130101; H01L 2924/1301 20130101; H01L
2924/14 20130101; H01L 2924/00014 20130101; H01L 2924/3011
20130101; H01L 2924/13091 20130101; H01L 2224/48145 20130101; H01L
2224/49175 20130101; H01L 2224/73265 20130101; H01L 2924/14
20130101; H01L 2224/49175 20130101 |
Class at
Publication: |
257/686 ;
257/E23.18 |
International
Class: |
H01L 23/02 20060101
H01L023/02 |
Foreign Application Data
Date |
Code |
Application Number |
Nov 28, 2003 |
JP |
2003-398469 |
Claims
1-14. (canceled)
15. A semiconductor device comprising: a printed wiring board
having a main surface and a back surface; a first semiconductor
chip having an external connection electrode connected with
external connection means for receiving a signal from outside of
the semiconductor device, first electrostatic discharge protection
means connected with the external connection electrode, a first
internal connection electrode connected with the external
connection electrode through the first electrostatic discharge
protection means and through an input buffer, and a first internal
circuit connected to the first internal connection electrode, the
first semiconductor chip being mounted on the main surface of the
printed wiring board; a bonding wire having an end connected with
the first internal connection electrode; and a second semiconductor
chip having a second internal connection electrode connected with
another end of the bonding wire, a second internal circuit
connected to the second internal connection electrode, and second
electrostatic discharge protection means connected with the second
internal connection electrode, the second electrostatic discharge
protection means having a smaller area size than the first
electrostatic discharge protection means, and the second
semiconductor chip being stacked on the first semiconductor chip so
that a part of the second semiconductor chip overlaps the first
semiconductor chip; wherein each of a size of the external
connection electrode and a size of the second internal connection
electrode is less than a size of the first internal connection
electrode.
16. The semiconductor device of claim 15, wherein the first
semiconductor chip has a first side and a second side; wherein the
external connection electrode and the first internal connection
electrode are gathered in a part of the first side of the first
semiconductor chip; wherein the second semiconductor chip has a
first side and a second side; and wherein the second semiconductor
chip is stacked on the first semiconductor chip so that the
external connection electrode and the first internal connection
electrode are exposed from the second semiconductor chip and the
first side of the first semiconductor chip is arranged side by side
with the first side of the second semiconductor chip.
17. The semiconductor device according to claim 15, wherein the
first semiconductor chip includes a memory controller; and wherein
the second semiconductor chip includes a semiconductor memory
controlled by the memory controller.
18. The semiconductor device according to claim 15, wherein the
first semiconductor chip and the second semiconductor chip include
semiconductor memories.
19. The semiconductor device according to claim 18, wherein the
first semiconductor chip includes a counter circuit which generates
address signals for the first semiconductor chip and the second
semiconductor chip from clock signals inputted from outside the
semiconductor device.
20. The semiconductor device according to claim 19, wherein the
first semiconductor chip includes a security portion for
encoding/decoding signals which are received from, or output to,
outside the semiconductor device.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] The present application claims priority from Japanese patent
application No. 2003-398469 filed on Nov. 28, 2003, the content of
which is hereby incorporated by reference into this
application.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to technology for
miniaturization of semiconductor integrated circuit devices and
more particularly to technology, which is effective for stacked
chip semiconductor devices in which two or more semiconductor chips
are stacked.
[0003] With the recent trend toward smaller and higher-performance
electronic systems, demand for smaller and higher-density
semiconductor integrated circuit devices is growing. One
widely-known technique for increasing the density of a package
almost equal in size to a semiconductor chip is a semiconductor
device with two or more semiconductor chips stacked which is called
a stacked CSP (Chip Size Package).
[0004] In this stacked chip semiconductor device, two or more
semiconductor chips are stacked in the center of a printed wiring
board and a lower semiconductor chip is larger than or equal to an
upper one.
[0005] When a lower semiconductor chip and an upper one are bonded,
an adhesive agent in the form of paste or film is coated over the
surface of the lower one, over which the upper one is laid.
[0006] Bonding pads are made around peripheral areas of the upper
and lower semiconductor chips and electrodes made on the printed
wiring board are connected with the bonding pads through bonding
wires.
[0007] In a stacked CSP memory module in which semiconductor chips
including semiconductor memories such as flash memories, DRAMs and
SRAMs are stacked, external connection terminals such as address
terminals and data input/output terminals (I/O terminals) are
shared in order to decrease the number of external connection
terminals.
[0008] One example of technology for miniaturization of stacked
chip semiconductor devices is that a package includes an ESD
protection circuit and other buffer circuits such as decoupling
capacitors, drivers and receivers which are provided on support
chips other than a core integrated circuit chip (for example, see
Patent Literature 1: Japanese Unexamined Patent Publication No. Hei
10 (1998)-41458).
SUMMARY OF THE INVENTION
[0009] However, the inventors have found that the above stacked
chip semiconductor device has the following problems.
[0010] Although the address terminals and data input/output
terminals are shared as mentioned above, the area efficiency in
chip layout is low because each semiconductor chip has a function
of interfacing with an externally connected module.
[0011] As a consequence, it may be difficult to miniaturize the
stacked chip semiconductor device and also the device may be not
cost-effective.
[0012] An object of the present invention is to provide a
substantially miniaturized stacked chip semiconductor device
through high density packaging of two or more semiconductor
chips.
[0013] The above and further objects and novel features of the
invention will more fully appear from the following detailed
description and accompanying drawings.
[0014] Typical aspects of the invention will be briefly outlined
below.
[0015] According to one aspect of the present invention, a
semiconductor device has a primary semiconductor chip and at least
one secondary semiconductor chip which are stacked. Here, the
primary semiconductor chip has a primary electrostatic discharge
protection circuit to be connected with an external connection
terminal; the secondary semiconductor chip has a secondary
electrostatic discharge protection circuit whose protection
capability is smaller than that of the primary electrostatic
discharge protection circuit; and an external signal is inputted
and outputted through the primary electrostatic discharge
protection circuit.
[0016] According to another aspect of the present invention, a
semiconductor device has a semiconductor chip for electrostatic
discharge protection, which has a primary electrostatic discharge
protection circuit, and at least one secondary semiconductor chip.
Here, the secondary semiconductor chip has a secondary
electrostatic discharge protection circuit whose protection
capability is smaller than that of the primary electrostatic
discharge protection circuit; and an external signal is inputted
and outputted through the primary electrostatic discharge
protection circuit.
[0017] Main advantageous effects, which are brought about by the
present invention, are as follows:
[0018] (1) A compact stacked chip semiconductor device is
realized.
[0019] (2) Power consumption of a stacked chip semiconductor device
is reduced.
[0020] (3) The above effects (1) and (2) contribute to
miniaturization of electronic systems and reduction in their power
consumption.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] FIG. 1 is a top view of a stacked chip semiconductor device
according to a first embodiment of the present invention;
[0022] FIG. 2 is a sectional view of the stacked chip semiconductor
device of FIG. 1;
[0023] FIG. 3 illustrates an interface circuit in the stacked chip
semiconductor device of FIG. 1;
[0024] FIG. 4 is a circuit diagram of an ESD protection circuit and
an input buffer which are incorporated in the interface circuit of
FIG. 3;
[0025] FIG. 5 is a circuit diagram of an output buffer incorporated
in the interface circuit of FIG. 3;
[0026] FIG. 6 is a top view of a stacked chip semiconductor device
according to another embodiment of the present invention;
[0027] FIG. 7 is a top view of a stacked chip semiconductor device
according to a second embodiment of the present invention;
[0028] FIG. 8 is a sectional view of the stacked chip semiconductor
device of FIG. 7;
[0029] FIG. 9 is a sectional view of a stacked chip semiconductor
device according to a third embodiment of the present
invention;
[0030] FIG. 10 is a sectional view of a stacked chip semiconductor
device according to another embodiment of the present
invention;
[0031] FIG. 11 shows a bit configuration in the memory of a stacked
chip semiconductor device according to another embodiment of the
present invention;
[0032] FIG. 12 shows a word address configuration in the memory of
a stacked chip semiconductor device according to another embodiment
of the present invention; and
[0033] FIG. 13 illustrates an interface circuit as another example
in a stacked chip semiconductor device according to another
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0034] Next, preferred embodiments of the present invention will be
described in detail referring to the accompanying drawings. In all
the drawings that illustrate the preferred embodiments, like
elements are designated by like reference numerals; and
descriptions of these elements will not be repeated.
First Embodiment
[0035] FIG. 1 is a top view of a stacked chip semiconductor device
according to a first embodiment of the present invention, FIG. 2 is
a sectional view of the stacked chip semiconductor device of FIG.
1, FIG. 3 illustrates an interface circuit in the stacked chip
semiconductor device of FIG. 1, FIG. 4 is a circuit diagram of an
ESD protection circuit and an input buffer which are incorporated
in the interface circuit of FIG. 3, and FIG. 5 is a circuit diagram
of an output buffer incorporated in the interface circuit of FIG.
3.
[0036] In the first embodiment, a stacked chip semiconductor device
1 consists of a BGA (Ball Grid Array) as a kind of surface mount
CSP. As shown in FIGS. 1 and 2, the semiconductor device 1 has a
printed wiring board 2, for example, made of BT (Bismaleimide
Triazine). On the back of the printed wiring board 2 is an array of
electrodes for connection.
[0037] The printed wiring board 2 has a stacked structure in which
semiconductor chips 3 to 6 are stacked in the center of its main
surface. The bottom semiconductor chip (primary semiconductor chip)
3 is bonded to the printed wiring board 2 through an adhesive agent
such as insulating resin.
[0038] The semiconductor chip (secondary semiconductor chip) 4 lies
over the semiconductor chip 3 through an adhesive agent such as
insulating resin. The semiconductor chip (secondary semiconductor
chip) 5 lies over the semiconductor chip 4 and the semiconductor
chip (secondary semiconductor chip) 6 lies over the semiconductor
chip 5. Likewise, these chips are bonded to each other through an
adhesive agent such as insulating resin.
[0039] The semiconductor chips 3 to 6 are comprised of
semiconductor memories such as nonvolatile memories. The bottom
semiconductor chip 3 has a memory section and an interface circuit
7.
[0040] The memory section comprises: a control circuit which
controls nonvolatile memory read, write and erase operations; a
decoder circuit which selects word lines to be accessed; and a
memory array including a sense amplifier which amplifies the bit
line potential and determines the data read from nonvolatile memory
cells. The interface circuit 7 carries out external input/output
and includes a buffer which temporarily stores data for external
input/output.
[0041] The semiconductor chips 4 to 6 respectively have memory
sections but no interface functions. The semiconductor chips 4 to 6
are equal in size (area) to each other and smaller than the
semiconductor chip 3.
[0042] Bonding electrodes 2a are arranged over the main surface of
the printed wiring board 2, along one side on the semiconductor
chip periphery. The bonding electrodes 2a are electrically
connected with connection electrodes by a wiring pattern HP formed
in the wiring layer of the printed wiring board 2. Solder bumps 2b
(spherical) are made as the connection electrodes on the back
surface of the printed wiring board 2.
[0043] External connection electrodes 3a are arranged near the
bonding electrodes 2a along one side on the periphery of the main
surface of the semiconductor chip 3. Internal connection electrodes
3b are arranged on the inside of the external connection electrodes
3a.
[0044] The internal connection electrodes 3b are, for example,
rectangular and have a larger area than the external connection
electrodes 3a. The internal connection electrodes 3b are connected
with the memory section of the semiconductor chip 3. The reason
that the internal connection electrodes 3b have a larger area than
the external connection electrodes 3a is that each internal
connection electrode 3b is to be connected to connection electrodes
4a, 5a and 6a of the semiconductor chips 4 to 6 through plural
bonding wires while each external connection electrode 3a is to be
connected through one bonding wire. This means that if only one
semiconductor chip 4 is laid over the semiconductor chip 3, the
internal connection electrodes may have the same area as the
external connection electrodes 3a. This applies throughout this
specification.
[0045] Electrodes (connection electrodes) 4a are arranged along one
side on the periphery of the main surface of the semiconductor chip
4. These electrodes 4a are each connected to the memory section of
the semiconductor chip 4. The semiconductor chip 4 is located in
the center of the semiconductor chip 3, adjacent to the internal
connection electrodes 3b.
[0046] Electrodes (connection electrodes) 5a are arranged along one
side on the periphery of the main surface of the semiconductor chip
5. These electrodes 5a are each connected to the memory section of
the semiconductor chip 5. The semiconductor chip 5 is located not
in the center of the semiconductor chip 4, but decentered (offset)
so that the electrodes 5a are exposed from the semiconductor chip 4
and close to the electrodes (connection electrodes) 6a.
[0047] Electrodes (connection electrodes) 6a are arranged along one
side on the periphery of the main surface of the semiconductor chip
6. These electrodes 6a are each connected to the memory section of
the semiconductor chip 6. Like the semiconductor chip 5, the
semiconductor chip 6 is decentered (offset) so that the electrodes
6a are exposed from the semiconductor chip 5 and close to the
electrodes (connection electrodes) 5a. The semiconductor chips 4 to
6 are sifted to the extent that their electrodes 4a to 6a are
exposed and can be connected with the internal connection
electrodes 3b.
[0048] The semiconductor chips 5 and 6 each partially protrude from
the projection plane shared with the underlying chip and there is
space beneath their protruding parts. Part of the interface circuit
7 of the semiconductor chip 3 lies in the space beneath the
protruding parts. Since the semiconductor chip 3 is larger than the
semiconductor chips 4 to 6 and they are stacked in this way, the
packaging efficiency is improved.
[0049] The bonding electrodes 2a of the printed wiring board 2 are
connected to the external connection electrodes 3a of the
semiconductor chip 3 through bonding wires 8. The external
connection electrodes 3a and the internal connection electrodes 3b
are connected each other through the interface circuit 7 of the
semiconductor chip 3. The internal connection electrodes 3b and the
electrodes 4a to 6a are connected each other through bonding wires
9 to 11.
[0050] This means that signals which not only the memory section of
the semiconductor chip 3 but also the memory sections of the
semiconductor chips 4 to 6 receive and send are all inputted or
outputted through the interface circuit 7 of the semiconductor chip
3.
[0051] Next, the structure of the interface circuit 7 of the
semiconductor chip 3 will be explained.
[0052] FIG. 3 shows the external connection electrodes 3a, internal
connection electrodes 3b and interface circuit 7 of the
semiconductor chip 3.
[0053] As shown in FIG. 3, the external connection electrodes 3a
are located on the right and the internal connection electrodes 3b
on the left and the interface circuit 7 in the center. However, the
layout with these elements of the semiconductor chip 3 is not
limited thereto.
[0054] As shown in FIG. 3, the external connection electrodes 3a
are arranged from top to bottom as follows: external connection
electrodes 3.sub.a1 which are connected to external address buses;
external connection electrodes 3.sub.a2 which receive control
signals; external connection electrodes 3.sub.a3 which are
connected to external data buses; and an external connection
electrode 3.sub.a4 which is connected to an external power
line.
[0055] As shown in FIG. 3, the internal connection electrodes 3b
are arranged from top to bottom as follows: internal connection
electrodes 3.sub.b1 which are connected to internal address buses;
internal connection electrodes 3.sub.b2 which receive control
signals; internal connection electrodes 3.sub.b3 which are
connected to internal data buses; and an internal connection
electrode 3.sub.b4 which is connected to an internal power
line.
[0056] The interface circuit 7 includes electrostatic discharge
protection circuits (primary ESD protection circuits) 12, input
buffers 13, input/output buffers 14, a decoder 15 and a power
supply circuit 16.
[0057] The external connection electrodes 3.sub.a1 and 3.sub.a2 are
connected to the internal connection electrodes 3.sub.b1 and
3.sub.b2 through the ESD protection circuits 12 and input buffers
13, respectively.
[0058] Some of the internal connection electrodes 3.sub.b1 and
3.sub.b2 are connected with output of the input buffers 13
connected to the corresponding external connection electrodes
3.sub.a1 and 3.sub.a2 via the decoder 15. And the decoder 15
further receives the address signals and the control signals.
[0059] The decoder 15 decodes the address signal and control signal
which it has received, and generates and outputs a chip select
signal which is for selecting whether to activate or inactivate the
memory sections of the semiconductor chips 3 to 6. In writing
operation, signals, which are inputted through external data bus,
are outputted through an input/output buffer 14 to an internal
connection electrode 3.sub.b3, which is connected to an internal
data bus. This input/output changeover in the input/output buffer
14 is carried out according to some of the control signals which
come from the outside.
[0060] The power supply circuit 16 transforms the voltage level of
power supplied through the external connection electrode 3.sub.a4
from an external power line to generate internal power supply
voltage. The internal power supply voltage generated by the power
supply circuit 16 is supplied through the internal connection
electrode 3.sub.b4 to the semiconductor chips 3 to 6. The power
supply circuit 16 is capable of generating a plurality of internal
power supply voltages, which are different voltage levels from And
the power supply circuit 16 is capable of including not only the
voltage step down circuit but also the voltage step up circuit, for
example a charge pump circuit, etc.
[0061] Furthermore, the interface circuit 7 may also include a
circuit which encodes or decodes address signals or data signals.
This substantially improves security of the stacked chip
semiconductor device 1.
[0062] FIG. 4 illustrates an ESD protection circuit 12 and an input
buffer 13 connected between an external connection electrode
3.sub.a1 and an internal connection electrode 3.sub.b1.
[0063] The ESD protection circuit 12 prevents discharge current
from reaching the internal circuits of the semiconductor chips 3 to
6 or limits the discharge current. The ESD protection circuit 12
comprises a thyristor 17, a resistor 18, and a clamp MOS transistor
19. The input buffer 13 is comprised of a resistor 20 and a NAND
circuit 21.
[0064] The external connection electrode 3.sub.a1 is connected to
one end of the resistor 18. The thyristor 17 is connected between
the one end of the resistor 18 and reference potential VSS. The
other end of the resistor 18 is connected to one end of the input
buffer 13.
[0065] The clamp MOS transistor 19 is connected between the other
end of the resistor 18 and reference potential VSS. The other end
of the resistor 20 is connected to one input of the NAND circuit
21. And the other input of the NAND circuit 21 is connected to a
control signal (write enable signal, etc) output from the internal
circuit of the semiconductor chip 3. The output of the NAND circuit
21 serves as an output of the input buffer 13.
[0066] The ESD protection circuit 12 is a high ESD tolerance
circuit. In order to prevent breakdown of the ESD protection
circuit 12 itself due to high voltage, its elements are larger than
in an internal circuit of a chip core.
[0067] On the other hand, since the semiconductor chips 4 to 6
receive and send signals through the interface circuit 7 of the
semiconductor chip 3, they only have to withstand at most
electrostatic discharge which can occur in an ESD-controlled
manufacturing environment. Therefore, they incorporate a relatively
simple ESD protection circuit (secondary ESD protection circuit)
which is, for example, only composed of a diode and a resistor.
[0068] Because the semiconductor chips 4 to 6 do not require a
relatively large ESD protection circuit 12, it is possible to
decrease their area for layout and achieve remarkable cost
reduction.
[0069] Next, the circuitry of the input/output buffer 14 (FIG. 3)
will be explained.
[0070] The input/output buffer 14 is comprised of an input buffer
13 (FIG. 4) and an output buffer 21. FIG. 5 illustrates the
structure of the output buffer 21. The output buffer 21 is
comprised of an inverter 22, AND circuits 23 and 24, and
transistors 25 and 26 for data output.
[0071] The input of the inverter 22 and one input of the AND
circuit 23 are connected to the internal connection electrode
3.sub.b3. The output of the inverter 22 is connected to one input
of the AND circuit 24.
[0072] The other inputs of the AND circuits 23 and 24 are connected
in a way to receive an output select signal from the internal
circuit of the semiconductor chip 3. The output of the AND circuit
23 is connected to the gate of the transistor 25 and the output of
the AND circuit 23 is connected to the gate of the transistor
26.
[0073] The transistors 25 and 26 consist of, for example, N-channel
MOSs (Metal Oxide Semiconductors). They are connected in series
between the power supply voltage VCC and the reference potential
VSS and the joint of the transistors 25 and 26 is connected to the
external connection electrode 3.sub.a3.
[0074] A signal from one of the semiconductor chips 3 to 6 goes
through the internal connection electrode 3.sub.b3 to the output
buffer 21. In this output buffer 21, whether to output the signal
or make a high impedance condition is selected according to an
output select signal which enters the other inputs of the AND
circuits 23 and 24.
[0075] The gate width of the transistors 25 and 26 is large enough
to obtain a sufficient source-drain current to drive another device
(MOS transistor) externally connected with the stacked chip
semiconductor device 1 and their gate length is also large enough
to obtain a required ESD tolerance at the same time.
[0076] Therefore, the transistors 25 and 26 occupy a large space.
However, the interface circuit 7 is shared among the semiconductor
chips 3 to 6 and the size of the semiconductor chips 4 to 6 can be
remarkably reduced.
[0077] Hence, according to this embodiment, sharing of the
interface circuit 7 of the semiconductor chip 3 permits the use of
a fewer number of large transistors necessary for the interface
circuit 7, thereby leading to reduction in the cost of the stacked
chip semiconductor device 1 and reduction in its power
consumption.
[0078] Although the external connection electrodes 3a are arranged
along one side on the periphery of the main surface of the
semiconductor chip 3 in the first embodiment, instead they may be
arranged along two or more sides. For example, as shown in FIG. 6,
in the stacked chip semiconductor device 1a, external connection
electrodes 3a are arranged along the four sides of the
semiconductor chip 3. In this case, the bonding electrodes 2a of
the printed wiring board 2 are also arranged along the four sides
of the printed wiring board 2 and the bonding electrodes 2a and the
external connection electrodes 3a are connected through bonding
wires 8 respectively.
[0079] This allows more latitude in layout and permits reduction in
the size of the semiconductor chip 3.
Second Embodiment
[0080] FIG. 7 is a top view of a stacked chip semiconductor device
according to the second embodiment of the present invention; and
FIG. 8 is a sectional view of the stacked chip semiconductor device
of FIG. 7.
[0081] As shown in FIGS. 7 and 8, in the second embodiment, the
stacked chip semiconductor device 1b consists of a BGA with a
stacked structure. Like the first embodiment (see FIGS. 1 and 2),
the stacked chip semiconductor device 1b includes a printed wiring
board 2, solder bumps 2b, semiconductor chips 3 to 6, bonding wires
8a and bonding wires 9 to 11. The difference from the first
embodiment is the layout of the interface circuit of the
semiconductor chip 3.
[0082] The interface circuit 7 is located not on the periphery of
the external connection electrodes 3a and internal connection
electrodes 3b on the semiconductor chip 3, but on the side facing
the side where the external connection electrodes 3a are
located.
[0083] The connection electrodes are located on the back surface of
the printed wiring board 2 as an array. Semiconductor chips 3 to 6
are stacked in the center of the main surface of the printed wiring
board 2.
[0084] The bonding electrodes 2a are located on the left side of
the periphery of the main surface of the printed wiring board 2.
The bonding electrodes 2a are electrically connected with
connection electrodes by a wiring pattern HP formed in the wiring
layer of the printed wiring board 2. Solder bumps 2b (spherical)
are made as the connection electrodes on the back surface of the
printed wiring board 2.
[0085] The electrodes 3a are located near the bonding electrodes
2a, on the left side of the periphery of the main surface of the
semiconductor chip 3 and the interface circuit 7 is located on the
inside of the external connection electrodes 3a.
[0086] The internal connection electrodes 3b are located on the
right side of the periphery of the main surface of the
semiconductor chip 3. They are, for example, rectangular, and
larger than the external connection electrodes 3a. They are
connected to the memory section of the semiconductor chip 3.
[0087] Like the first embodiment, electrodes 4a to 6a are located
on the right side of the periphery of the main surface of each of
the semiconductor chips 4 to 6. These semiconductor chips 4 to 6
are stacked in a staggered manner.
[0088] The bonding electrodes 2a of the printed wiring board 2 are
connected to the external connection electrodes 3a of the
semiconductor chip 3 through bonding wires 8a. The external
connection electrodes 3a and the internal connection electrodes 3b
are connected with each other through the interface circuit 7 and
the internal wiring of the semiconductor chip 3. The internal
connection electrodes 3b and the electrodes 4a to 6a are connected
each other through bonding wires 9 to 11.
[0089] Thus, in the second embodiment, for the semiconductor chip
3, the external connection electrodes 3a and internal connection
electrodes 3b are separately connected so that the area efficiency
of the semiconductor chip 3 is improved.
Third Embodiment
[0090] FIG. 9 is a sectional view of a stacked chip semiconductor
device according to the third embodiment of the present
invention.
[0091] In the third embodiment, a stacked chip semiconductor device
1c is the same as in the first embodiment except that a
semiconductor chip (semiconductor chip with ESD protection) 27 is
newly added and semiconductor chips 3.sub.l, and 4 to 6 only have
memory sections.
[0092] As shown in FIG. 9, in the stacked chip semiconductor device
1c, the connection electrodes are located on the back surface of
the printed wiring board 2 as an array. The semiconductor chips
3.sub.l, and 4 to 6 are stacked in the center of the main surface
of the printed wiring board 2 and the additional semiconductor chip
27, on which an interface circuit 7 (FIG. 3) is structured, lies
over the semiconductor chip 6.
[0093] The bonding electrodes 2a are located on the right side of
the periphery of the main surface of the printed wiring board 2.
The bonding electrodes 2a are electrically connected with
connection electrodes by a wiring pattern HP formed in the wiring
layer of the printed wiring board 2. Solder bumps 2b (spherical)
are made as the connection electrodes on the back surface of the
printed wiring board 2.
[0094] External connection electrodes 27a are located on the left
side of the periphery of the main surface of the semiconductor chip
27 and internal connection electrodes 27b are located on the right
of the external connection electrodes 27a. The internal connection
electrodes 27b are, for example, rectangular, and larger than the
external connection electrodes 3a. They are connected to the memory
sections of the semiconductor chips 3.sub.l and 4 to 6.
[0095] Electrodes (connection electrodes) 28 are located on the
right side of the periphery of the main surface of the
semiconductor chip (secondary semiconductor chip) 3.sub.l.
Electrodes 4a to 6a are provided on the right side of the periphery
of the main surfaces of the semiconductor chips 4 to 6.
[0096] The bonding electrodes 2a of the printed wiring board 2 are
connected to the external connection electrodes 27a of the
semiconductor chip 27 through bonding wires 29. The external
connection electrodes 27a and the internal connection electrodes
27b are connected each other through the interface circuit 7 of the
semiconductor chip 27.
[0097] The internal connection electrodes 27b of the semiconductor
chip 27 and the electrodes 28 and 3a to 6a of the semiconductor
chips 3.sub.l and 4 to 6 are connected through bonding wires 30 to
33.
[0098] Thus, in the third embodiment, the addition of the
semiconductor chip 27 with an interface function makes it possible
to reduce the sizes of the semiconductor chips 3.sub.l and 4 to 6
and realize a more compact stacked chip semiconductor device
1c.
[0099] When the stacked chip semiconductor device 1c is used to
make a multimedia card, it is possible to use the semiconductor
chip 27 as a control chip (memory controller).
[0100] Although the semiconductor chip 27 is located at the top in
the third embodiment, instead it may lie side-by-side with the
semiconductor chip 3.sub.l at the bottom as shown in FIG. 10.
[0101] In this case, the electrodes 28 of the semiconductor chip
3.sub.l are located on the left in the peripheral area and are
connected to the internal electrodes 27b of the semiconductor chip
27 through bonding electrodes 34 provided on the printed wiring
board 2, wiring pattern HP1 and bonding wires 35.
[0102] When the semiconductor chip 27 is located at the bottom in
this way, if it incorporates a circuit (security means) which
encodes/decodes address signals and/or data signals, the security
of the stacked chip semiconductor device 1c is substantially
increased.
[0103] This means that, because the semiconductor chip 27 is hard
to detach, someone who tries to reverse-engineer the device might
break the semiconductor chip 27.
[0104] So far, preferred embodiments of the invention made by the
inventors have been concretely described. However, obviously the
present invention is not limited to the above embodiments but may
be embodied in other various forms without departing from the scope
and spirit thereof.
[0105] In the first to third embodiments, input/output buses for
the memory sections of the semiconductor chips used in the stacked
chip semiconductor device need not consist of 2.sup.n bits.
[0106] For example, it is also possible that when a semiconductor
chip (primary semiconductor chip) 36, which has a memory of 1 M
words.times.5 bits and an interface circuit 7, is combined with a
semiconductor chip (secondary semiconductor chip) 37 having a
memory of 1 M words.times.3 bits as shown in FIG. 11, they are
regarded as a single memory of 1 M words.times.8 bits by an
external interface.
[0107] Consequently, the memory packaging form can be diversified
to suit the available packaging space and the device can be mounted
in a module or memory card whose shape is restricted, and its
memory capacity can be increased.
[0108] In the first to third embodiments, address space in the
memory sections of the semiconductor chips used in the stacked chip
semiconductor device need not consist of 2.sup.n bits.
[0109] For example, it is also possible to combine a semiconductor
chip (primary semiconductor chip) 38, which has a memory of 5 M
words.times.8 bits and an interface circuit 7, with a semiconductor
chip (secondary semiconductor chip) 39 having a memory of 3 M
words.times.8 bits as shown in FIG. 12.
[0110] In this case, the interface circuit 7 incorporates a decoder
circuit and 8 M words address is decoded by the decoder circuit and
distributed to 5 M words address and 3 Ms word address so that an
external interface regards this as a memory of 8 M words.times.8
bits.
[0111] Consequently, the memory packaging form can be diversified
to suit the available packaging space and the device can be mounted
in a module or memory card whose shape is restricted, and its
memory capacity can be increased.
[0112] A function of protection against data leaks can be provided
by adding a distribution rule encoding circuit to a decoder circuit
which distributes the address space so that the security of the
stacked chip semiconductor device is increased.
[0113] In the first to third embodiments, it is also possible to
add a counter circuit which generates address signals for the
semiconductor chips from clock signals.
[0114] FIG. 13 shows a stacked chip semiconductor device which
includes two semiconductor chips 40 and 41. The semiconductor chip
(primary semiconductor chip) 40 has a memory section and an
interface circuit 7 and the semiconductor chip (secondary
semiconductor chip) 41 only has a memory section. In this case, a
counter circuit 42 is structured in the interface circuit 7 of the
semiconductor chip 40.
[0115] Hence, a memory which permits serial access can be
constituted using a random access memory, and a large capacity
memory (stacked chip semiconductor device) with a smaller number of
external connection terminals can be realized.
[0116] The semiconductor chip packaging technology used for
semiconductor devices according to the present invention is
suitable for high density packaging of stacked semiconductor
chips.
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