U.S. patent application number 11/987156 was filed with the patent office on 2008-11-20 for semiconductor device and method for fabricating the same.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Yuka Hayami, Katsuaki Okoshi, Takashi Saiki.
Application Number | 20080283924 11/987156 |
Document ID | / |
Family ID | 35459690 |
Filed Date | 2008-11-20 |
United States Patent
Application |
20080283924 |
Kind Code |
A1 |
Saiki; Takashi ; et
al. |
November 20, 2008 |
Semiconductor device and method for fabricating the same
Abstract
The semiconductor device comprises a silicon wafer 10, a
multilayer interconnection 12 buried in inter-layer insulation film
formed on the upper surface of the silicon wafer 10, and a silicon
nitride film 16b which is formed on the back surface of the silicon
wafer 10 and is an insulation film having a tensile stress,
relaxing a stress exerted to the silicon wafer 10 by the
inter-layer insulation films in which the multilayer
interconnection 12 is buried.
Inventors: |
Saiki; Takashi; (Kawasaki,
JP) ; Okoshi; Katsuaki; (Kawasaki, JP) ;
Hayami; Yuka; (Kawasaki, JP) |
Correspondence
Address: |
WESTERMAN, HATTORI, DANIELS & ADRIAN, LLP
1250 CONNECTICUT AVENUE, NW, SUITE 700
WASHINGTON
DC
20036
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
35459690 |
Appl. No.: |
11/987156 |
Filed: |
November 28, 2007 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
10973391 |
Oct 27, 2004 |
7319066 |
|
|
11987156 |
|
|
|
|
Current U.S.
Class: |
257/368 ;
257/E21.575; 257/E23.132; 257/E29.255 |
Current CPC
Class: |
H01L 23/3171 20130101;
H01L 2924/0002 20130101; H01L 21/768 20130101; H01L 2924/00
20130101; H01L 2924/3511 20130101; H01L 2924/0002 20130101 |
Class at
Publication: |
257/368 ;
257/E29.255 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 15, 2004 |
JP |
2004-176755 |
Claims
1. A semiconductor device comprising: a substrate of a
semiconductor; a gate electrode formed on one surface of the
substrate with a gate insulation film formed therebetween; a
source/drain region formed in the substrate on both sides of the
gate electrode; a contact plug electrically connected to the
substrate; a first insulation film formed on said one surface of
the substrate; a multilayer interconnection buried in the first
insulation film; and a second insulation film formed on the other
surface of the substrate and having a stress relaxing a stress
exerted by the first insulation film to the substrate.
2. A semiconductor device according to claim 1, wherein the second
insulation film has a stress equal to a stress of the first
insulation film.
3. A semiconductor device according to claim 1, wherein the second
insulation film has a tensile stress.
4. A semiconductor device according to claim 1, wherein the second
insulation film is a silicon nitride film.
5. A semiconductor device according to claim 1, wherein the
multilayer interconnection includes 10 or more interconnection
layers.
6. A semiconductor device according to claim 1, wherein the
substrate is a wafer of an above 200 mm-diameter including 200
mm.
7. A semiconductor device according to claim 1, wherein the first
insulation film includes a silicon nitride film or a low dielectric
constant insulation film.
8. A semiconductor device according to claim 1, wherein the first
insulation film includes a stopper film which has a tensile stress
and functions as a stopper for etching or polishing.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This is a divisional of U.S. application Ser. No.
10/973,391, filed on Oct. 27, 2004, which is based upon and claims
priority of Japanese Patent Application No. 2004-176755, filed on
Jun. 15, 2004, the contents being incorporated herein by
reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a semiconductor device and
a method for fabricating the same, more specifically a
semiconductor device and a method for fabricating the same, the
device having an insulation film formed on a surface of a
semiconductor substrate, which is an inter-layer insulation film or
others having tensile stress.
[0003] The method for fabricating a conventional semiconductor
device having the multilayer interconnection structure formed on a
semiconductor substrate will be explained with reference to FIGS.
14A-14C, 15A-15C and 16A-16B. FIGS. 14A-14C, 15A-15C and 16A-16B
are sectional views of the semiconductor device having the
multilayer interconnection structure in the steps of the method for
fabricating the conventional semiconductor device having the
multilayer interconnection structure.
[0004] First, a silicon oxide films 214a, 214b are formed
respectively on the upper surface and the back surface of a silicon
wafer 210 by, e.g., thermal oxidation.
[0005] Then, a silicon nitride films 216a, 216b are formed by,
e.g., thermal CVD using a vertical furnace respectively on the
silicon oxide films 214a, 214b formed respectively on the upper
surface and the back surface of the silicon wafer 210 (FIG.
14A).
[0006] Then, a photoresist film 220 exposing regions for a device
isolation film to be formed in and covering the rest region is
formed on the silicon nitride film 216a on the upper surface of the
silicon wafer 210 by photolithography (FIG. 14B).
[0007] Then, with the photoresist film 220 as a mask, the silicon
nitride film 216a is etched. Thus, openings 222 are formed in the
silicon nitride film 216a (FIG. 14C).
[0008] Next, with the photoresist film 220 and the silicon nitride
film 216a as a mask, the silicon oxide film 214a and the silicon
wafer 210 are respectively etched from the side of the upper
surface of the silicon wafer 210. Thus, openings 224 are formed in
the silicon oxide film 214a, and grooves 226 are formed in the
surface of the silicon wafer 210.
[0009] After the grooves 226 are formed in the surface of the
silicon wafer 210, the photoresist film 220 is removed by, e.g.,
ashing (FIG. 15A).
[0010] Next, a silicon oxide film 228 is formed on the entire upper
surface of the silicon wafer 210 by, e.g., CVD (FIG. 15B).
[0011] Next, the silicon oxide film 228 is polished by, e.g., CMP
until the upper surface of the silicon nitride film 216a is exposed
to remove the silicon oxide film 228 on the silicon nitride film
216a. The silicon oxide film 228 is buried in the grooves 226
formed in the silicon wafer 210, the openings 224 formed in the
silicon oxide film 214a and the openings 222 formed in the silicon
nitride film 216a. Thus, the device isolation film of the silicon
oxide film 228 is formed (FIG. 15C).
[0012] Then, the silicon nitride film 216a on the upper surface of
the silicon wafer 210 is removed by wet etching. At this time, the
silicon nitride film 216b on the back surface of the silicon wafer
210 is also etched off (FIG. 16A).
[0013] Next, the silicon oxide film 214a exposed on the upper
surface of the silicon wafer 210 is removed by wet etching. At this
time, the silicon oxide film 214b on the back surface of the
silicon wafer 210 is also etched off (FIG. 16B).
[0014] On the upper surface of the silicon wafer 210 having the
device region thus defined by the device isolation film 228,
semiconductor devices, such as MOS transistors, etc., are
formed.
[0015] On the upper surface of the silicon wafer 210 with
semiconductor devices formed on, interconnection layers buried in
inter-layer insulation films by single damascening, dual
damascening or others are suitably repeatedly formed to thereby
form a multilayer interconnection including a plurality of
interconnection layers.
[0016] In forming a multilayer interconnection on the upper surface
of a semiconductor substrate as of the above-described silicon
wafer or others, when the inter-layer insulation films for the
interconnection layers to be buried in are formed, the tensile
stress of the inter-layer insulation films often causes the
semiconductor substrate to warp convexly toward the back surface of
the semiconductor substrate.
[0017] Recently, as semiconductor devices are required to be highly
integrated, the layer number of interconnection layers forming
multilayer interconnections formed on semiconductor substrates is
increased. As semiconductor devices are required to be speedy,
inter-layer insulation films with interconnection layers, etc.
buried in are formed of low dielectric constant (low-k) insulation
films.
[0018] Semiconductor substrates having such increased number of
such low-k inter-layer insulation films formed on the surface are
often caused to largely warp convexly toward the back surfaces due
to the tensile stress of the inter-layer insulation films.
Furthermore, diameters of semiconductor substrates used in
fabricating semiconductor devices are increasing, which makes the
warpage of semiconductor substrates tend to increase.
[0019] Here, as means for improving characteristics of the NMOS
field effect transistors is known the means in which a silicon
nitride film of, e.g., a 30-100 nm-thickness is formed between a
semiconductor substrate and an upper layer of an interconnection
layer or others formed on the upper surface thereof to thereby
introduce strains due to a tensile stress of, e.g., 1-2 GPa of the
silicon nitride film into the channel regions. However, the tensile
stress of the insulation film formed between the semiconductor
substrate and the upper layer, such as the interconnection layer or
others formed on the upper surface thereof is a cause for the
semiconductor substrate warping convexly toward the back surface
thereof.
[0020] The warpage of the semiconductor substrate is a cause for
the defective suction in the transfer system, in which
semiconductor substrates are sucked by chucks, etc. to be
transferred. Accordingly, such warpage of semiconductor substrate
is required to be suppressed.
[0021] The background arts of the present invention are disclosed
in e.g., Japanese published unexamined patent application No. Hei
09-64169 (1997) and Japanese published unexamined patent
application No. Hei 10-32233 (1998).
SUMMARY OF THE INVENTION
[0022] An object of the present invention is to provide a
semiconductor device with an insulation film, such as an
inter-layer insulation film, etc. having a tensile stress formed on
an upper surface of a semiconductor substrate, which can suppress
the warpage, and a method for fabricating the semiconductor
device.
[0023] According to one aspect of the present invention, there is
provided a semiconductor device comprising: a substrate of a
semiconductor; a gate electrode formed on the substrate with a gate
insulation film formed therebetween; a source/drain region formed
in the substrate on both sides of the gate electrode; a contact
plug electrically connected to the substrate; a first insulation
film formed on one surface of the substrate; a multilayer
interconnection buried in the first insulation film; and a second
insulation film formed on the other surface of the substrate and
having a stress relaxing a stress exerted by the first insulation
film to the substrate.
[0024] According to another aspect of the present invention, there
is provided a method for fabricating a semiconductor device
comprising the steps of: forming a gate electrode on one surface of
a semiconductor substrate with a gate insulation film formed
therebetween; forming a source/drain region in the semiconductor
substrate on both sides of the gate electrode; forming a contact
plug electrically connected to the substrate; forming a first
insulation film on said one surface of the semiconductor substrate;
and forming a multilayer interconnection buried in the first
insulation film; the method further comprising before the step of
forming the first insulation film, the step of forming a second
insulation film on the other surface of the substrate, having a
stress relaxing a stress exerted by the first insulation film to
the substrate.
[0025] According to the present invention, the semiconductor device
comprising a multilayer interconnection buried in insulation films
formed on one surface of a semiconductor substrate has an
insulation film formed on the other surface of the substrate and
having a stress for relaxing a stress exerted by the insulation
films formed on one surface of the substrate to the substrate,
whereby the warpage of the substrate can be depressed. Thus, the
generation of defective suction in the transfer system for
semiconductor substrates can be prevented.
[0026] Furthermore, according to the present invention, the
insulation film which is formed on the other surface of the
substrate and has a stress for relaxing a stress exerted to the
substrate by insulation films to be formed on one surface of the
substrate is formed concurrently with forming an insulation film as
a mask for etching and a stopper for polishing in forming a device
isolation film, whereby the warpage of the substrate can be
depressed without adding to the step number of the method for
fabricating the semiconductor device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0027] FIG. 1 is a diagrammatic sectional view of the semiconductor
device according to a first embodiment of the present invention,
which illustrates a structure thereof (Part 1).
[0028] FIG. 2 is a diagrammatic sectional view of the semiconductor
device according to the first embodiment of the present invention,
which illustrates the structure thereof (Part 2).
[0029] FIGS. 3A-3C are views explaining a warped state of the
semiconductor device according to the first embodiment of the
present invention.
[0030] FIG. 4 is a graph of relationships between warpage amounts
of a silicon wafer with a multilayer interconnection formed on the
upper surface, and the film thickness of a silicon nitride film
formed on the back surface of the silicon wafer.
[0031] FIGS. 5A-5C are sectional views of the semiconductor device
according to the first embodiment of the present invention in the
steps of the method for fabricating the same, which illustrate the
method (Part 1).
[0032] FIGS. 6A-6C are sectional views of the semiconductor device
according to the first embodiment of the present invention in the
steps of the method for fabricating the same, which illustrate the
method (Part 2).
[0033] FIGS. 7A-7C are sectional views of the semiconductor device
according to the first embodiment of the present invention in the
steps of the method for fabricating the same, which illustrate the
method (Part 3).
[0034] FIGS. 8A-8C are sectional views of the semiconductor device
according to the first embodiment of the present invention in the
steps of the method for fabricating the same, which illustrate the
method (Part 4).
[0035] FIGS. 9A-9C are sectional views of the semiconductor device
according to the first embodiment of the present invention in the
steps of the method for fabricating the same, which illustrate the
method (Part 5).
[0036] FIGS. 10A-10C are sectional views of the semiconductor
device according to a second embodiment of the present invention in
the steps of the method for fabricating the same, which illustrate
the method (Part 1).
[0037] FIGS. 11A-11C are sectional views of the semiconductor
device according to the second embodiment of the present invention
in the steps of the method for fabricating the same, which
illustrate the method (Part 2).
[0038] FIGS. 12A-12C are sectional views of the semiconductor
device according to the second embodiment of the present invention
in the steps of the method for fabricating the same, which
illustrate the method (Part 3).
[0039] FIGS. 13A-13C are sectional views of the semiconductor
device according to the second embodiment of the present invention
in the steps of the method for fabricating the same, which
illustrate the method (Part 5).
[0040] FIGS. 14A-14C are sectional views of the conventional
semiconductor device having the multilayer structure in the steps
of the method for fabricating the same, which illustrate the method
(Part 1).
[0041] FIGS. 15A-15C are sectional views of the conventional
semiconductor device having the multilayer structure in the steps
of the method for fabricating the same, which illustrate the method
(Part 2).
[0042] FIGS. 16A and 16B are sectional views of the conventional
semiconductor device having the multilayer structure in the steps
of the method for fabricating the same, which illustrate the method
(Part 3).
DETAILED DESCRIPTION OF THE INVENTION
A First Embodiment
[0043] The semiconductor device and the method for fabricating the
same according to a first embodiment of the present invention will
be explained with reference to FIGS. 1, 2, 3A-3C, 4, 5A-5C, 6A-6C,
7A-7C, 8A-8C and 9A-9C. FIGS. 1 and 2 are diagrammatic sectional
views of the semiconductor device according to the present
embodiment. FIGS. 3A-3C are views explaining the warpage of the
semiconductor device according to the present embodiment. FIG. 4 is
a graph of relationships between warpage amounts of a silicon wafer
with a multilayer interconnection formed on the upper surface, and
the film thickness of a silicon nitride film formed on the back
surface of the silicon wafer. FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8C and
9A-9C are sectional view of the semiconductor device according to
the present embodiment in the steps of the method for fabricating
the same, which illustrate the method.
[0044] First, the structure of the semiconductor device according
to the present embodiment will be explained with reference to FIGS.
1 and 2. FIG. 1 is a diagrammatic sectional view of the
semiconductor device according to the present embodiment, which
illustrates a general structure thereof. FIG. 2 is a diagrammatic
sectional view of the semiconductor device according to the present
embodiment, which illustrates the structure near the silicon
wafer.
[0045] As illustrated in FIG. 1, the semiconductor device according
to the present embodiment includes a silicon wafer 10 having an
NMOS transistor and a PMOS transistor formed on the upper surface,
and a multilayer interconnection 12 formed on the upper surface of
the silicon wafer 10.
[0046] As illustrated in FIG. 2, a silicon nitride film 16b is
formed on the back surface of the silicon wafer 10 with a silicon
oxide film 14b formed therebetween. The silicon nitride film 16b is
an insulation film having a tensile stress.
[0047] A device isolation film 18 for defining device regions is
formed on the upper surface of the silicon wafer 10. On the upper
surface of the silicon wafer 10, the device isolation film 18
defines an NMOS transistor region 20n with the NMOS transistor
formed in and a PMOS transistor region 20p with the PMOS transistor
formed in.
[0048] A p type well 22 is formed in the silicon wafer 10 in the
NMOS transistor region 20n. an n type well 24 is formed in the
silicon wafer 10 in the PMOS transistor region 20p.
[0049] On the upper surface of the silicon wafer 10 in the NMOS
transistor region 20n, a gate electrode 28n is formed with a gate
insulation film 26 formed therebetween. A sidewall insulation film
30 is formed on the side wall of the gate electrode 28n. In the
silicon wafer 10 on both sides of the gate electrode 28n, n type
source/drain diffused layers 32n are formed. The source/drain
diffused layers 32n includes a shallow lightly doped impurity
diffused region 34n having the end nearer to the gate electrode 28n
extended up to below the sidewall insulation film 30, and a deep
heavily doped impurity diffused region 36n having the end nearer to
the gate electrode 28n extended up to the end of the sidewall
insulation film 30. P type pocket regions 38p are formed on the
side of the source/drain diffused layers 32n nearer to the channel
region. Metal silicide films 40 are formed respectively on the gate
electrode 28n and the source/drain diffused layers 32n. Thus, the
NMOS transistor including the gate electrode 28n and the
source/drain diffused layers 32n is formed.
[0050] On the upper surface of the silicon wafer 10 in the PMOS
transistor region 20p, a gate electrode 28p is formed with the gate
insulation film 26 formed therebetween. The sidewall insulation
film 30 is formed on the side wall of the gate electrode 28p. In
the silicon wafer 10 on both sides of the gate electrode 28p, p
type source/drain diffused layers 32p are formed. The source/drain
diffused layers 32p includes a lightly doped impurity diffused
region 34p having the end nearer to the gate electrode 28p extended
up to below the sidewall insulation film 30 and a heavily doped
impurity diffused region 36p having the side nearer to the gate
electrode 28p extended up to the end of the sidewall insulation
film 30. N type pockets regions 38n are formed the side of the
source/drain diffused layers 32p nearer to the channel region.
Metal silicide films 40 are formed respectively on the gate
electrode 28p and the source/drain diffused layer 32p. Thus, the
PMOS transistor including the gate electrode 28p and the
source/drain diffused layer 32p is formed.
[0051] On the silicon wafer 10 with the NMOS transistor and PMOS
transistor formed on, inter-layer insulation film 46 of a silicon
nitride film 42 and a silicon oxide film 44 formed the latter on
the former is formed. Contact plugs 48 electrically connected to
the source/drain diffused layers 32n, 32p are buried in the
inter-layer insulation film 46.
[0052] On the inter-layer insulation film 46 with contact plugs 48
buried in, as illustrated in FIG. 1, a multilayer interconnection
12 including 11 interconnection layers is formed. The multilayer
interconnection 12 is constituted with a first metal
interconnection part 12a including 8 interconnection layers, a
second metal interconnection part 12b including 2 interconnection
layers, and a third metal interconnection part 12c including 1
interconnection layer.
[0053] In the first metal interconnection part 12a, an inter-layer
insulation film 50 of a low-k insulation film is formed on the
inter-layer insulation film 46 with the contact plugs 48 buried in.
An interconnection layer 52 is buried in the inter-layer insulation
film 50. On the inter-layer insulation film 50, inter-layer
insulation films 54, 58, 62, 66, 70, 74, 78 each formed of a
stopper film of, e.g., SiC film and a low-k insulation film of,
e.g., SiOC film formed the latter on the former are formed
sequentially the latter on the former. Interconnection layers 56,
60, 64, 68, 72, 76, 80 are buried respectively in the inter-layer
insulation films 54, 58, 62, 66, 70, 74, 78.
[0054] In the second metal interconnection part 12b, an inter-layer
insulation film 82 formed of an SiC film and a silicon oxide film
formed the latter on the former is formed on the inter-layer
insulation film 78 with the interconnection layer 80 buried in. An
interconnection layer 84 is buried in the inter-layer insulation
film 82. On the inter-layer insulation film 82, an inter-layer
insulation film 86 of the same layer structure as the inter-layer
insulation film 82 is formed. An interconnection layer 88 is buried
in the inter-layer insulation film 86.
[0055] In the third metal interconnection part 12c, an inter-layer
insulation film 90 formed of an SiC film and a silicon oxide film
formed the latter on the former is formed on the inter-layer
insulation film 86 with the interconnection layer 88 buried in. A
contact plug 92 is buried in the inter-layer insulation film 90. On
the inter-layer insulation film 90, an interconnection layer 94 is
formed, electrically connected to the contact plug 92. On the
inter-layer insulation film 90 with the interconnection layer 90
formed on, a cover film 92 formed of a silicon oxide film and a
silicon nitride film formed the latter on the former is formed.
[0056] Thus, the semiconductor device according to the present
embodiment is constituted.
[0057] The semiconductor device according to the present embodiment
is characterized mainly in that the silicon nitride film 16b which
is an insulation film having a tensile stress is formed on the back
surface of the silicon wafer 10 with the insulation films, such as
the inter-layer insulation films of silicon nitride film, etc.,
having tensile stresses formed on the upper surface.
[0058] The silicon wafer 10 without anything formed on the upper
surface and the back surface thereof has substantially no warpage
as illustrated in FIG. 3A.
[0059] The silicon wafer 10 having the multilayer interconnection
12 formed on the upper surface and having the back surface exposed
is warped convexly toward the back surface as illustrated in FIG.
3B due to the tensile stresses of the inter-layer insulation films
with the interconnection layer buried in, the cover film, etc. The
insulation films which cause such warpage of the silicon wafer 10
are, silicon nitride film of, e.g., a 1-2 GPa tensile stress and
inter-layer insulation films of low-k insulation film with
interconnection layers of copper, etc. buried in. When the stopper
film, which functions as the stopper for etching or polishing and
the cover film or others formed on the multilayer interconnection
are formed of silicon nitride film or others having tensile
stresses, such insulation films also causes the warpage of the
silicon wafer 10. The tensile stress of the low-k insulation film
itself is not high. However, when an interconnection layer of
copper or others is buried in a low-k insulation film, the low-k
insulation film has the tensile stress due to the compression
stress of the interconnection layer, which is a cause for the
warpage of the silicon wafer 10. When the silicon wafer 10 has a
large warpage amount, defective suction takes place in the transfer
system, in which the silicon wafer 10 is sucked with chuck, etc. to
be transferred.
[0060] The semiconductor device according to the present embodiment
has the silicon nitride film 16b, which is an insulation film
having a tensile stress, formed on the back surface of the silicon
wafer 10. When the multilayer interconnection 12 is formed on the
upper surface of the silicon wafer 10, and the insulation films
having tensile stresses, such as silicon nitride film, low-k
insulation films with the interconnection layers of copper or
others buried in, etc., the silicon nitride film 16b relaxes the
stress to be exerted to the silicon wafer 10. Thus, the
semiconductor device according to the present embodiment can
depress the warpage of the silicon wafer 10 as illustrated in FIG.
3C in comparison with the warpage of the silicon wafer 10 with the
back surface exposed as illustrated in FIG. 3B. Thus, the warpage
of the silicon wafer 10 is depressed, whereby the defective suction
can be prevented in the transfer system, in which the silicon wafer
10 is sucked with chucks, etc. to be transferred.
[0061] The silicon nitride film 16b is formed concurrently with
forming a silicon nitride film 16a which is used as the mask for
etching and the stopper for polishing in forming the device
isolation film 18 defining the device regions. Thus, the formation
of the silicon nitride film 16b does not add to the number of the
steps of the method for fabricating the semiconductor device.
[0062] The film thickness of the silicon nitride film 16b to be
formed on the back surface of the silicon wafer 10 is set in
accordance with the tensile stress of the inter-layer insulation
films to be formed on the upper surface of the silicon wafer 10.
That is, the film thickness of the silicon nitride film 16b is set
so that the tensile stress of the inter-layer insulation films of
the multilayer interconnection 12, and the tensile stress of the
silicon nitride film 16b are substantially equal to each other.
Specifically, the tensile stress of the silicon nitride film 16b is
set at, e.g., 1-2 GPa.
[0063] FIG. 4 is a graph of the warpage amounts of the silicon
wafer with the multilayer interconnection formed on the upper
surface, which were measured with the film thickness of the silicon
nitride film formed on the back surface changed. The film
thicknesses of the silicon nitride film formed on the back surface
of the silicon wafer are taken on the horizontal axis of the graph,
and on the vertical axis, the warpage amounts of the silicon wafer
are taken. In the transfer system used by the inventors, et al. of
the present application, when the warpage amounts of the silicon
wafer is above 200 .mu.m including 200 .mu.m, transfer errors due
to defective suction took place.
[0064] As evident in the graph, the film thickness of the silicon
nitride film to be formed on the back surface of the silicon wafer
is, e.g., 100 nm or more, the warpage amount of the silicon wafer
can be depressed to a value of below 200 .mu.m excluding 200 .mu.m
which prevents the generation of the transfer error.
[0065] Next, the method for fabricating the semiconductor device
according to the present embodiment will be explained with
reference to FIG. 1 and FIGS. 5A-5C, 6A-6C, 7A-7C, 8A-8C and
9A-9C.
[0066] First, the silicon oxide films 14a, 14b of, e.g., a 5-10
nm-thickness are formed respectively on the upper surface and the
back surface of the silicon wafer 10 by, e.g., thermal oxidation.
The silicon wafer 10 has, e.g., a 20 mm-diameter. The upper surface
of the silicon wafer 10 is the surface where devices are to be
formed, while the back surface of the silicon wafer 10 is the
surface where no device is to be formed.
[0067] Next, on the silicon oxide film 14a, 14b formed on the upper
surface and the back surface of the silicon wafer 10, the silicon
nitride films 16a, 16b of, e.g., a 100-200 nm-thickness are formed
by thermal CVD using, e.g., a vertical furnace (FIG. 5A). As
conditions for forming the silicon nitride films 16a, 16b, the raw
material gas is a mixed gas of, e.g., SiH.sub.2Cl.sub.2 and
NH.sub.3, and the film forming temperature is, e.g.,
700-800.degree. C. By using a vertical furnace in forming the
films, the silicon nitride film 16a which functions as a mask for
etching and a stopper for polishing and the silicon nitride film
16b can be formed respectively on the upper surface of the silicon
wafer 10 and on the back surface of the silicon wafer 10.
[0068] Then, the silicon oxide films 98a, 98b of, e.g., a 100-200
nm-thickness are formed by, e.g., thermal CVD using a vertical
furnace on the silicon nitride film 16a, 16b formed on the upper
surface and the back surface of the silicon wafer 10 (FIG. 5B). As
conditions for forming the silicon oxide films 98a, 98b, the raw
material gas is a mixed gas of, e.g., TEOS (tetraethoxysilane) and
O.sub.2, and the film forming temperature is, e.g., 600-700.degree.
C. As will be described later, the silicon oxide film 98b functions
as a protection film which covers the silicon nitride film 16b so
that the silicon nitride film 16b is not removed by the etching for
removing the silicon nitride film 16a.
[0069] Then, of the silicon oxide films 98a, 98b, the silicon oxide
film 98a formed on the upper surface of the silicon wafer 10 is
selectively removed by wet etching using, e.g., hydrofluoric acid
(FIG. 5C). The silicon oxide film 98a on the upper surface of the
silicon wafer 10 can be selectively removed by wet etching using,
e.g., a single wafer spin cleaner.
[0070] Next, a photoresist film 100 for exposing regions for the
device isolation films 18 to be formed in and covering the rest
region is formed by photolithography on the silicon nitride film
16a on the upper surface of the silicon wafer 10 (FIG. 6A).
[0071] Then, with the photoresist film 100 as a mask, the silicon
nitride film 16a is etched. Thus, openings 102 are formed in the
silicon nitride film 16a (FIG. 6B).
[0072] Then, with the photoresist film 100 and the silicon nitride
film 16a as a mask, the silicon oxide film 14a and the silicon
wafer 10 are respectively etched from the side of the upper surface
of the silicon wafer 10. openings 104 are formed in the silicon
oxide film 14a while trenches 106 of, e.g., a 0.3-0.5 .mu.m-depth
are formed in the upper surface of the silicon wafer 10.
[0073] After the trenches 106 have been formed in the surface of
the silicon wafer 10, the photoresist film 100 is removed by, e.g.,
ashing (FIG. 6C).
[0074] Then, the silicon oxide film 108 is formed in, e.g., a
400-600 nm-thickness on the entire upper surface of the silicon
wafer 10 by, e.g., CVD (FIG. 7A).
[0075] Then, the silicon oxide film 108 is polished by, e.g., CMP
until the surface of the silicon nitride film 16a is exposed to
thereby remove the silicon oxide film 108 on the silicon nitride
film 16a. The silicon nitride film 16a functions as a stopper here
for the polishing. Thus, the silicon oxide film 108 is buried in
the trenches 106 formed in the silicon wafer 10, the openings 104
formed in the silicon oxide film 14a and the openings 102 formed in
the silicon nitride film 16a. Thus, the device isolation films 18
of the silicon oxide film 108 are formed (FIG. 7B).
[0076] After the trenches 106 has been formed in the silicon wafer
10 and before the silicon oxide film 108 is buried in the trenches
106, a silicon oxide film of, e.g., a 1-5 nm-thickness may be
formed on the inside surface of the trenches 106, and then, a
lining silicon nitride film of, e.g., a 5-20 nm-thickness may be
formed on the inside surface of the trenches 106 and the surface of
the silicon nitride film 16a.
[0077] Then, the silicon nitride film 16a on the upper surface of
the silicon wafer 10 is removed by wet etching using, e.g., a
heated phosphoric acid solution. At this time, the silicon nitride
film 16b covered by the silicon oxide film 98b is protected from
the etching. Thus, the silicon nitride film 16b remains on the back
surface of the silicon wafer 10 (FIG. 7C).
[0078] Then, the silicon oxide film 14a exposed on the upper
surface of the silicon wafer 10 and the silicon oxide film 98b on
the back surface of the silicon wafer 10 are respectively removed
by wet etching using, e.g., hydrofluoric acid (FIG. 8A).
[0079] Next, by, e.g., ion implantation, the p type well 22 is
formed in the NMOS transistor region 20n, and the n type well 24 is
formed in the PMOS transistor region 20p (FIG. 8B).
[0080] Next, using the same way as in the usual MOS transistor
fabrication method, on the side of the upper surface of the silicon
wafer 10, the NMOS transistor including the gate electrode 28n and
the source/drain diffused layers 22n is formed in the NMOS
transistor region 20, and the PMOS transistor including the gate
electrode 28p and the source/drain diffused layers 32p is formed in
the PMOS transistor region 24 (FIG. 8C).
[0081] Then, using the salicide process, the metal silicide films
40 are formed respectively on the gate electrodes 28n, 28p and the
source/drain diffused layers 32n, 32p (FIG. 9A).
[0082] Next, on the upper surface of the silicon wafer with the
NMOS transistor and the PMOS transistor formed on, the silicon
nitride film 42 of, e.g., a 30-100 nm-thickness is formed by, e.g.,
CVD. Then, the silicon oxide film 44 of, e.g., a 600-800
nm-thickness is formed on the silicon nitride film 42. Then, the
surface of the silicon oxide film 44 is polished by, e.g., CMP to
flatten the surface of the silicon oxide film 44. Thus, the
inter-layer insulation film 46 formed of the silicon nitride film
42 and the silicon oxide film 44 laid the latter on the former is
formed (FIG. 9B).
[0083] Then, contact holes are formed by photolithography and dry
etching in the inter-layer insulation film 46 down to the metal
silicide films 40 formed on the source/drain diffused layers 32n,
32p. Next, a metal film is formed by, e.g., CVD on the inter-layer
insulation film 46 with the contact holes formed in. Next, the
metal film is polished by, e.g., CMP until the surface of the
silicon oxide film 44 is exposed. Thus, the contact plugs 48 of the
metal film buried in the contact holes are formed (FIG. 9C).
[0084] Hereafter, on the inter-layer insulation film 46 with the
contact plugs 48 buried in, the multilayer interconnection 12
including, e.g., 11 interconnection layers buried in the
inter-layer insulation films illustrated in FIG. 1 is formed by the
usual multilayer interconnection forming method using single
damascening, dual damascening, etc. The silicon nitride film to be
formed on the upper surface of the silicon wafer 10 as the
inter-layer insulation film is formed at, e.g., a 500-600.degree.
C. film forming temperature and in, e.g., a 30-100 nm-thickness.
The silicon nitride film formed as the inter-layer insulation film
has, e.g., a 1-2 GPa tensile stress.
[0085] Thus, the semiconductor device according to the present
embodiment is fabricated.
[0086] As described above, according to the present embodiment, the
silicon nitride film 16b, which is an insulation film having
tensile stress, is formed on the back surface of the silicon wafer
10 on the upper surface of which insulation films having tensile
stresses are formed, whereby the warpage of the silicon wafer 10
can be depressed. The silicon nitride film 16b is formed
concurrently with forming the silicon nitride film 16a which is
used as the mask for etching and the stopper for polishing in
forming the device isolation film 18, whereby the warpage of the
silicon wafer 10 can be depressed without adding to the step number
of the method for fabricating the semiconductor device. The warpage
of the silicon wafer 10 is thus depressed, whereby the generation
of defective suction in the transfer system for semiconductor
substrates can be prevented.
[0087] In the present embodiment, the silicon wafer 10 has a 200 mm
diameter. However, according to the present embodiment, the warpage
of silicon wafers of large diameters of, e.g., 200 nm or more can
be depressed, and the generation of defective suction in the
transfer system for semiconductor substrates can be prevented.
A Second Embodiment
[0088] The semiconductor device and the method for fabricating the
same according to a second embodiment of the present invention will
be explained with reference to FIGS. 10A-10C, 11A-11C, 12A-12C and
13A-13C. FIG. 10A-10C, 11A-11C, 12A-12C and 13A-13C are sectional
views of the semiconductor device according to the present
embodiment in the steps of the method for fabricating the same,
which illustrate the method. The same members of the present
embodiment as those of the semiconductor device and the method for
fabricating the same according to the first embodiment are
represented by the same reference numbers not to repeat or to
simplify their explanation.
[0089] The basic structure of the semiconductor device according to
the present embodiment is the same as that of the semiconductor
device according to the first embodiment. The semiconductor device
according to the present embodiment is different from the
semiconductor device according to the first embodiment in the
fabrication method. The method for fabricating the semiconductor
device according to the present embodiment will be explained with
reference to FIGS. 10A-10C, 11A-11C, 12A-12C and 13A-13C.
[0090] First, silicon oxide films 14a, 14b and silicon nitride
films 16a, 16b are formed on the upper surface and the back surface
of a silicon wafer 10 in the same way as in the method for
fabricating the semiconductor device according to the first
embodiment (FIG. 10A).
[0091] Then, polycrystal silicon film 110a, 110b of, e.g., a
100-200 nm-thickness are formed by thermal CVD using, e.g., a
vertical furnace respectively on the silicon nitride films 16a, 16b
formed on the upper surface and the back surface of the silicon
wafer 10 (FIG. 10B). As conditions for forming the polycrystal
silicon films 110a, 110b, the raw material gas is, e.g., SiH.sub.4,
and the film forming temperature is, e.g., 600-700.degree. C. The
polycrystal silicon film 110b functions as a protection film for
protecting the silicon nitride film 16b so that the silicon nitride
film 16b is not removed by the etching for removing the silicon
nitride film 16a.
[0092] Next, a photoresist film 112 for exposing regions for device
isolation films 18 to be formed in and covering the rest region is
formed by photolithography on the polycrystal silicon film 110a on
the upper surface of the silicon wafer 10 (FIG. 10C).
[0093] Then, with the photoresist film 112 as a mask, the
polycrystal silicon film 110a is etched. Thus, openings 114 are
formed in the polycrystal silicon film 110a (FIG. 11A).
[0094] After the openings 114 have been formed in the polycrystal
silicon film 11a, the photoresist film 112 is removed by, e.g.,
ashing (FIG. 11B).
[0095] Then, with the polycrystal silicon film 110a as a mask, the
silicon nitride film 16a is etched from the side of the upper
surface of the silicon wafer 10 to form openings 102 in the silicon
nitride film 16a (FIG. 1C).
[0096] Then, with the polycrystal silicon film 110a and the silicon
nitride film 16a as a mask, the silicon oxide film 14a and the
silicon wafer 10 are etched from the upper surface of the silicon
wafer 10. Thus, openings 104 are formed in the silicon oxide film
14a while a trenches 106 of, e.g., a 0.3-0.5 .mu.m-depth are formed
in the upper surface of the silicon wafer 10. The polycrystal
silicon film 110a itself used as the mask is etched here and is
removed when the trenches 106 are formed. The silicon nitride film
16a, however, remains (FIG. 12A).
[0097] Next, the silicon oxide film 108 of, e.g., a 400-600
nm-thickness is formed on the entire upper surface of the silicon
wafer 10 by, e.g., CVD (FIG. 12B).
[0098] Then, the silicon oxide film 108 is polished by, e.g., CMP
until the upper surface of the silicon nitride film 16a is exposed
to remove the silicon oxide film 108 on the silicon nitride film
16a. The silicon nitride film 16a functions here as a stopper for
the polishing. Thus, the silicon oxide film 108 is buried in the
trenches 106 formed in the silicon wafer 10, the openings 104
formed in the silicon oxide film 14a and the openings 102 formed in
the silicon nitride film 16a, and the device isolation films 18 of
the silicon oxide film 108 are formed (FIG. 12C).
[0099] After the trenches 106 have been formed in the silicon wafer
10 and before the silicon oxide film 108 is buried in the trenches
106, a silicon oxide film of, e.g., a 1-5 nm-thickness may be
formed on the inside surface of the trenches 106, and then, a
lining silicon nitride film of, e.g., a 5-20 nm-thickness may be
formed on the inside surface of the trenches 106 and the surface of
the silicon nitride film 16a.
[0100] Then, the silicon nitride film 16a on the upper surface of
the silicon wafer 10 is removed by wet etching using, e.g., a
heated phosphoric acid solution (FIG. 13A). At this time, the
silicon nitride film 16b covered by the polycrystal silicon film
110b is protected from the etching. Thus, the silicon nitride film
16b remains on the back surface of the silicon wafer 10.
[0101] Then, the silicon oxide film 14a exposed on the upper
surface of the silicon wafer 10 is removed by wet etching using,
e.g., hydrofluoric acid (FIG. 13B).
[0102] Next, the polycrystal silicon film 110b on the back surface
of the silicon wafer 10 is removed by wet etching using, e.g.,
fluoro-nitric acid (FIG. 13C). The polycrystal silicon film 110b on
the back surface of the silicon wafer 10 can be selectively removed
by using a single wafer spin cleaner.
[0103] The following steps are the same as those of the method for
fabricating a semiconductor device according to the first
embodiment illustrated in FIGS. 8B-8C and 9A-9C, and their
explanation will be omitted.
[0104] As described above, according to the present embodiment, the
silicon nitride film 16b, which is an insulation film having
tensile stress, is formed on the back surface of the silicon wafer
on the upper surface of which insulation films having tensile
stress are to be formed, whereby the warpage of the silicon wafer
10 can be depressed. The silicon nitride film 16b is formed
concurrently with the silicon nitride film 16a used as the mask for
etching and the stopper for polishing for forming the device
isolation films 18, whereby the warpage of the silicon wafer 10 can
be depressed without adding to the step number of the method for
fabricating the semiconductor device. The warpage of the silicon
wafer 10 is thus depressed, whereby the generation of the defective
suction in the transfer system for semiconductor wafers can be
prevented.
Modified Embodiments
[0105] The present invention is not limited to the above-described
embodiments and can cover other various modifications.
[0106] For example, in the above-described embodiments, NMOS
transistors and PMOS transistors are formed, but the semiconductor
devices to be formed on the silicon wafer 10 are not limited to
NMOS transistors and PMOS transistors.
[0107] In the above-described embodiments, the multilayer
interconnection 12 including 11 interconnection layers is formed on
the upper surface of the silicon wafer 10, but the interconnection
layer number of the multilayer interconnection 12 is not
essentially limited to 11 layers. According to the present
invention, the warpage of the silicon wafer 10 can be effectively
depressed even in a case that a multilayer interconnection of a
large interconnection layer number, such as 10 or more
interconnection layers is formed on the upper surface of the
silicon wafer 10.
[0108] In the above-described embodiments, the silicon nitride film
16b is formed on the back surface of the silicon wafer 10. However,
an insulation film having tensile stress may be formed on the back
surface of the silicon wafer 10. As the insulation film having
tensile stress other than silicon nitride film, SOG (Spin On Glass)
film or others, for example, can be formed.
[0109] In the above-described embodiments, as the protection film
for covering the silicon nitride film 16b so that the silicon
nitride film 16b, which is on the back surface of the silicon wafer
10, is not etched off, the silicon oxide film 98b or the
polycrystal silicon film 110b is formed. However, the protection
film for covering the silicon nitride film 16b is not limited to
them. The protection film for covering the silicon nitride film 16b
may be different from silicon nitride film in the etching
characteristics for a prescribed etching solution, such as heated
phosphoric acid solution or others. As the protection films, other
than the silicon oxide film 98b and the polycrystal silicon film
110b, SiON film, SiC film, SiOC film, etc., for example, can be
formed.
[0110] In the above-described embodiments, the silicon nitride film
16b, which is an insulation film having tensile stress, is formed
on the back surface of the silicon wafer 10 on the upper surface of
which insulation films having tensile stresses are to be formed.
The present invention is applicable widely to a case that
insulation films formed on the upper surface of the silicon wafer
10 exert stress to the silicon wafer 10. In such case, an
insulation film having a stress which relaxes a stress exerted to
the silicon wafer 10 by insulation films formed on the upper
surface of the silicon wafer 10 may be formed on the back surface
of the silicon wafer 10.
[0111] In the above-described embodiments, the silicon wafer 10 is
used. However, the present invention is applicable not only to the
silicon wafer 10, but also to various semiconductor wafers. The
present invention is applicable not only to wafers, but also to
semiconductor substrates in various shapes.
* * * * *