U.S. patent application number 12/219080 was filed with the patent office on 2008-11-13 for method and apparatus for controlling cache.
This patent application is currently assigned to FUJITSU LIMITED. Invention is credited to Souta Kusachi, Kuniki Morita, Tomoyuki Okawa, Masaki Ukai.
Application Number | 20080282037 12/219080 |
Document ID | / |
Family ID | 38437079 |
Filed Date | 2008-11-13 |
United States Patent
Application |
20080282037 |
Kind Code |
A1 |
Kusachi; Souta ; et
al. |
November 13, 2008 |
Method and apparatus for controlling cache
Abstract
A cache controller controls at least one cache. The cache
includes ways including a plurality of blocks that stores therein
entry data. A writing unit writes degradation data to a failed
block. The degradation data indicates that the failed block is in a
degradation state. A reading unit reads entry data from a block. A
determining unit determines, if the entry data obtained by the
reading unit includes the degradation data, that the block is in
the degradation state.
Inventors: |
Kusachi; Souta; (Kawasaki,
JP) ; Morita; Kuniki; (Kawasaki, JP) ; Ukai;
Masaki; (Kawasaki, JP) ; Okawa; Tomoyuki;
(Kawasaki, JP) |
Correspondence
Address: |
STAAS & HALSEY LLP
SUITE 700, 1201 NEW YORK AVENUE, N.W.
WASHINGTON
DC
20005
US
|
Assignee: |
FUJITSU LIMITED
Kawasaki
JP
|
Family ID: |
38437079 |
Appl. No.: |
12/219080 |
Filed: |
July 15, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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PCT/JP2006/303589 |
Feb 27, 2006 |
|
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12219080 |
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Current U.S.
Class: |
711/133 ;
711/118 |
Current CPC
Class: |
G06F 12/0846 20130101;
G06F 11/1064 20130101; G06F 12/0864 20130101 |
Class at
Publication: |
711/133 ;
711/118 |
International
Class: |
G06F 12/00 20060101
G06F012/00 |
Claims
1. A cache controller that controls at least one cache, wherein the
cache includes ways including a plurality of blocks that stores
therein entry data, the cache controller comprising: a writing unit
that writes degradation data to a failed block, the degradation
data indicative that the failed block is in a degradation state; a
reading unit that reads entry data from a block; and a determining
unit that determines, if the entry data obtained by the reading
unit includes the degradation data, that the block is in the
degradation state.
2. The cache controller according to claim 1, wherein the
degradation data includes first data and second data, and the
writing unit writes the first data in a first area and the second
data in a second area, wherein data in the first area is an object
for subjecting an error correcting process, and data in the second
area is not an object for subjecting the error correcting
process.
3. The cache controller according to claim 2, wherein the writing
unit writes such a value as the first data that other data that is
expected to be stored in the first area cannot take.
4. The cache controller according to claim 2, wherein the writing
unit writes a 2-bit data as the second data.
5. The cache controller according to claim 2, wherein the
determining unit determines from the entry data obtained by the
reading unit whether data in the first area indicates the first
data thereby obtaining a first result and whether data in the
second area indicates the second data thereby obtaining a second
result, and determines whether the block is in the degradation
state based on the first result and the second result.
6. The cache controller according to claim 2, wherein the
determining unit determines from the entry data obtained by the
reading unit whether data in the first area indicates the first
data thereby obtaining a first result and whether data in the
second area indicates the second data thereby obtaining a second
result, and determines whether any one of processes is required
including a block-degradation process, a way-degradation process,
and a fatal-error process.
7. A cache control method of controlling at least one cache,
wherein the cache includes ways including a plurality of blocks
that stores therein entry data, the cache control method
comprising: writing degradation data to a failed block, the
degradation data indicative that the failed block is in a
degradation state; reading entry data from a block; and
determining, if the entry data obtained at the reading includes the
degradation data, that the block is in the degradation state.
8. The cache control method according to claim 7, wherein the
degradation data includes first data and second data, and the
writing including writing the first data in a first area and the
second data in a second area, wherein data in the first area is an
object for subjecting an error correcting process, and data in the
second area is not an object for subjecting the error correcting
process.
9. The cache control method according to claim 8, wherein the
writing including writing such a value as the first data that other
data that is expected to be stored in the first area cannot
take.
10. The cache control method according to claim 8, wherein the
writing includes writing a 2-bit data as the second data.
11. The cache control method according to claim 8, wherein the
determining including determining from the entry data obtained at
the reading whether data in the first area indicates the first data
thereby obtaining a first result and whether data in the second
area indicates the second data thereby obtaining a second result,
and determining whether the block is in the degradation state based
on the first result and the second result.
12. The cache control method according to claim 8, wherein the
determining including determining from the entry data obtained at
the reading whether data in the first area indicates the first data
thereby obtaining a first result and whether data in the second
area indicates the second data thereby obtaining a second result,
and determining whether any one of processes is required including
a block-degradation process, a way-degradation process, and a
fatal-error process.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates to a technology for
controlling a cache that includes ways including a plurality of
blocks that store therein entry data, and more particularly, to a
technology for controlling block degradation.
[0003] 2. Description of the Related Art
[0004] Cache memories are low-capacity and high-speed memories that
are widely used to solve problems caused by difference in
performance between a processor such as a central processing unit
(CPU) and a storage device such as a memory. The cache memory
includes a plurality of ways arranged in parallel. Each of the ways
includes a plurality of storage units called "block" as many as
indices of the cache memory. A group of blocks in different ways
having the same index (i.e., blocks within the same cache line) is
usually accessed simultaneously.
[0005] Tag random access memories (tag RAMs) are used to store
therein tags indicative of addresses where cache data, which is
stored in the cache memory, is on a main memory actually. Such a
tag RAM provides a list of addresses of the cache data for the CPU.
The data structure of the tags stored in the tag RAM is same as the
above-described data structure using ways and blocks.
[0006] Accesses to a specific block, which are the storage unit in
the cache memory, may frequently fail due to a memory failure. If
such access errors occur, it is necessary to set the specific block
that causes the access errors to an unavailable state, i.e., to
degrade the specific block, to avoid occurrence of a serious
failure.
[0007] In one of degradation methods, if the failure occurs in the
specific block, the whole way including the specific block is
degraded. Although the block that causes the failure can be easily
degraded by the degradation method mentioned earlier, all the
blocks in the same way cannot be used, which results in decreasing
performance of the cache memory. In contrast, Japanese Patent
Application Laid-open No. S60-101656 and Japanese Patent
Application Laid-open No. H2-302856 disclose technologies for
degrading, if a failure has occurred in a specific block, the
specific block only.
[0008] However, if the technologies disclosed in Japanese Patent
Application Laid-open No. S60-101656 and Japanese Patent
Application Laid-open No. H2-302856 are used, degradation data
indicative of a degradation status is stored corresponding to each
one of the failed blocks, which increases an amount of data in the
circuit. To be specific, if there are many ways including many
blocks, i.e., there are many blocks, a large amount of degradation
data is required, as a result of which a larger part of storage
circuit is occupied by the degradation data.
[0009] For this reason, there are needs for producing a cache
controller that degrades not the whole way but the failed block by
using a lower amount of the degradation data. Such problem commonly
arises in a data processor including the cache memory.
SUMMARY OF THE INVENTION
[0010] It is an object of the present invention to at least
partially solve the problems in the conventional technology.
[0011] According to an aspect of the present invention, there is
provided a cache controller that controls at least one cache,
wherein the cache includes ways including a plurality of blocks
that stores therein entry data. The cache controller includes a
writing unit that writes degradation data to a failed block, the
degradation data indicative that the failed block is in a
degradation state; a reading unit that reads entry data from a
block; and a determining unit that determines, if the entry data
obtained by the reading unit includes the degradation data, that
the block is in the degradation state.
[0012] According to another aspect of the present invention, there
is provided a cache control method of controlling at least one
cache, wherein the cache includes ways including a plurality of
blocks that stores therein entry data. The cache control method
includes writing degradation data to a failed block, the
degradation data indicative that the failed block is in a
degradation state; reading entry data from a block; and
determining, if the entry data obtained at the reading includes the
degradation data, that the block is in the degradation state.
[0013] The above and other objects, features, advantages and
technical and industrial significance of this invention will be
better understood by reading the following detailed description of
presently preferred embodiments of the invention, when considered
in connection with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] FIG. 1 is a schematic diagram for explaining an overview of
a cache control method according to an embodiment of the present
invention;
[0015] FIG. 2 is a schematic diagram of a tag-RAM control unit
according to the present embodiment;
[0016] FIG. 3 is a block diagram of the tag-RAM control unit shown
in FIG. 2;
[0017] FIG. 4A is an example of the structure of entry data stored
in a tag RAM shown in FIG. 3;
[0018] FIG. 4B is an example of the entry data in the degradation
state;
[0019] FIG. 5 is a table illustrating exemplary results of
determination about the degradation state; and
[0020] FIG. 6 is a flowchart of a block-degradation process.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0021] Exemplary embodiments of the present invention are described
in detail below with reference to the accompanying drawings. In a
present embodiment of the present invention, a tag-RAM control unit
of a system controller (SC) uses a predetermined method to control
a plurality of tag RAMs in CPUs. The SC and the CPUs are connected
to each other.
[0022] FIG. 1 is a schematic diagram for explaining an overview of
a cache control method according to the present embodiment. More
particularly, FIG. 1 is a schematic diagram of data structure of a
tag RAM. The tag RAM shown in FIG. 1 is for a single CPU. If, for
example, there are four CPUs, four sets (for four CPUs) of the tag
RAM shown in FIG. 1 are used.
[0023] The tag RAM includes total 12 ways from a way 0 to a way 11.
Each way includes 2048 blocks. The block is a unit of entry data.
The CPU collectively accesses a group of blocks in different ways
having the same index, i.e., blocks within the same cache line. For
example, if the target index is 3, the CPU simultaneously accesses
twelve blocks having the index 3 in each of the ways 0 to 11.
[0024] Thus, in the tag RAM that includes a plurality of blocks,
due to a failure in a predetermined position inside the tag RAM, an
access error frequently occurs at the time of accessing a specific
block. If the specific block that causes the access error remains
as it is, a serious failure is likely to occur. To avoid occurrence
of such a serious failure, it is necessary to degrade the specific
block.
[0025] If the whole way including the failed block is degraded,
degradation data indicating that the block is in a degradation
state is stored corresponding to each of the ways. In other words,
in the example of FIG. 1, the degradation data is stored
corresponding to up to twelve ways. Thus, an amount of data in the
circuit such as registers necessary for storing the degradation
data is suppressed. However, because the whole way is degraded, not
only the failed block but also the normal blocks are not
accessible, which decreases the performance of the tag RAM.
[0026] On the other hand, if only the failed block is degraded,
decrease in the performance can be minimized. However, the
degradation data is stored corresponding to each of the failed
blocks. In other words, in the example of FIG. 1, the degradation
data is stored corresponding to up to 12.times.2048=24576 blocks.
Therefore, there are needs to suppress a total size of the
degradation data.
[0027] In the cache control method according to the present
embodiment, if the failed block that is to be degraded is detected
(see (1) of FIG. 1), the degradation data is stored in the failed
block as entry data. The degradation data, which indicates that the
block is in the degradation state, is written to both a protected
area and a non-protected area (see (2) of FIG. 2). Data stored in
the protected area is an object for subjecting an error correcting
process using an error correcting code (ECC). Data in the protected
area includes, for example, a physical address indicative of an
address of the data. Data stored in the non-protected area is not
an object for subjecting the error correcting process using the
ECC.
[0028] If the degradation data is written only to the non-protected
area, 5-bit degradation data is required to completely correct any
read errors including a 2-bit error. However, in the cache control
method according to the present embodiment, the degradation data is
written to the protected area in addition to the non-protected
area. Therefore, a result of determination using the ECC can be
used to determine whether the block is in the degradation state.
Due to this, a bit rate of the degradation data stored in the
non-protected area is suppressed to 2-bit.
[0029] If a block is normal, data, for example, the physical
address indicative of an address of data and status data indicative
of a status of the block when the CPU refers to the block is stored
in the protected area. However, if a failure occurs in the block,
it is unnecessary to store data such as the physical address or the
status data in the protected area. In other words, writing
predetermined bits indicating the degradation data to the protected
area causes no problems.
[0030] A relation between a tag-RAM control unit 10 according to
the present embodiment and relevant devices is explained below with
reference to FIG. 2. Although the tag-RAM control unit is in the SC
in the present embodiment, the tag-RAM control unit can be
configured as an independent cache controller. The cache control
method according to the present embodiment can be used to control
various cache memories without limited to the tag RAM.
[0031] The SC including the tag-RAM control unit 10 is connected to
four CPUs 0 to 3. Each of the CPUs 0 to 3 includes a cache memory
and a tag RAM that is used as the index of data stored in the cache
memory. The tag-RAM control unit 10 stores therein a copy of tag
RAM of each of the four CPUs.
[0032] For example, if the CPU 0 cannot find desired data in its
cache memory, the CPU 0 determines whether the other CPUs (CPUs 1
to 3) include desired data by referring to the tag-RAM control unit
10. Upon determining that the other CPUs include the desired data,
the CPU 0 retrieves the desired data from the CPU that includes the
desired data. If the CPU 0 cannot find the desired data even after
referring to the tag RAM in the tag-RAM control unit 10, the CPU 0
requests a memory access controller (MAC), to which the CPU 0 is
connected via the SC, to send the desired data.
[0033] The structure of the tag-RAM control unit 10 is explained
with reference to FIG. 3. FIG. 3 is a block diagram of the tag-RAM
control unit 10. The tag-RAM control unit 10 includes a control
unit 11 and a storage unit 12. The control unit 11 includes a
writing unit 11a, a reading unit 11b, and a degradation-status
determining unit 11c. The storage unit 12 includes a tag RAM 12a
corresponding to each CPU.
[0034] If a failed block is detected, the control unit 11 writes
predetermined degradation data to the failed block of the tag RAM
12a. The control unit 11 reads data from a block of the tag RAM
12a, and determines whether the block is in the degradation state
based on the obtained data.
[0035] The writing unit 11a writes entry data received from the CPU
to a block of the tag RAM 12a. If a failed block is detected, the
writing unit 11a writes the degradation data to the failed block of
the tag RAM 12a. The degradation data written by the writing unit
11a is explained with reference to FIGS. 4A and 4B. FIG. 4A is an
example of the structure of entry data stored in the tag RAM 12a;
and FIG. 4B is an example of the entry data in the degradation
state.
[0036] As shown in FIG. 4A, the entry data in the tag RAM 12a
includes a flag in the non-protected area, a physical address (PA)
and a status (STS) in the protected area, and an ECC. The flag is
2-bit data. The flag of 11 indicates that the block is in the
degradation state; the flag of 00 indicates that the block is not
in the degradation state; and the flag of 01 or 10 indicates that
the block is not in use. The physical address, which is 22-bit
data, indicates an address of data.
[0037] The status, which is 8-bit data, indicates a status of data
indicated by the tag in the CPU. The status of data includes four
types: corresponding data is stored in one CPU, corresponding data
is stored in a plurality of CPUs, corresponding data is stored in a
plurality of CPUs and the data stored in the CPUs is new, and the
corresponding data is not stored in any CPU. The ECC, which is
7-bit data, is used for protecting the physical address and the
status.
[0038] If a failed block is detected, data shown in FIG. 4B is
written to the failed block in the tag RAM 12a as the entry data.
To be specific, "11" indicating that the block is in the
degradation state, bits all set to 1 indicating that actual
physical address does not exist, bits all set to 0 indicating that
CPU does not stores therein valid data, and information indicative
of no error are written as the flag, the physical address, the
status, and the ECC, respectively.
[0039] In this manner, the degradation data, which indicates that
the block is in the degradation state, is written to the failed
block. However, data obtained by reading may differ from the
originally written data due to a data error. Taking such data error
into consideration, the degradation-status determining unit 11c
determines whether the block is in the degradation state, thereby
obtaining a correct result of determination.
[0040] The reading unit 11b is explained by referring back to FIG.
3. The reading unit 11b reads data from the tag RAM 12a, and sends
the obtained data to the CPU. If the reading unit 11b reads data
from the failed block, the reading unit 11b sends the obtained data
to the degradation-status determining unit 11c.
[0041] The degradation-status determining unit 11c determines
whether the block is in the degradation state based on the data
that is received from the reading unit 11b, and sends a result of
determination to an external device. A determination process
performed by the degradation-status determining unit 11c is
explained in detail with reference to FIG. 5. FIG. 5 is a table for
illustrating exemplary results of determination about the
degradation state. CE shown in FIG. 5 indicates a correctable
error; and UE indicates an uncorrectable error.
[0042] The degradation-status determining unit 11c determines
whether the block is in the degradation state based on the flag
stored in the non-protected area, the physical address and the
status stored in the protected area, and a result of the ECC
determination. The degradation-status determining unit 11c selects,
if a given result of the determination about the degradation state
is obtained, a required error process.
[0043] In a row 51 shown in FIG. 5, the flag is 00. As explained
above, the flag of 00 indicates that the block is not in the
degradation state, and the flag of 11 indicates that the block is
in the degradation state. Because possibility that the original
data written by the writing unit 11a had been 11, i.e., possibility
that both bits are inverted due to data error is remarkably low, if
the flag is 00, the degradation-status determining unit 11c
determines that the block is not in the degradation state without
checking the other fields.
[0044] In rows 52 to 55 shown in FIG. 5, the flag is 11. Upon
receiving data shown in any one of rows 52 to 55, the
degradation-status determining unit 11c determines whether the
block is in the degradation state based on the physical address,
the status, and the result of ECC determination in addition to the
flag. If inadmissible data errors are included in the received
data, for example, information indicated by one of the fields is
inconsistent to information indicated by another field (see, the
rows 54 and 55), the degradation-status determining unit 11c
determining errors such as way degradation or a fatal error, and
sends a result of determination about the degradation status to a
relevant external device.
[0045] In rows 56 to 59 shown in FIG. 5, the flag is 01 or 10. Upon
receiving data shown in any one of rows 56 to 59, the
degradation-status determining unit 11c determines whether the
block is in the degradation state based on the physical address,
the status, and the result of ECC determination in addition to the
flag. If inadmissible data errors are included in the received
data, for example, information indicated by one of the fields is
inconsistent to information indicated by another field (see, the
rows 57, 58, and 59), the degradation-status determining unit 11c
determining errors such as way degradation or a fatal error, and
sends a result of determination about the degradation status to a
relevant external device.
[0046] The storage unit 12 is explained by referring back to FIG.
3. The storage unit 12 includes the tag RAM 12a. The tag RAM 12a as
a static RAM (SRAM) includes the ways and the blocks shown in FIG.
1. The tag RAM 12a includes tags as many as CPUs that refer to the
tag-RAM control unit 10. The tags store therein a copy of the tag
RAMs of the CPUs.
[0047] FIG. 6 is a flowchart of a block-degradation process using
the degradation data. Upon detecting a block error (Step S101), the
SC issues a block-degradation request to the CPU (Step S102). Upon
receiving the block-degradation request, the CPU determines whether
if the target block is degraded, all blocks in different ways
having the index same as the target block are degraded (Step
S103).
[0048] If determining that all blocks in different ways having the
index same as the target block are not to be degraded (No at Step
S103), the CPU writes all data in the way including the target
block back to the main memory (Step S104), and sets the flag of the
target block to ON (see FIG. 4B, Step S105). After that, the CPU
sends a degradation notification to the SC (Step S106). Upon
receiving the degradation notification, the SC executes block
degradation (Step S107), and the control process goes to end. On
the other hand, if determining that all blocks in different ways
having the index same as the target block are to be degraded (Yes
at Step S103), the control process goes to end skipping Steps S104
to S106.
[0049] In the present embodiment, upon detecting the block failure,
the writing unit writes degradation data indicating that the block
is in the degradation state to both the protected area and the
non-protected area as the entry data in the tag RAM. When the
reading unit reads data from the block of the tag RAM, the
degradation-status determining unit determines from the obtained
data whether the block is in the degradation state taking
possibility of occurrence of a read error into consideration. The
degradation-status determining unit, if necessary, determines
errors such as way degradation or the fatal error. In other words,
a bit rate of the degradation data stored in the non-protected area
is minimized by writing the degradation data to the protected area
thereby using an error correcting function using the ECC. Thus, it
is possible to degrade the failed block only with the lower amount
of degradation data.
[0050] According to an embodiment of the present invention, it is
possible to degrade the failed block only with a lower amount of
degradation data.
[0051] Moreover, a size of the degradation data stored in a
non-protected area is minimized.
[0052] Furthermore, it is unnecessary to reserve an area dedicated
to the degradation data in a protected area.
[0053] Although the invention has been described with respect to
specific embodiments for a complete and clear disclosure, the
appended claims are not to be thus limited but are to be construed
as embodying all modifications and alternative constructions that
may occur to one skilled in the art that fairly fall within the
basic teaching herein set forth.
* * * * *