U.S. patent application number 12/137600 was filed with the patent office on 2008-11-06 for method for stabilizing asynchronous interfaces.
This patent application is currently assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION. Invention is credited to Anthony P. Cullen, Michael Fee, Patrick J. Meaney.
Application Number | 20080276024 12/137600 |
Document ID | / |
Family ID | 39190016 |
Filed Date | 2008-11-06 |
United States Patent
Application |
20080276024 |
Kind Code |
A1 |
Meaney; Patrick J. ; et
al. |
November 6, 2008 |
Method for Stabilizing Asynchronous Interfaces
Abstract
A method and computer system apparatus for asynchronous data
transfer between a source and sink without the use of an
asynchronous control signal. includes metastability circuits, data
change detection logic, a stability window delay counter, and a
mux/register pair to allow for the holding of previous stable data
during the transition. While the processing logic employed
specifically applies to asynchronous logic, the logic can be
extended to synchronous or untimed interfaces as well. Also
disclosed is a programmable means to adjust the window delay.
Inventors: |
Meaney; Patrick J.;
(Poughkeepsie, NY) ; Cullen; Anthony P.;
(Ringwood, NJ) ; Fee; Michael; (Cold Spring,
NY) |
Correspondence
Address: |
INTERNATIONAL BUSINESS MACHINES CORPORATION
IPLAW DEPARTMENT, 2455 SOUTH ROAD - MS P386
POUGHKEEPSIE
NY
12601
US
|
Assignee: |
INTERNATIONAL BUSINESS MACHINES
CORPORATION
Armonk
NY
|
Family ID: |
39190016 |
Appl. No.: |
12/137600 |
Filed: |
June 12, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11532199 |
Sep 15, 2006 |
|
|
|
12137600 |
|
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Current U.S.
Class: |
710/117 ;
710/51 |
Current CPC
Class: |
G06F 13/4226
20130101 |
Class at
Publication: |
710/117 ;
710/51 |
International
Class: |
G06F 13/372 20060101
G06F013/372; G06F 3/00 20060101 G06F003/00 |
Claims
1. A method of data transfer from a source to a sink in a computer
system comprising the steps of: launching data onto a data bus;
capturing with a sink circuit from said data bus using sink circuit
logic including meta-stability register and stability registers,
data change detection logic and a stability window delay counter
and a multiplexor register pair are provided for holding previous
data during a transfer and wherein said sink circuit's
meta-stability registers stage the input data bus, and a stability
register holds previous data from said data bus coupled onto a sink
circuit output data bus, and wherein a multiplexor selects between
the output of a last of said stability registers and an output of
said stability register which holds previous data from said data
bus coupled onto a sink circuit output data bus, and with said sink
circuit detecting changes in data received at the sink; allowing
previous data to be observed when a change in data is detected;
releasing previous data and allowing new data to be observed after
a time period.
2. The method according to claim 1 wherein said sink circuit
includes a stability counter with a load input control, a load
input value bus, and a decrement increment control.
3. The method according to claim 2 wherein said sink circuit
further includes an edge detect circuit which compares input and
output buses of said stability register to determine if a change in
data has occurred which also activates said load input of said
stability counter thereto.
4. The method according to claim 3 wherein said sink circuit
further includes a counter detect circuit which decrements the
counter when it has a non-zero value and which also controls said
multiplexor to freeze said stability register at its present value
when the counter is not zero.
5. The method according to claim 4 wherein said stability counter
will decrement when the load and the decrement inputs are activated
simultaneously.
6. The method according to claim 1 wherein said sink circuit
includes a programmable register coupled to said stability register
circuit.
7. The method according to claim 1 wherein said sink circuit
stabilizes one or more data bus signals across an asynchronous or
untimed interface of said computer system without the use of a
separate control signal for computer system data transfer.
8. The method in accordance with claim 1 wherein said data transfer
is an asynchronous data transfer.
9. The method in accordance with claim 8 wherein said data transfer
is an asynchronous data transfer using no asynchronous control
signal.
10. The method in accordance with claim 1 wherein said time period
is implemented with a counter.
11. The method in accordance with claim 6 wherein said time period
is programmable.
12. The method according to claim 1 wherein said data is used for
determining in detecting changes in data received at the sink.
13. The method according to claim 6 wherein stabilization logic
prevents data from transitioning through incorrect states prior to
reaching a new steady state.
14. The method according to claim 7 wherein said data transfers in
the absence of a separate control signal.
15. The method according to claim 6 wherein a programmable delay
provides a window for detecting skew in the data being transferred.
Description
RELATED APPLICATIONS
[0001] This application is a divisional application based on U.S.
Ser. No. 11/532,199 filed Sep. 15, 2006 now entitled Apparatus for
Stabilizing Asynchronous Interfaces.
TRADEMARKS
[0002] IBM.RTM. is a registered trademark of International Business
Machines Corporation, Armonk, N.Y., U.S.A. Other names used herein
may be registered trademarks, trademarks or product names of
International Business Machines Corporation or other companies.
BACKGROUND OF THE INVENTION
[0003] 1. Field of the Invention
[0004] This invention relates to a transfer of data, and
particularly to a method of stabilizing one or more bus signals
across an asynchronous or untimed interface without the use of a
separate control signal for computer system data transfer.
[0005] 2. Description of Background
[0006] In an SMP computer, such as the IBM.RTM. z Series.RTM. of
mainframe computer systems manufactured by IBM, it is vitally
important to maintain high levels or performance and interlocking.
Many times, there are interfaces which are self-calibrating while
others are timed to strict early/late timing criteria. However,
self-calibrating logic can be costly in area. Asynchronous
interfaces pose a problem as well due to extra handshaking signals
that often cross between one side of the interface and another.
[0007] Many applications have data or controls that need to be sent
over the bus asynchronously, where latency is not a big concern.
Typically, metastability latches are added to help resolve possible
transitions on signals. There is typically one control signal that
is used for handshaking in one direction of the bus transfer. This
signal is used to edge-trigger a sampling event. It is important
that the data bus is stable before this signal is activated. Care
must be taken to make sure that this control signal has more
latency than the data bus. If not, the sampling could take place
while the normal data bus is still transitioning.
[0008] While prior art techniques solve some of the problems that
arise on asynchronous interfaces, there is a restriction that the
control signal is separate from the data. Attempts to use the data
bus to sample the data itself on an asynchronous interface can pose
incorrect data samples due to not all the data bits being
consistent on every cycle.
SUMMARY OF THE INVENTION
[0009] The data transfer interface in accordance with our invention
and the described embodiments does not require a separate control
signal. We have provided a mechanism wherein the data itself is
used for determining if the data has changed. The invention
provides stabilization logic which keeps the output data from
transitioning through incorrect or illegal states prior to reaching
the new steady-state
[0010] The invention also allows for a programmable delay for the
stability window to allow for unforeseen skews and noise that are
experienced.
[0011] System and computer program products corresponding to the
above-summarized methods are also described and claimed herein.
[0012] Additional features and advantages are realized through the
techniques of the present invention. Other embodiments and aspects
of the invention are described in detail herein and are considered
a part of the claimed invention. For a better understanding of the
invention with advantages and features, refer to the description
and to the drawings.
TECHNICAL EFFECTS
[0013] As a result of the summarized invention, for asynchronous or
untimed interfaces where data is stable and transitions to another
stable state, there is no need for a separate control signal for
the interface. This can save valuable wires, especially between
chips or other circuits. Also, the latency can be bound by the data
skew, so if data skew is less, the latency can be designed less for
that. The invention allows for a programmable latency to allow late
trade-offs between risk of corruption and latency/performance
without redesign.
BRIEF DESCRIPTION OF THE DRAWINGS
[0014] The subject matter which is regarded as the invention is
particularly pointed out and distinctly claimed in the claims at
the conclusion of the specification. The foregoing and other
objects, features, and advantages of the invention are apparent
from the following detailed description taken in conjunction with
the accompanying drawings in which:
[0015] FIG. 1 illustrates an example of Prior Art communication
from a source to a sink.
[0016] FIG. 2 illustrates an example of Prior Art asynchronous
receiver circuitry.
[0017] FIG. 3 illustrates an example of a data transfer method
incorporating the invention.
[0018] FIG. 4 illustrates a state diagram depicting a stabilization
technique featured in the invention.
[0019] FIG. 5 illustrates an example of a programmable stability
window duration value using a register.
[0020] FIG. 6 is a table depicting an example data bus stream and
the results with and without the invention.
[0021] The detailed description explains the preferred embodiments
of the invention, together with advantages and features, by way of
example with reference to the drawings.
DETAILED DESCRIPTION OF THE INVENTION
[0022] Turning now to the drawings in greater detail, it will be
seen that the prior art shown in FIG. 1 contains two circuits that
communicate with each other. Shown is a single-direction of the
communication. Data bus, 104, is driven by source circuit, 101, and
received by sink circuit, 102. There is also a control signal, 103,
that is sent from source circuit, 101, to sink circuit, 102.
Typically, the data bus, 104, will be allowed to switch and will
stabilize on a new value. Then, control signal, 103, will be used
to activate a strobe to sample the stable data.
[0023] FIG. 2 shows a more detailed diagram of prior art sink
logic, 102. In this embodiment, control signal, 103, and data bus,
104, enter asynchronous receiver circuit, 201. Shown are
metastability latches, 202, edge detect circuitry, 203, and staging
register or buffer, 204. There are numerous other embodiments for
implementing the prior art.
[0024] FIG. 3 depicts the preferred embodiment of a data transfer
method utilizing the invention. Unlike the prior art, there is no
control signal, 103, between source circuit, 310, and sink circuit,
301. Instead, the data bus, 312, is used directly in the means to
detect the data transition. Data bus, 312, gets staged through
metastability registers, 307. This is to ensure that the data is
consistent for downstream processing. There is a stability mux,
308, that allows new data to feed stability register, 302, that
normally captures the data every cycle. The output of the stability
register is compared to input of stability register using edge
detect circuit, 303. When there is a miscompare in the new and old
data bus values, the detect circuit, 303, loads a stability window
counter, 304, with stability window duration value bus, 305.
[0025] The predicted next counter state is available at the output
of the stability window counter, 304, on next counter state bus,
309. Next counter state bus, 309, feeds the counter detect circuit,
306, which determines if the next count will be zero or not. On the
same cycle the counter is loaded with the stability window duration
value bus, 305, the next counter state bus, 309, is non-zero. This
forces the stability mux, 308, to re-load the stability register,
302, with its previous value rather than allowing the new data to
enter the register. This causes the stability register, 302, to
freeze its state. The only way the register can be reloaded with
bus data is for the counter to reach zero.
[0026] Meanwhile, the counter detect circuit, 306, detects nonzero
counter values and will decrement the stability window counter,
304, until it eventually reaches zero.
[0027] The output of the stability register, 302, is available to
downstream logic as sink circuit stable output data bus, 311.
Because the stability register, 302, is controlled to wait before
sampling data that is transitioning, sink circuit stable output
data bus, 311, is also stable.
[0028] FIG. 4 shows a state diagram representing a method of the
invention. The system starts in the RUNNING state where stable data
is available. When a transition of any bit in the incoming data is
detected, the previous data is held as output. This transition also
causes a state change to the WAIT state. The invention will WAIT a
predefined period of time. Typically this is similar to a loaded
and decrementing counter. While in the WAIT state, output data is
still being held at the previous state. When the WAIT period is
over (e.g. count=0), there is a transition back to the RUNNING
state. The new data is then sent as output. The invention relies on
the fact that the WAIT period is at least as long as the maximum
instability window of the data. Also, the data should not be
allowed to switch again for at least a cycle after the guaranteed
WAIT period. Given that there is uncertainty in the timing, the
recommendation is to ensure that at least three maximum WAIT
periods occur before sending new data from the source.
[0029] FIG. 5 shows one implementation of a preferred way to supply
the stability window duration value bus, 305, using stability
window duration programmable register, 501. This register can be
loaded or changed based on many techniques known by those skilled
in the art.
[0030] FIG. 6 shows a table comparing incoming raw data to outgoing
data with and without the invention. Notice the illegal states
encountered when not using the invention which are never intended
to be sent on the original data bus. For instance, the source
circuit data bus only drives the patterns 00000, 00FF00, and 000FF.
Without the invention, the additional data patterns 0A000, 0E800,
00331, and 001FA may all show up as shown in this particular
example. They represent the skew and/or noise that may be
associated with data bits arriving at different times. However,
with the invention, only the 00000, 00FF00, and 000FF are observed
at the output.
[0031] While the figures and details describe a single-data bus,
unidirectional, asynchronous interface, one skilled in the art can
extend this concept to a multiple-bus, bi-directional (along with
acknowledgment protocols), interface or system. Also, while a
counter was shown in the invention, other means of delaying the
stability period can be constructed. While the description showed
the case where the stability register is normally unlocked and
allows stable data to stream through and then locks into a
stability window, the invention can be constructed such that data
is normally blocked from the stability window and only gets gated
into the stability register when there is stable data.
Consideration would need to be given to the start-up values of the
held data under these conditions. Many equivalent circuits and
methods can certainly be applied.
[0032] The drawings indicate particular circuit implementations,
but could also represent emulation of the same without departing
from the spirit of the invention.
[0033] The capabilities of the present invention can be implemented
in software, firmware, hardware or some combination thereof.
[0034] As one example, one or more aspects of the present invention
can be included in an article of manufacture (e.g., one or more
computer program products) having, for instance, computer usable
media. The media has embodied therein, for instance, computer
readable program code means for providing and facilitating the
capabilities of the present invention. The article of manufacture
can be included as a part of a computer system or sold
separately.
[0035] Additionally, at least one program storage device readable
by a machine, tangibly embodying at least one program of
instructions executable by the machine to perform the capabilities
of the present invention can be provided.
[0036] The flow diagrams depicted herein are just examples. There
may be many variations to these diagrams or the steps (or
operations) described therein without departing from the spirit of
the invention. For instance, the steps may be performed in a
differing order, or steps may be added, deleted or modified. All of
these variations are considered a part of the claimed
invention.
[0037] While the preferred embodiment to the invention has been
described, it will be understood that those skilled in the art,
both now and in the future, may make various improvements and
enhancements which fall within the scope of the claims which
follow. These claims should be construed to maintain the proper
protection for the invention first described.
* * * * *