U.S. patent application number 12/216951 was filed with the patent office on 2008-11-06 for method and apparatus for reading data from a ferromagnetic memory cell.
Invention is credited to Richard M. Lienau.
Application Number | 20080273368 12/216951 |
Document ID | / |
Family ID | 22691290 |
Filed Date | 2008-11-06 |
United States Patent
Application |
20080273368 |
Kind Code |
A1 |
Lienau; Richard M. |
November 6, 2008 |
Method and apparatus for reading data from a ferromagnetic memory
cell
Abstract
A ferromagnetic memory cell is disclosed. The cell includes a
bit (10), made of a ferromagnetic material, having a remnant
polarity. The cell also includes a read drive line (20) coupled to
a first portion of the bit (10), to feed a current into the bit
(10). A sense conductor (30) is coupled to a second portion of the
bit (10), to receive the current from the bit (10). The current
conducted through the bit (10) is responsive to the polarity of the
bit (10). A method is also disclosed for determining the magnetic
polarity of a ferromagnetic bit (10). In this method, a bit (10) is
provided that is made of ferromagnetic material and has a remnant
polarity. An input current (50) is fed into the bit (10) through a
read drive line (20) coupled to a first portion of the bit (10). An
output current (60) is received from the bit (10) through a sense
conductor (30) coupled to a second portion of the bit (10). The
current conducted through the bit (10) is responsive to the
polarity of the bit (10). A variance between the input current (50)
and output current (60) is then sensed, from which the magnetic
polarity of the bit (10) is determined.
Inventors: |
Lienau; Richard M.; (Pecos,
NM) |
Correspondence
Address: |
MORGAN LEWIS & BOCKIUS LLP
1111 PENNSYLVANIA AVENUE NW
WASHINGTON
DC
20004
US
|
Family ID: |
22691290 |
Appl. No.: |
12/216951 |
Filed: |
July 14, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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11645159 |
Dec 26, 2006 |
7414885 |
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12216951 |
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11089018 |
Mar 25, 2005 |
7177180 |
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11645159 |
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10239377 |
Sep 20, 2002 |
6873546 |
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PCT/US01/07409 |
Mar 8, 2001 |
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11089018 |
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60187981 |
Mar 9, 2000 |
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Current U.S.
Class: |
365/145 ;
257/421; 257/E29.323; 365/171 |
Current CPC
Class: |
G11C 11/18 20130101;
G11C 11/14 20130101; G11C 11/15 20130101 |
Class at
Publication: |
365/145 ;
257/421; 365/171; 257/E29.323 |
International
Class: |
G11C 11/22 20060101
G11C011/22; H01L 29/82 20060101 H01L029/82; G11C 11/00 20060101
G11C011/00 |
Claims
1-13. (canceled)
14. A memory device, comprising a substrate; a first conductor
formed on a surface of the substrate; a second conductor formed at
an angle relative to the first conductor; and a magnetic material
having a first end formed proximate to the first conductor and a
second end formed proximate to the second conductor, wherein when
an input current on the first conductor is directed into the
magnetic material, an output current results on the second
conductor at variance with the input current to indicate a stored
bit in the magnetic material.
15. The memory device of claim 14 wherein the second conductor is
formed at about 90 degrees relative to the first conductor.
16. The memory device of claim 14 wherein the magnetic material has
a height to width aspect ration of greater than 1:1.
17. The memory device of claim 14, further comprising a write coil
formed proximate to the magnetic material.
18. The memory device of claim 17 wherein the write coil surrounds
the magnetic material up to and including 270 degrees.
19. The memory device of claim 15 wherein the first conductor is
formed approximately centered along the first end of the magnetic
material.
20. The memory device of claim 15 wherein the second conductor is
formed approximately centered along the second end of the magnetic
material.
21. The memory device of claim 15 wherein the first conductor is
formed approximately along a side of the first end of the magnetic
material.
22. The memory device of claim 15 wherein the second conductor is
formed approximately along a side of the second end of the magnetic
material.
23. The memory device of claim 14 wherein the first and second
conductors are formed of copper.
24. The memory device of claim 14 wherein the first and second
conductors are formed of aluminum.
25. The memory device of claim 14 wherein the substrate is formed
from one of glass, silicon, or GaAs material.
26. A method of determining a magnetic polarity of a bit
comprising: providing a substrate; feeding an input current to a
first conductor formed on a surface of the substrate; directing the
input current into a magnetic material having a first end proximate
to the first conductor; and receiving an output current on a second
conductor formed proximate to a second end of the magnetic
material, wherein the second conductor is formed at an angle
relative to the first conductor and the output current is at
variance with the input current to indicate a stored bit in the
magnetic material.
27. The method of claim 26 wherein the second conductor is formed
at about 90 degrees relative to the first conductor.
28. The method of claim 27 wherein the first conductor is formed
approximately centered along the first end of the magnetic
material.
29. The method of claim 27 wherein the second conductor is formed
approximately centered along the second end of the magnetic
material.
30. The method of claim 27 wherein the first conductor is formed
approximately along a side of the first end of the magnetic
material.
31. The method of claim 27 wherein the second conductor is formed
approximately along a side of the second end of the magnetic
material.
Description
[0001] This application is a continuation of pending U.S.
application number Ser. No. 11/089,018 filed Mar. 25, 2005, which
is a continuation of U.S. application Ser. No. 10/239,377 filed
Sep. 20, 2002, now U.S. Pat. No. 6,873,546, which is a national
stage application of PCT application number PCT/US01/07409 filed on
Mar. 8, 2001, which claims the benefit of provisional U.S.
application No. 60/187,981 filed on Mar. 9, 2000, each of which is
incorporated herein by reference.
THE FIELD OF THE INVENTION
[0002] The present invention relates to reading data from a
ferromagnetic memory cell, and more particularly to employing
inductive interference to sense the magnetic polarity of the
storage medium.
BACKGROUND OF THE INVENTION
[0003] In a ferromagnetic memory cell, in which the storage medium
is a stick or rod normal to the plane of the substrate, the static
magnetic moment, or polarity, of the storage medium must be sampled
to determine in which of two directions, north or south, the
magnetic field is aligned at sense, or read time. Depending on the
polarity of the storage medium, a binary value of "zero" or "one"
is read. However, in accomplishing this sampling or sensing,
consideration must also be given to the amount of area required by
the sensing means. For example, in a matrix of memory cells, in
order to accomplish high-density, it is important to reduce the
area, or "real estate" required for data sense circuitry, as well
as increase data acquisition speed, and lower power
requirements.
[0004] Examples of patents related to non-volatile ferromagnetic
memory cells, each of which are herein incorporated by reference
for their supporting teachings, are as follows:
[0005] U.S. Pat. No. 4,360,899 to Dimyan et al. teaches a
non-volatile random access memory having a plurality of magnetic
cells arranged in an array on a major surface of a substrate. In
operation, a single magnetic cell is selected and inductively
switched between opposite remnant, (i.e. permanent) states, upon
the simultaneous application of electrical pulses has an amplitude
which is insufficient to inductively switch the remnant state of
the selected cell. However, the combined amplitude of the
electrical pulses is at least equal to the amplitude required for
such a switch.
[0006] U.S. Pat. No. 5,068,826 to Mathews teaches a non-volatile,
status magnetic memory device, whose operation is based on the Hall
effect. The device includes a magnetic patch which stores data in
the form of a magnetic field, a semiconductor Hall bar, and a pair
of integrally-informed bipolar transistors which are used for
amplifying and buffering the Hall voltage produced along the Hall
bar in use, current is forced to flow down the length of the Hall
bar causing the Hall voltage to be developed in a direction
transverse to the direction of both the magnetic field and the
current. The bases of the bipolar transistors are ohmically coupled
to the Hall bar to sense the Hall voltage--the polarity of which is
representative of the stores information. Finally, a system of
current carrying conductors is employed for writing data to
individual magnetic patches.
[0007] U.S. Pat. No. 5,295,097 to Lienau teaches a nonvolatile
random access memory having a substrate that carried separate
magnetically polarizable domains. Each domain is surrounded by a
full write loop member, and arranged to penetrate a Hall channel of
a dual drain FET with its residual magnetic field. The domains are
organized in word rows and bit columns, are each written to by a
single full write current through the surrounding loop member, and
each read by a comparator connected to the FET drains. Independent
separate write lines and read lines are used in writing and reading
the values of each magnetic bit.
[0008] U.S. Pat. No. 4,791,604 to Lienau et al. teaches a sheet
random access memory (SHRAM). The SHRAM is a nonvolatile and
transportable memory characterized by its cell density and
relatively small size and power requirements, but having the
nonvolatile character and rugged transportability of core memory,
or magnetic disks or tape. The SHRAM is further characterized by a
memory comprising a two dimensional magnetic substrate and a fixed
driving device for writing and reading into the substrate. Further,
a fixed sensing device for sensing the information is attached at
each cell location. The memory media includes not only a
homogeneous two dimensional substrate, but also ferrite cores
formed into the substrate by photolithographic techniques, wherein
the information is stores within the cores and read by the sensing
device from a gap defined by the core. Memory cells according to
the invention can thus be arranged and organized to form
destructive readout RAMs, or non-destructive readout Rams, in both
serial and parallel form.
[0009] U.S. Pat. No. 5,926,414 to McDowell et al. teaches a
magnetic integrated circuit structure in combination with a
carrier-deflection-type magnetic field sensor. Each of a variety of
magnet structures realize a condition in which the magnetic field
is substantially orthogonal to the direction of travel of carriers
of a sense current, thereby achieving maximum sensitivity. By
basing a magnetic memory cell on a single minimum size MOS device,
a small cell may be realized that compares favorably with a
conventional DRAM of FLASH memory cell. The greater degree of
control over the magnetic field afforded by the magnetic structures
enables the cross-coupling between cells in a memory array to be
minimized.
[0010] U.S. Pat. No. 3,727,199 to Lekven teaches a magnet memory
element and a process for producing such elements in plurality to
constitute a static magnetic memory or digital information storage
system. Individual binary storage members are afforded
directionally preferential magnetic characteristics by flux
circuits to establish the preferred axis of magnetization.
Conductors for driving the individual binary storage members (for
storing and sensing) are provided in an organized pattern to
accomplish selectivity. A batch production process is also
disclosed.
[0011] To date, there have been no commercial examples of
non-volatile ferromagnetic memories, capable of both random write
and random read, with truly simple data sense circuitry.
SUMMARY OF THE INVENTION
[0012] It is therefore a feature of the present invention to
provide a non-volatile ferromagnetic memories, capable of both
random write and random read, with truly simple data sense
circuitry.
[0013] The present invention relates to reading data from a
ferromagnetic memory cell, and more particularly to employing
inductive interference to sense the magnetic polarity of the
storage medium.
[0014] The ferromagnetic memory cell contains a bit made of a
ferromagnetic material that has a remnant polarity. The cell also
contains a read drive line coupled to a first portion of the bit
through which a current is fed into the bit. On a second portion of
the bit is a sense conductor. The sense conductor receives the
current from the bit and the current conducted through the bit is
responsive to the polarity of the bit.
[0015] In one embodiment, the read drive line is positioned
approximately perpendicular to a central axis running lengthwise
through the bit. The read drive line may also be positioned along a
top edge of the bit. Similarly, the sense conductor may be
positioned approximately perpendicular to the central axis or
positioned along a bottom edge of the bit. Furthermore, the read
drive line may be oriented at approximately a ninety degree
(90.degree.) angle relative to the sense conductor.
[0016] In a preferred embodiment both the read drive line and the
sense conductor are in direct contact with the bit. The bit also
preferably has a height to width aspect ratio of greater than
1:1.
[0017] A method of determining a magnetic polarity of a
ferromagnetic bit is also disclosed. In this method a bit is
provided that is made of a ferromagnetic material, and has a
remnant polarity. An input current is fed through a read drive line
that is coupled to a first portion of the bit. An output current is
then received from the bit through a sense conductor coupled to a
second portion of the bit. Again, the current conducted through the
bit is responsive to the polarity of the bit. A variance between
the input current and the output current is sensed, from which the
magnetic polarity of the bit is determined.
[0018] There has thus been outlined, rather broadly, the more
important features of the invention so that the detailed
description thereof that follows may be better understood, and so
that the present contribution to the art may be better appreciated.
Other features of the present invention will become clearer from
the following detailed description of the invention, taken with the
accompanying drawings and claims, or may be learned by the practice
of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0019] FIGS. 1A & 1B are cross-sectional representations of a
ferromagnetic memory cell.
[0020] FIGS. 2A & 2B are oblique representations of a
ferromagnetic memory cell.
[0021] FIG. 3 shows a representation of the ferromagnetic bit and
pulse current traveling through the bit.
[0022] FIG. 4 is a data sense, or read timing chart.
[0023] FIG. 5 is a partial schematic of a four-by-four random
access memory matrix.
[0024] FIGS. 6 & 7 show cross-sectional views of two preferred
embodiments of the memory cell.
[0025] It is noted that the drawings of the invention are not to
scale. The drawings are merely schematic representations, not
intended to portray specific parameters of the invention. The
drawings are intended to depict only selected embodiments of the
invention, and therefore should not be considered to be limiting
the scope of the invention. The invention will be described with
additional specificity and detail through the use of the
accompanying drawings. Like numbering between figures represent
like elements.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)
[0026] FIGS. 1A, 1B, 2A and 2B are cross-sectional and oblique
representations, respectively, of a ferromagnetic memory cell
comprised of a micron or sub-micron sized ferromagnetic bit 10
whose aspect ratio is greater than 1:1 (i.e., 2:1, etc.), deposited
normal to the plane of the substrate. The bit 10, which can be a
stick or rod, is in communication with a byte, or word, drive
conductor 20 at one end. The other end of the bit 10 is in
communication with a bit sense conductor 30. The data set, or write
drive, coil 280 (as seen in FIGS. 5-7) is not shown for the sake of
clarity.
[0027] FIGS. 1A and 2A show an embodiment of the present invention
wherein the byte, or word, drive conductor 20 is approximately
perpendicular to an axis 21 running lengthwise through the bit 10.
The bit sense conductor 30 is also approximately perpendicular to
the axis 21, and is oriented about ninety degrees (90.degree.)
relative to the orientation of the byte drive conductor 20.
[0028] FIGS. 1B and 2B show an embodiment of the present invention
wherein the byte drive conductor 20 runs along a top edge 22 of the
bit 10. The sense conductor 30 runs along a bottom edge 23 of the
bit 10 and is oriented approximately ninety degrees (90.degree.)
relative to the orientation of the byte drive conductor 20.
[0029] These two figures represent two different approaches to the
electrical relationship of the read drive 20 and read sense 30
conductors to the ferromagnetic bit 10. Electrically, there is no
essential difference between these two embodiments, but one may be
preferred over the other for purposes of fabrication.
[0030] In FIG. 3 the pulse current, as it travels through the
ferromagnetic bit 10, is schematically shown. The pulse current is
characterized by an input portion 50, which is the current as it is
directed into the bit 10, and an output portion 60, which is the
current as it comes out of the bit 10. The E and H fields generated
by the AC components of the pulse are represented by features 70
and 80 respectively.
[0031] FIG. 4 is a data sense, or read, timing chart. Reading the
chart from top to bottom, line 90 represents the byte drive line
with the raw input pulse 150 injected at read, or sense, time. Line
100 represents one of two bit sense, or read, output lines as seen
from the opposite end of the ferromagnetic bit. Line 110 represents
the second output. These two cases demonstrate the proximate result
from feeding the pulse 150 longitudinally through the bit with
opposite remnant magnetic fields. Line 120 represents the read, or
data sense, strobe present during data sense, or read time, at the
sense circuitry to which the bit sense conductor is electrically
connected. Lines 130 & 140 show the results from the two
different outputs 160 & 170. Line 130 is at zero (0) volts,
while line 140 shows a gated pulse 190. Thus, with these differing
outputs, the differing binary conditions of the ferromagnetic bit
can be determined. Note that no representation is made as to which
pulse or output is north or south, or represents a binary "zero" or
"one," in addition, the representations made may prove to be
different in reality.
[0032] The embodiment in FIG. 5 shows a partial schematic of a four
by four random access memory matrix 105 of the present invention. A
plurality of individual ferromagnetic bits 10 are each surrounded
by a coil which surrounds up to and including 270.degree., and is
intimate to the ferromagnetic stick. The coil is also referred to
as a write or drive line 13. The read drive line or byte conductor
20 is coupled to a first portion of the ferromagnetic bit 10. The
bit output or sense conductor 30 is coupled to a second portion of
the bit 10. The sense conductor 30 is coupled to a sense line 4.
Notably, the byte and sense conductors are preferably coupled at
opposite ends of each bit (not shown in this figure). The control
circuitry 32 comprises a read/write drive circuit 11, a read/write
switch 9 (in the form of an FET), and an input amplifier 15. The
control circuitry 32 is coupled to the write line 13, and to the
read drive conductor or read drive line 20. This dual coupling
allows the control 32 to be used during both write and sense read
operations. A write drive circuit 31 is also coupled to the write
line 13, as illustrated. Additionally, an amplifier 12 is coupled
to sense line 45 as illustrated.
[0033] During write operations of a single memory cell, appropriate
segments of the control circuit 32 and write drive circuit 31 are
activated simultaneously. One skilled in the art will easily
understand that current is directed in a desired direction, around
any given memory cell, to set a logical "0" or "1" into the
bit.
[0034] At data sense, or read, time, a pulse 50, whose duration,
amplitude and polarity are the same during each and every data
sample time, is introduced from the byte drive conductor 20, which
flows longitudinally through the ferromagnetic stick, or bit 10, to
the bit sense conductor 30. As the pulse courses through the
ferromagnetic bit 10, the rising and falling E field 70 generated
by the AC components of the pulse cross the remnant magnetic field
of the ferromagnetic bit 10 at an angle of ninety degrees
(90.degree.), while the H, or magnetic component, field 80 crosses
at zero degrees (0.degree.). The disturbance caused by the mutual
interference of these fields reflects into the pulse current 60,
causing the output which appears on the bit sense conductor to be
at variance with the input. This variance is sensed by circuitry
electrically connected to the bit sense conductor, allowing
determination of the polarity of the remnant magnetic field of the
bit 10, and thus the binary value, that is, a "zero" or a
"one".
[0035] During read operations of a single memory cell, appropriate
sections of the control circuit 32 and sense amplifier 12 are
simultaneously activated. Thus, one skilled in the art will easily
understand how individual memory cells can be read. It is noted
that by using the same control circuit 32 in combination with the
read 12 and write 31 circuits, there is an overall reduction in the
amount of circuitry needed to operate the memory cell. This
circuitry is representative only, and can be designed any number of
different ways by those familiar with the art.
[0036] FIGS. 6 and 7 show cross-sections of preferred embodiments
of the above-described memory cell fabricated at the micron,
sub-micron, or smaller scale. There is no functional difference
between these configurations. The difference is that in FIG. 6, the
word sense drive 20 and the bit sense conductor 30 are shown
positioned more or less centered at each end of the ferromagnetic
stock, or bit 10. FIG. 7 however, illustrates that the sense drive
and bit sense conductor can be offset to the sides of the bit 10.
All conductors or lines may be made of Al, Cu, or any other
suitable material. The write, or data set, coil 280 is shown in
both FIGS. 6 and 7. The substrate 290 may be made of any suitable
material such as glass, silicon, or GaAs. Insulating materials 310,
320, and 330 may be of an appropriate material such SiO.sub.2 or
Si.sub.3N.sub.4, etc.
[0037] It is noted that in this depiction, matrix interconnects are
not shown for the sake of clarity. It is also noted that several
methods may be employed to make the present invention, including,
but not limited to, electroplating, sputtering, E-beam deposition,
chemical vapor deposition and molecular beam epitaxy.
[0038] Furthermore, FIGS. 1A, 1B, 2A, 2B and 5 depict the
ferromagnetic memory cell as part of a matrix of cells. However,
the invention may be used in connection with any high-speed, dense,
nonvolatile digital memory or other circuitry where any amount of
memory, including single bits, may be required. This could be in
all manner of digital circuitry, including computers, robotics,
telephone and automotive circuits, security devices, and so on.
[0039] Numerous modifications and alternative arrangements may be
devised by those skilled in the art without departing from the
spirit and scope of the present invention and the appended claims
are intended to cover such modifications and arrangements. Thus,
while the present invention has been described above with
particularity and detail in connection with what is presently
deemed to be the most practical and preferred embodiments of the
invention, it will be apparent to those of ordinary skill in the
art that numerous modifications, including, but not limited to,
variations in size, materials, shape, form, function, manner of
operation, assembly, and use may be made without departing from the
principles and concepts set forth herein.
* * * * *