U.S. patent application number 12/216541 was filed with the patent office on 2008-11-06 for display device having misalignment detection pattern for detecting misalignment between conductive layer and insulating layer.
This patent application is currently assigned to Hitachi Displays, Ltd.. Invention is credited to Shinsaku Chiba, Yasushi Nakano.
Application Number | 20080273157 12/216541 |
Document ID | / |
Family ID | 35095464 |
Filed Date | 2008-11-06 |
United States Patent
Application |
20080273157 |
Kind Code |
A1 |
Nakano; Yasushi ; et
al. |
November 6, 2008 |
Display device having misalignment detection pattern for detecting
misalignment between conductive layer and insulating layer
Abstract
There is provided a display device of high display quality
having a circuit substrate, on which electronic parts are correctly
mounted in a manner to afford visually recognizing presence and
absence of misalignment of a solder resist opening with ease. The
display device comprises a display panel and a circuit substrate
connected to the display panel, the circuit substrate comprises an
insulating substrate, a conductive layer, an insulating layer to
cover a part of the conductive layer, a plating layer applied to
that portion of the conductive layer, which is exposed from the
insulating layer, and a misalignment detection pattern for
detection of misalignment between the conductive layer and the
insulating layer, and the misalignment detection pattern comprises
a pattern covered by the insulating layer in a manner to prevent
adherence of a plating material to the conductive layer.
Inventors: |
Nakano; Yasushi; (Tokyo,
JP) ; Chiba; Shinsaku; (Mobara, JP) |
Correspondence
Address: |
Stanley P. Fisher;Reed Smith LLP
Suite 1400, 3110 Fairview Park Drive
Falls Church
VA
22042-4503
US
|
Assignee: |
Hitachi Displays, Ltd.
|
Family ID: |
35095464 |
Appl. No.: |
12/216541 |
Filed: |
July 7, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11095603 |
Apr 1, 2005 |
7411294 |
|
|
12216541 |
|
|
|
|
Current U.S.
Class: |
349/149 |
Current CPC
Class: |
H05K 2203/166 20130101;
H05K 2201/09781 20130101; G02F 1/13452 20130101; H05K 3/28
20130101; H05K 1/0269 20130101; H05K 2203/163 20130101; H05K 3/243
20130101 |
Class at
Publication: |
349/149 |
International
Class: |
G02F 1/1345 20060101
G02F001/1345 |
Foreign Application Data
Date |
Code |
Application Number |
Apr 14, 2004 |
JP |
2004-119297 |
Claims
1. A display device comprising a display panel and a circuit
substrate connected to the display panel, wherein the display panel
includes an array substrate, the circuit substrate is separately
formed and positioned different from the array substrate and
comprises an insulating substrate, a conductive layer, and an
insulating layer to cover a part of the conductive layer, the
conductive layer of the circuit substrate includes a wiring
pattern, wiring terminals, and a meshy pattern, the wiring
terminals are exposed from the insulating layer and are applied
with a plating layer to a surface exposed from the insulating
layer, a misalignment detection pattern for detecting the
misalignment between the conductive layer and the insulating layer
is formed on the circuit substrate, the misalignment detection
pattern includes a first layer formed of the conductive layer, a
second layer formed of the insulating layer having an opening, the
first layer is connected with the meshy pattern and is supplied
with a predetermined potential, if the misalignment between the
conductive layer and the insulating layer is smaller than a
predetermined misalignment tolerance, the first layer is wholly
covered by the second layer in a manner to prevent adherence of a
plating material to the first layer, and if the misalignment
between the conductive layer and the insulating layer is larger
than the predetermined misalignment tolerance, a part of the first
layer is exposed from the second layer at the opening in a manner
to be applied with plating.
2. The display device according to claim 1, wherein the opening of
the second layer is surrounded by the first layer.
3. The display device according to claim 2, wherein the first layer
is formed in a frame shape.
4. The display device according to claim 1, wherein the first layer
is formed in a frame shape.
5. The display device according to claim 1, wherein the first layer
and meshy pattern are supplied with a ground potential.
6. The display device according to claim 1, wherein the circuit
substrate is a flexible printed circuit substrate.
7. The display device according to claim 1, wherein an electronic
part is mounted on one of the wiring terminals of the circuit
substrate.
8. The display device according to claim 1, wherein the circuit
substrate covers a part of a back surface of the display panel.
9. The display device according to claim 1, wherein the circuit
substrate covers a part of a side surface of the display panel.
10. The display device according to claim 1, wherein the display
panel is a liquid crystal display panel having a backlight, and the
circuit substrate covers a part of a back surface of the
backlight.
11. The display device according to claim 10, wherein a drive
circuit chip is mounted on the array substrate of the liquid
crystal display panel, and the circuit substrate is connected at
one end thereof to the drive circuit chip and at the other end
thereof to another substrate provided on the back surface of the
backlight.
12. The display device according to claim 1, wherein the display
panel is a liquid crystal display panel, an organic
electroluminescence (EL) display panel, a field emission type
display (FED) panel, or a plasma display panel.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation of nonprovisional U.S.
application Ser. No. 11/095,603 filed on Apr. 1, 2005. Priority is
claimed based on U.S. application Ser. No. 11/095,603 filed on Apr.
1, 2005, which claims the priority of Japanese Application
2004-119297 filed on Apr. 14, 2004, all of which is incorporated by
reference.
BACKGROUND OF THE INVENTION
[0002] The present invention relates to a display device, and more
particular, to a display device making use of a flat-surface type
display panel, and is suited to a circuit substrate that supplies a
signal and a voltage required for driving of a display panel.
[0003] Display devices of various types such as liquid crystal
display devices making use of a liquid crystal panel as a display
panel, which constitutes a highly-accurate flat-surface type
display device capable of color display for portable telephones,
note-sized computers, or display monitors, organic
electroluminescence display devices (organic EL display devices),
field emission type display devices (FED), plasma display devices,
or the like have already come into practical use, or are in the
study phase of commercial application.
[0004] In particular, high accuracy and lightening are greatly
demanded of display devices used for portable telephones in recent
years. Display devices of this type propagate as a display module,
in which a backlight, a drive circuit, a peripheral circuit, etc.
are incorporated into a display panel such as liquid crystal panel,
etc. In, for example, display modules for portable telephones,
various signals and voltages for display are supplied to a drive
circuit chip, which is mounted on a substrate of a display panel,
from a signal processing circuit substrate with the use of a
flexible printed circuit substrate (FPC). In addition, while the
invention is not limited to FPC but is also applicable to a
so-called printed circuit substrate, it is described here taking a
FPC as a typical example.
[0005] Such circuit substrates called FPC mount solder mounted
parts such as resistors, capacitors, etc. and comprise an
insulating substrate made of base film, a conductive layer of
copper or the like to constitute a wiring pattern, an insulating
layer to cover a part of the conductive layer, and a plating layer
applied to that portion of the conductive layer, which is exposed
from the insulating layer. Solder resist (insulating layer), which
serves to avoid adherence of a plating layer to portions except a
necessary conductive layer, is coated or stuck to a region, in
which solder mounted parts are mounted. An opening is formed in the
solder resist and terminals of parts being mounted are
solder-connected to wiring terminals exposed from the opening.
[0006] FIGS. 12A and 12B are views illustrating misalignment
between an opening of solder resist and a conductive layer in a
conventional FPC, FIG. 12A being a cross sectional view, and FIG.
12B being a plan view. In FIGS. 12A and 12B, upper sections
illustrate the case where there is no misalignment between an
opening of solder resist and a conductive layer, and lower sections
illustrate the case where there is misalignment between the opening
of the solder resist SRG and the conductive layer. In FIGS. 12A and
12B, a FPC comprises an insulating substrate BFM made of a base
film, a conductive layer (a wiring pattern of copper) CPT, solder
resist SRG being an insulating layer to cover a part of the
conductive layer CPT, and a gold plating layer APL applied to that
portion of the conductive layer CPT, which is exposed from the
solder resist SRG. FIG. 12A shows a laminated state of the
elements, and FIG. 12B shows an opening of the solder resist SRG
and a state of misalignment in a plane of the opening.
[0007] In the case where there is no misalignment between the
opening of the solder resist and the conductive layer, the gold
plating layer APL is correctly formed on the conductive layer (a
wiring pattern of copper) CPT within the opening of the solder
resist, as shown in the upper sections of FIGS. 12A and 12B. In
contrast, in the case where there is misalignment S of at least
.DELTA.S between the opening of the solder resist and the
conductive layer, there comes out a state, in which the gold
plating layer APL formed on the conductive layer (a wiring pattern
of copper) CPT becomes narrow within the opening of the solder
resist SRG and the insulating substrate BFM made of a base film is
exposed to a A region, as shown in the lower sections of FIGS. 12A
and 12B. When electronic parts are mounted in such state, there
occurs a state, in which terminals of the electronic parts are not
connected normally to the gold plating layer APL formed on the
conductive layer CPT.
[0008] Shift of an opening of solder resist formed on a FPC from a
normal position is prescribed to be, for example, at most 0.1 mm
while being according to a degree of minuteness of a wiring
pattern. Conventionally, an amount of misalignment of a solder
resist opening is visually inspected with the use of a microscope
of about 10 magnifications.
SUMMARY OF THE INVENTION
[0009] In case of using polyimide as a base film for a
lower-layered insulating substrate, both its body color and a body
color of solder resist are of the same family color (yellow
translucent color), so that it is hard to decide a boundary between
the both and it is difficult to ascertain misalignment and to
measure an amount of misalignment, thus bringing about a
possibility that misalignment is recognized to be too small. In the
case where solder resist is substantially colorless and
transparent, it is likewise difficult to decide a boundary between
the both. When misalignment of a solder resist opening is
underestimated in this manner, there is incurred failure in
mounting of electronic parts, so that there is caused degradation
in indicated quality.
[0010] The invention has an advantage that it is possible to
provide a display device of high display quality having a circuit
substrate, on which electronic parts are correctly mounted in a
manner to afford visually recognizing presence and absence of
misalignment of a solder resist opening with ease even when a body
color of solder resist and a body color of insulating substrate are
of the same family.
[0011] The advantage can be achieved by providing a misalignment
detection pattern on a circuit substrate such as FPC, etc. and
composing the misalignment detection pattern from a conductive
layer for detection of misalignment, formed simultaneously from the
same material as that of a conductive layer used for wiring and
terminals, and an insulating layer, which covers the conductive
layer for detection of misalignment with a predetermined
misalignment tolerance .DELTA.S from an edge of the conductive
layer for detection of misalignment in a manner to prevent a
plating material from adhering to the conductive layer for
detection of misalignment.
[0012] When a pattern of the conductive layer and solder resist are
shifted at least a predetermined misalignment tolerance .DELTA.S
from each other, the conductive layer for detection of
misalignment, which amounts to a magnitude beyond the predetermined
misalignment tolerance .DELTA.S, is exposed from the solder resist.
Plating (usually, gold plating) adheres to a region on the
conductive layer for detection of misalignment, which amounts to a
magnitude beyond the predetermined distance .DELTA.S, in a
post-process. When misalignment is less than the predetermined
distance .DELTA.S, there is no adherence of plating. Thereby,
misalignment between the pattern of the conductive layer and an
opening of solder resist is judged on the basis of presence and
absence of plating, of which visibility is high, and a magnitude of
misalignment is made easy to measure.
[0013] A typical constitution of the invention is as follows. That
is, a display device of the invention comprises (1) a display panel
and a circuit substrate connected to the display panel. The circuit
substrate comprises an insulating substrate, a conductive layer, an
insulating layer to cover a part of the conductive layer, a plating
layer applied to that portion of the conductive layer, which is
exposed from the insulating layer, and a misalignment detection
pattern for detection of misalignment between the conductive layer
and the insulating layer. The misalignment detection pattern
comprises a pattern covered by the insulating layer in a manner to
prevent adherence of a plating material to the conductive
layer.
[0014] (2) In (1), the misalignment detection pattern comprises an
opening formed on the insulating layer to allow the insulating
substrate to be exposed, and the conductive layer formed distant a
predetermined distance from the opening to surround the opening and
covered by the insulating layer.
[0015] (3) In (2), the conductive layer surrounding the opening of
the misalignment detection pattern comprises a pattern itself,
which is unitarily continuous.
[0016] (4) In (2), the conductive layer surrounding the opening of
the misalignment detection pattern comprises a plurality of
discrete patterns.
[0017] (5) In (1), the misalignment detection pattern comprises the
conductive layer formed to be island-shaped, and the insulating
layer formed to be island-shaped to cover the island-shaped
conductive layer.
[0018] (6) In (1), the conductive layer of the misalignment
detection pattern is supplied with a predetermined potential.
[0019] (7) In (1), the conductive layer of the misalignment
detection pattern is electrically floating.
[0020] (8) In any one of (1) to (7), the circuit substrate
comprises a flexible printed circuit substrate.
[0021] (9) In any one of (1) to (8), an electronic part is mounted
on that portion of the circuit substrate, on which the plating
layer is formed.
[0022] In addition, the invention is not limited to the
constitution described above and a constitution disclosed in
embodiments described later but it goes without saying that various
modifications can be made without departing from the technical
thought of the invention.
[0023] According to the invention, a display device of high display
quality can be provided by using such circuit substrate to
constitute a display device.
BRIEF DESCRIPTION OF THE DRAWINGS
[0024] FIGS. 1A and 1B are views illustrating misalignment between
an opening of solder resist and a conductive layer in a FPC
according to an embodiment 1 of the invention;
[0025] FIGS. 2A and 2B are views illustrating misalignment between
an opening of solder resist and a conductive layer in a FPC
according to an embodiment 2 of the invention;
[0026] FIGS. 3A to 3F are plan views illustrating various
configurational examples of misalignment detection patterns
according to the invention;
[0027] FIG. 4 is a view illustrating an example of a specific
arrangement of misalignment detection patterns on a FPC;
[0028] FIG. 5 is a schematic view showing a state, in which an
electronic part is mounted on a FPC;
[0029] FIG. 6 is a plan view in the case where solder resist
openings for wiring terminals, disposed in those portions of a FPC,
on which electronic parts are mounted, do not involve misalignment
of at least a predetermined misalignment tolerance .DELTA.S;
[0030] FIG. 7 is a plan view in the case where solder resist
openings for wiring terminals, disposed in those portions of a FPC,
on which electronic parts are mounted, involve misalignment of at
least the predetermined misalignment tolerance .DELTA.S;
[0031] FIG. 8 is a plan view illustrating an actual example of a
misalignment detection pattern according to the invention;
[0032] FIG. 9 is a view illustrating a specific example of
dimensions of the detection pattern shown in FIG. 8;
[0033] FIG. 10 is a schematic view of a cross section illustrating
a constructional example of a FPC, to which the invention is
applied;
[0034] FIG. 11 is a schematic view of a cross section illustrating
a liquid crystal module for portable telephones as an example of
application of a display device according to the invention; and
[0035] FIGS. 12A and 12B are views illustrating misalignment
between an opening of solder resist and a conductive layer in a
conventional FPC.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0036] Embodiments of a display device according to the invention
will be described below in detail with reference to the drawings.
In addition, while the following embodiments are described taking a
liquid crystal display device as an example of the display device
according to the invention, it goes without saying that they are
applicable to other display devices such as organic EL display
devices, FED, etc.
Embodiment 1
[0037] FIGS. 1A and 1B are views illustrating misalignment between
an opening of solder resist and a conductive layer in a FPC
according to an embodiment 1 of the invention, FIG. 1A being a
cross sectional view, and FIG. 1B being a plan view. In FIGS. 1A
and 1B, upper sections illustrate the case where there is
misalignment less than a predetermined misalignment tolerance
between the opening of the solder resist and the conductive layer,
and lower sections illustrate the case where there is misalignment
of at least the predetermined misalignment tolerance between the
opening of the solder resist SRG and the conductive layer. In FIGS.
1A and 1B, the FPC comprises an insulating substrate BFM made of a
base film, a misalignment detection pattern SCP formed from a
conductive layer of copper (Cu), and solder resist SRG covering the
misalignment detection pattern SCP and formed with an opening, to
which the insulating substrate BFM is exposed. Illustration of a
wiring pattern is omitted.
[0038] According to the present embodiment, the misalignment
detection pattern SCP is in the form of a rectangular frame and is
formed to surround the opening of the solder resist SRG. As shown
in the upper sections, when misalignment between the opening of the
solder resist and the misalignment detection pattern SCP is less
than a predetermined misalignment tolerance .DELTA.S, plating is
not formed on the misalignment detection pattern about the opening
of the solder resist SRG through a gold plating processing in the
subsequent process.
[0039] On the other hand, as shown in the lower sections, when an
amount S of misalignment between the opening of the solder resist
and the misalignment detection pattern SCP becomes at least the
predetermined misalignment tolerance .DELTA.S, the misalignment
detection pattern SCP is exposed from the opening of the solder
resist. Therefore, when going through a gold plating processing in
the subsequent process, gold plating APL is formed on the
misalignment detection pattern SCP exposed from the opening of the
solder resist SRG. Since there is a large difference in hue and
brilliance between a C portion, to which the gold plating APL is
applied, and the solder resist SRG in the vicinity thereof, or the
substrate BFM, it is possible to visually recognize presence of
misalignment between the both and an amount of misalignment with
ease. Accordingly, such detection of misalignment can prevent a
defective FPC from being used for products, thus enabling obtaining
a display device of high quality and high reliability.
[0040] FIGS. 2A and 2B are views illustrating misalignment between
an opening of solder resist and a conductive layer in a FPC
according to an embodiment 2 of the invention, FIG. 2A being a
cross sectional view, and FIG. 2B being a plan view. In FIGS. 2A
and 2B, upper sections illustrate the case where there is
misalignment less than a predetermined misalignment tolerance
between the opening of the solder resist and a misalignment
detection pattern SCP, and lower sections illustrate the case where
there is misalignment of at least the predetermined misalignment
tolerance between the opening of the solder resist SRG and the
misalignment detection pattern SCP. Illustration of a wiring
pattern is omitted.
[0041] According to the present embodiment, the misalignment
detection pattern SCP is made island-shaped. As shown in FIGS. 2A
and 2B, a conductive layer preferably made of copper (Cu) is used
to form an island-shaped misalignment detection pattern SCP on the
insulating substrate BFM, and the solder resist SRG is formed on
the pattern. A predetermined misalignment tolerance .DELTA.S is set
between an edge SRG of at least a side of the solder resist SRG and
an edge of the misalignment detection pattern SCP.
[0042] As shown in the upper sections of FIGS. 2A and 2B, when
misalignment between the opening of the solder resist SRG and the
misalignment detection pattern SCP is less than the predetermined
misalignment tolerance .DELTA.S, plating is not formed on the
misalignment detection pattern SCP through a gold plating
processing in the subsequent process.
[0043] In contrast, as shown in the lower sections of FIGS. 2A and
2B, when an amount S of misalignment between the opening of the
solder resist SRG and the misalignment detection pattern SCP
becomes at least the predetermined misalignment tolerance .DELTA.S,
the misalignment detection pattern SCP is exposed from an edge of
the solder resist SRG. Therefore, when going through a gold plating
processing in the subsequent process, gold plating APL is formed on
the misalignment detection pattern SCP exposed from the solder
resist SRG. Since there is a large difference in hue and brilliance
between a C portion, to which the gold plating APL is applied, and
the solder resist SRG in the vicinity thereof, or the substrate
BFM, it is possible to visually recognize presence of misalignment
between the both and an amount of misalignment with ease.
Accordingly, such detection of misalignment can prevent a defective
FPC from being used for products, thus enabling obtaining a display
device of high quality and high reliability.
[0044] FIGS. 3A to 3F are plan views illustrating various
configurational examples of misalignment detection patterns
according to the invention. FIG. 3A shows a misalignment detection
pattern in the form of the same rectangular frame as that of the
detection pattern described in the embodiment 1. FIG. 3B shows a
misalignment detection pattern in the form of a ring, FIG. 3C shows
a misalignment detection pattern in the form of discrete frames,
FIG. 3D shows the same island-shaped misalignment detection pattern
as that described in the embodiment 2, and FIG. 3E shows a
circular-shaped and island-shaped misalignment detection pattern.
Also, FIG. 3F shows an additional configuration for connection of a
misalignment detection pattern to a grounding conductor provided on
the insulating substrate. In addition, a shape of the misalignment
detection pattern is not limited to the above.
[0045] It does not matter if a conductive layer (SCP) in the
misalignment detection pattern is electrically floating in case of
electroless plating. Accordingly, both the embodiment 1 and the
embodiment 2 are applicable in case of electroless plating.
[0046] In case of electroplating, although not shown, both the
embodiment 1 and the embodiment 2 are applicable, for example, when
a wiring layer for application of electric potential is formed on a
conductive layer (SCP) in the misalignment detection pattern as
shown in FIG. 3F. This is because there is a need for application
of plating potential in the plating processing. However, the
embodiment 1 is suited to electroplating as compared with the
embodiment 2 since the former makes it possible to detect
misalignment in the opening of the solder resist SRG without being
affected by such wiring layer. In addition, when assembled into a
display module, it is desirable to supply a predetermined electric
potential such as ground potential.
[0047] FIG. 4 is a view illustrating an example of a specific
arrangement of misalignment detection patterns on a FPC. The FPC
includes a mount region EPA of electronic parts centrally thereof,
and misalignment detection patterns SCP are formed on both sides of
the mount region EPA.
[0048] FIG. 5 is a schematic view showing a state, in which an
electronic part is mounted on the FPC. The electronic part EP is
mounted on the FPC by using solder SLR to connect terminals of the
electronic part EP to gold plating APL applied to an electrode CPT
of a wiring pattern being a conductive layer formed on an
insulating substrate BFM (base film) of the FPC. A major part of
the wiring pattern is covered by solder resist SRG as an insulating
layer.
[0049] FIG. 6 is a plan view in the case where solder resist
openings for wiring terminals, disposed in those portions of the
FPC, on which the electronic parts are mounted, do not involve
misalignment of at least a predetermined misalignment tolerance
.DELTA.S, and FIG. 7 is a plan view in the case where solder resist
openings for wiring terminals, disposed in those portions of the
FPC, on which the electronic parts are mounted, involve
misalignment of at least the predetermined misalignment tolerance
.DELTA.S. As shown in FIG. 6, when there is no misalignment between
conductive layers (wiring terminals) CPT and solder resist openings
SRG-AT, gold plating layers APL are formed in sufficient areas on
the conductive layers (wiring terminals) CPT. Therefore, the
electronic parts are mounted correctly.
[0050] In contrast, as shown in FIG. 7, when there is misalignment
S, which is at least a predetermined distance .DELTA.S
(misalignment tolerance), between the conductive layers (wiring
terminals) CPT and the solder resist openings SRG-AT, the gold
plating layers APL are not formed in sufficient areas on the
conductive layers (wiring terminals) CPT, so that the electronic
parts are mounted unstably.
[0051] FIG. 8 is a plan view illustrating an actual example of a
misalignment detection pattern according to the invention. In this
example, the misalignment detection pattern of the embodiment 1
illustrated in FIG. 1 is formed in a region of a ground pattern
CP-MS provided on a FPC. The ground pattern CP-MS shown in FIG. 8
is meshy, and the misalignment detection pattern is embedded in the
meshy ground pattern CP-MS. Accordingly, the misalignment detection
pattern is formed by coating or applying solder resist over the
whole meshy ground pattern CP-MS to cover a frame-shaped conductive
layer CPT-PT, and includes a solder resist opening SRG-AT inside
the frame-shaped conductive layer CPT-PT. In addition, the figure
shows a state, in which no misalignment is present in the solder
resist opening SRG-AT, and a portion CP-EM with no conductive layer
is present between the solder resist opening SRG-AT and the
frame-shaped conductive layer CPT-PT. In addition, the ground
pattern CP-MS is not limited to a meshy one but may be one, in
which copper foil or the like is formed wholly. In addition,
instead of ground potential, a predetermined potential may be
applied to the ground pattern CP-MS. Also, in case of electroless
plating, plating potential is applied to the ground pattern CP-MS
in a processing of plating.
[0052] FIG. 9 is a view illustrating a specific example of
dimensions of the detection pattern shown in FIG. 8. The detection
pattern is in the form of a square frame, and a conductive layer
CPT-PT thereof has the following dimensions. The frame of the
conductive layer CPT-PT has a width of at least 0.1 mm, a side of
the solder resist opening SRG-AT has a width of at least 0.3 mm, a
width between an inner edge of the solder resist opening SRG-AT, an
inner edge of the frame-shaped conductive layer CPT-PT, that is, a
width of the portion CP-EM with no conductive layer is 0.1 mm being
the misalignment tolerance .DELTA.S, and other dimensions are as
shown in the figure.
[0053] FIG. 10 is a schematic view of a cross section illustrating
a constructional example of a FPC, to which the invention is
applied. The FPC is a so-called double-FPC having a two-layered
conductive pattern. A conductive layer CPT1 made of electrolytic
copper foil is patterned on both surfaces of a base film BFM being
an insulating substrate. Electrolytic copper plating PCT2 is
applied to an upper layer of the conductive layer CPT1. With the
double-FPC, the conductive layer CPT1 and the copper plating PCT2
are laminated to make conductive layers CPT. The reference
character SRG denotes solder resist, AD an adhesive, SC a cover
film, UBL a nickel backing layer, APL a gold plating layer, and AFF
a front-side reinforcement film, AFR a back-side reinforcement
film. The front and back conductive layers CPT are connected to
each other through a through-hole TH at need.
[0054] The FPC is manufactured in the following processes. First,
in a pre-process, (1) a through-hole TH is formed in an insulating
substrate BFM formed with a non-patterned conductive layer CPT1,
and a copper plating PCT2 is applied in order to connect
double-conductive layers CPT1 to each other through the
through-hole TH. (2) Photosensitive resist film is laminated
(stuck), or photosensitive resist is coated, and pattern exposure
and etching are performed to form a pattern of the conductive
layers CPT. (3) Back-side cover film Sc is laminated and curing is
performed in an oven. (4) Subsequently, solder resist SRG is
laminated on a surface, on which an electronic part is mounted,
exposure and developing are performed to form a necessary opening
including a misalignment detection pattern, and curing is
performed. (5) Reinforcement films AFF, AFR are adhered to a FPC
with the use of an adhesive AD. (6) Nickel plating UBL and gold
plating APL are applied in the plating process.
[0055] In addition, while according to the embodiment the resist
film of photosensitive film type is laminated when the solder
resist SRG is formed, this is not limitative but photosensitive
liquid resist may be applied. Also, a material for plating in the
plating process is not limited to nickel and gold but other
materials may be used. The insulating substrate BFM is not limited
to polyimide but other materials may be used.
[0056] In a post-process, punching for a necessary shape is
performed and a process of inspection follows. In the process of
inspection, a microscope of about 10 magnifications is used to
perform inspection. When misalignment of at least a predetermined
amount is present in the inspection, plating adheres to a copper
pattern protruding from the solder resist to afford visual
inspection of misalignment with ease. In addition, the inspection
may be performed before punching as far as it is performed after
the plating process.
[0057] FIG. 11 is a schematic view of a cross section illustrating
a liquid crystal module for portable telephones as an example of
application of a display device according to the invention. The
liquid crystal module for portable telephones comprises a backlight
BL provided on a back surface of a liquid crystal panel PNL having
two glass substrates SUB1, SUB2, these elements being accommodated
in a mold casing MD to be made unitary. A drive circuit chip (IC
chip) D-IC is mounted on one SUB1 of the glass substrates of the
liquid crystal panel PNL. A FPC mounting thereon electronic parts
EP is connected at one end thereof to the drive circuit chip D-IC
and at the other end thereof to a signal processing circuit
substrate (not shown) provided on a back surface of the backlight
BL.
[0058] The invention is not limited to a display device, which
makes use of a liquid crystal panel, but is also applicable to a
display device, which makes use of other display panels such as
organic EL display devices, FED, etc., or other electronic
devices.
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