U.S. patent application number 12/174735 was filed with the patent office on 2008-11-06 for method of manufacturing semiconductor device having recess gate structure with varying recess width for increased channel length.
Invention is credited to Jong Man KIM, Jong Sik KIM, Chang Goo LEE, Se Ra WON.
Application Number | 20080272431 12/174735 |
Document ID | / |
Family ID | 37184957 |
Filed Date | 2008-11-06 |
United States Patent
Application |
20080272431 |
Kind Code |
A1 |
KIM; Jong Man ; et
al. |
November 6, 2008 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING RECESS GATE
STRUCTURE WITH VARYING RECESS WIDTH FOR INCREASED CHANNEL
LENGTH
Abstract
A varying-width recess gate structure having a varying-width
recess formed in a semiconductor device can sufficiently increase
the channel length of the transistor having a gate formed in the
varying-width recess, thereby effectively reducing the current
leakage and improving the refresh characteristics. In the method of
manufacturing the recess gate structure, etching is performed twice
or more, so as to form a gate recess having varying width in the
substrate, and a gate is formed in the gate recess.
Inventors: |
KIM; Jong Man; (Kyoungki-do,
KR) ; LEE; Chang Goo; (Kyoungki-do, KR) ; KIM;
Jong Sik; (Kyoungki-do, KR) ; WON; Se Ra;
(Kyoungki-do, KR) |
Correspondence
Address: |
LADAS & PARRY LLP
224 SOUTH MICHIGAN AVENUE, SUITE 1600
CHICAGO
IL
60604
US
|
Family ID: |
37184957 |
Appl. No.: |
12/174735 |
Filed: |
July 17, 2008 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
11318960 |
Dec 27, 2005 |
7413969 |
|
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12174735 |
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Current U.S.
Class: |
257/330 ;
257/E21.2; 257/E21.218; 257/E21.219; 257/E21.232; 257/E21.429;
257/E29.27 |
Current CPC
Class: |
H01L 21/3081 20130101;
H01L 29/66621 20130101; H01L 21/30604 20130101; H01L 21/3065
20130101; H01L 21/28061 20130101 |
Class at
Publication: |
257/330 ;
257/E29.27 |
International
Class: |
H01L 29/78 20060101
H01L029/78 |
Foreign Application Data
Date |
Code |
Application Number |
Jun 30, 2005 |
KR |
10-2005-0058570 |
Claims
1. A recess gate structure for a transistor in a semiconductor
device having a semiconductor substrate having an active areas
defined by isolation regions, the recess gate structure comprising:
a varying-width recess having a first recess width formed in the
semiconductor substrate for a first recess depth measured from the
surface of the semiconductor substrate and having a second recess
width narrower than the first recess width and extending
continuously into the semiconductor substrate from the bottom end
of the first recess width, wherein the second recess depth measured
from the surface of the semiconductor substrate is longer than the
first recess depth measured from the surface of the semiconductor
substrate; and a transistor gate formed in the varying-width recess
formed in the semiconductor substrate.
Description
BACKGROUND OF THE INVENTION
[0001] 1. Field of the Invention
[0002] The present invention relates generally to a method of
manufacturing a semiconductor device, and more particularly to a
method of manufacturing a semiconductor device having recess
structure for increased channel length.
[0003] 2. Description of the Prior Art
[0004] The conventional transistors having planar structures are
unable to keep up with the technological demands of the recent
advances in the integration of DRAM devices, such that, for
example, these conventional transistors are unable to meet the
required threshold target of the device in which the transistors
are integrated. The advanced integration of DRAM devices requires
reduction in the minimum feature size, and to reduce the minimum
feature size the doping density is increased in a substrate, which
inevitably increases the electric field as well as the junction
leakage in the transistor.
[0005] Therefore, a three-dimensional active structure called a
"recess gate structure," which is considered to having effects on
lowering the substrate doping density and reducing the junction
leakage, is newly emerging.
[0006] According to the conventional recess gate structure, an
active area for formation of a gate is recessed, and a gate is
formed on the recessed area of the active area, thereby increasing
the channel length. Such conventional recess gate structure formed
in the given active area may be able to reduce the substrate doping
density, thereby increasing the data retention time. Further, the
increase in the channel length (due to the recess channel structure
in the given active area) can improve the characteristics with
respect to the drain induced barrier lowering (DIBL) and the
breakdown voltages (BVds), thereby may be able to improve the
overall cell properties.
[0007] Because the recess channel structure is shown to extend the
data retention time by, for example, more than 200 ms, it is
expected that the recess channel structure be utilized in the DRAM
devices below a level of the sub-90 nm.
[0008] As mentioned above, a gate having the recess channel
structure formed on the recessed area of the active area is capable
of increasing the channel length. However, when the given active
area is reduced, the channel length will also have to be reduced
even in the case of the recess gate structure undercutting the
advantages gained. Thus, there will be less reduction of leakage
current in the junction area and near elimination of the
improvement in the refresh characteristics of the devices. As a
result, it is impossible to secure consistent reliability and yield
for the devices with reduced active area.
SUMMARY OF THE INVENTION
[0009] Accordingly, the present invention has been made to solve
the above-mentioned and other problems occurring in the prior art,
and an object of the present invention is to provide a method of
manufacturing a semiconductor device, which can sufficiently
increase the channel length.
[0010] It is another object of the present invention to provide a
method of manufacturing a semiconductor device, which can
sufficiently increase the channel length, thereby effectively
reducing current leakage and improving the refresh
characteristics.
[0011] In order to accomplish this object, there is provided a
method of manufacturing a semiconductor device, the method
comprising the steps of: preparing a semiconductor substrate on
which an isolation layer defining an active area is formed;
sequentially forming an oxide layer, a poly-silicon layer, and a
reflection-proof layer on the semiconductor substrate; forming a
mask pattern defining an expected substrate recess area on the
reflection-proof layer; etching the reflection-proof layer, the
poly-silicon layer, and the oxide layer by using the mask pattern
as an etching mask, thereby exposing the expected substrate recess
area; performing a first etching on the expected substrate recess
area, thereby forming a bowed first groove; eliminating the mask
pattern and the reflection-proof layer; performing a second etching
on a substrate portion at a bottom of the first groove by using the
etched poly-silicon layer as an etching mask, thereby forming a
second groove having a vertical side profile; eliminating the
poly-silicon layer and the oxide layer; and forming a gate on the
first groove including the second groove.
[0012] It is preferred that, the first etching is performed by
using a mixture solution in which HF, NH.sub.4F, HNO.sub.3,
CH.sub.3COOH, H.sub.2O.sub.2 and H.sub.2O are mixed. The mixture
solution may contain 1.about.50% of CH.sub.3COOH solution. Also,
the mixture solution may contain 1.about.50% of HNO.sub.3 solution.
It is also preferred that the first etching is performed at a
temperature between 25 and 100.degree. C. in order to improve an
etching reactivity.
[0013] The first groove is formed to have a depth of 10.about.1000
.ANG..
[0014] Preferably, the second dry etching is performed by using a
gas containing groups of HBr, N.sub.2, Ar, Ne and Cl. Moreover, the
second dry etching is a plasma dry etching in which the etching
surface of the first groove is damaged, thereby breaking the
crystal lattice on the etching surface.
[0015] The plasma dry etching is performed at a temperature between
25.degree. C. and 700.degree. C., at a pressure between
0.1.about.100 Torr, by a power between 10 and 2000 Watt, and under
a reducing atmosphere. Further, in the plasma dry etching, one
selected from the group consisting of Ne, He, NH.sub.3, Kr, Xe and
Rn is added as a catalyst gas.
[0016] The second groove is formed to have a depth of
300.about.3000 .ANG..
[0017] In accordance with another aspect of the present invention,
there is provided a method of manufacturing a semiconductor device,
the method comprising the steps of: preparing a semiconductor
substrate on which an isolation layer defining an active area is
formed; forming an insulation layer on the semiconductor substrate;
forming a mask pattern defining an expected substrate recess area
on the insulation layer; etching the insulation layer by using the
mask pattern as an etching mask, thereby exposing the expected
substrate recess area; performing a first isotropic etching on the
expected substrate recess area, thereby forming a first groove;
performing a second dry etching on a substrate portion at a bottom
of the first groove, thereby forming a second groove; and forming a
gate on the first groove including the second groove.
[0018] It is preferred that the first isotropic etching is
performed by using a mixture solution in which HF, NH.sub.4F,
HNO.sub.3, CH.sub.3COOH, H.sub.2O.sub.2 and H.sub.2O are mixed. The
mixture solution may contain 1.about.50% of CH.sub.3COOH solution.
Also, the mixture solution may contain 1.about.50% of HNO.sub.3
solution.
[0019] It is also preferred that the second dry etching is
performed by using a gas containing groups of HBr, N.sub.2, Ar, Ne
and Cl. Moreover, the second dry etching may be a plasma dry
etching in which the etching surface of the first groove is
damaged, thereby breaking the crystal lattice on the etching
surface.
[0020] The plasma dry etching is performed at a temperature between
25.degree. C. and 700.degree. C., at a pressure between
0.1.about.100 Torr, by a power between 10 and 2000 Watt, and under
a reducing atmosphere. Moreover, in the plasma dry etching, one
selected from the group consisting of Ne, He, NH.sub.3, Kr, Xe and
Rn is added as a catalyst gas.
BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects, features and advantages of the
present invention will be more apparent from the following detailed
description taken in conjunction with the accompanying drawings, in
which:
[0022] FIGS. 1A through 1E are sectional views for illustrating a
method of manufacturing a semiconductor device according to an
embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0023] Hereinafter, a preferred embodiment of the present invention
will be described with reference to the accompanying drawings.
[0024] FIGS. 1A-1E are cross-sectional views for illustrating a
method of manufacturing a semiconductor device according to an
embodiment of the present invention.
[0025] Referring to FIG. 1A, an active area defined by two portions
of isolation layer 2 is formed in a semiconductor substrate 1.
Then, an oxide layer 3 and a poly-silicon layer 4 are sequentially
formed on the active area and the portions of the isolation layer 2
in the semiconductor substrate 1. Thereafter, a reflection-proof
layer 5 is formed on the poly-silicon layer 4, and a mask pattern 6
is formed on the reflection-proof layer 5 to define the areas that
are to be recessed (or etched) into the substrate 1.
[0026] In the present embodiment, a poly-silicon layer 4 is used as
a hard mask for forming recesses in the substrate 1. However, it is
possible to use an insulation layer such as a nitride layer
instead.
[0027] Referring to FIG. 1B, the reflection-proof layer 5, the
poly-silicon layer 4, and the oxide layer 3 are sequentially etched
by using the mask pattern 6 as an etching mask, thereby exposing
the areas that are expected to be recessed in the active area of
the substrate 1.
[0028] Referring to FIG. 1C, the exposed substrate area is etched
through a first isotropic wet etching by using the mask pattern 6
as an etching mask, thereby forming a first recess 7 in the
substrate 1. As shown in FIG. 1C, the bottom surface shape of the
first recess 7 may be round or bowed shape; however, a sharp corner
shape or other shapes are also possible. The first recess 7 is
formed to have a depth of 10.about.1000 .ANG. measured from the
surface of the substrate 1. Thereafter, the recess gate mask
pattern 6 and the reflection-proof layer 5 are removed.
[0029] The first isotropic wet etching is performed by using a
solution in which HF, NH.sub.4F, HNO.sub.3, CH.sub.3COOH,
H.sub.2O.sub.2, and H.sub.2O are mixed. In order to improve the
etching reactivity, the etching is performed at a temperature
between 25.degree. C. and 100.degree. C. In the etching solution,
CH.sub.3COOH is used as a stabilizer. Also, the etching solution
contains an amount of CH.sub.3COOH solution, which corresponds to
1.about.50% of the entire solution. Further, HNO.sub.3 is used as a
chemical complement when CH.sub.3COOH is exhausted through
reaction. Therefore, the etching solution contains an amount of
HNO.sub.3 solution, which corresponds to 1.about.50% of the entire
solution.
[0030] Referring to FIG. 1D, a portion at the bottom surface of the
first recess 7 is further etched through a second dry etching,
thereby forming a second recess 8 having a narrower width than the
first recess 7. The second recess 8 is formed to have a depth of
300.about.3000 .ANG. measured from the surface of the substrate 1.
Thereafter, the poly-silicon layer 4 and the oxide layer 3 are
removed The second dry etching is performed by using gas containing
HBr, N.sub.2, Ar, Ne, and Cl.
[0031] In addition, for the second dry etching, a plasma dry
etching is performed to damage the etching surface of the first
groove 7 and break the crystal lattice on the etching surface. The
plasma dry etching is performed at a temperature between 25.degree.
C. and 700.degree. C., at a pressure between 0.1.about.100 Torr, by
a power between 10 and 2000 Watts, and under a reducing atmosphere.
Also, in the plasma dry etching, one selected from the group
consisting of Ne, He, NH.sub.3, Kr, Xe and Rn is added as a
catalyst gas.
[0032] Referring to FIG. 1E, a gate oxide layer 9 is formed on the
active area of the substrate 1 including the second recess 8 and
the first recess 7. Then, a gate poly-silicon layer 10, a gate
metal silicide layer 11, and a gate hard mask layer 12 are
sequentially formed on the gate oxide layer 9.
[0033] Thereafter, the gate hard mask layer 12 is etched into a
pattern, and the etched gate hard mask layer 12 is used to etch the
gate metal silicide layer 11, the gate poly-silicon layer 10, and
the gate oxide layer 9 under the gate hard mask layer 12, thereby
forming a recess gate 13 (as shown in FIG. 1E) in the first and
second recesses 7, 8.
[0034] Thereafter, although not shown, a series of known processing
steps are sequentially performed, so as to complete the
manufacturing of a semiconductor device having the recess gate 13
according to an embodiment of the present invention.
[0035] In a semiconductor device having a recess gate (such as 13)
manufactured in the process according to an embodiment of the
present invention as described above, the active area of the
substrate (such as 1) is recessed through two steps of etching.
Therefore, the semiconductor device of the present invention has an
increased channel length when compared to the conventional
semiconductor device having a recess gate formed through a single
etching.
[0036] Therefore, according to the present invention, it is
possible to secure a sufficient channel length by twice-etching the
substrate active area on which a gate (such as 13) is expected to
be formed, even when the active area is reduced. Therefore, the
present invention can effectively reduce the current leakage of the
junction area and improve the refresh characteristics. Therefore,
the present invention can improve the reliability and yield of
semiconductor devices through the reduction of current leakage and
the improvement of the refresh characteristics.
[0037] Although a preferred embodiment of the present invention has
been described for illustrative purposes, those skilled in the art
will appreciate that various modifications, additions and
substitutions are possible, without departing from the scope and
spirit of the invention as disclosed in the accompanying
claims.
* * * * *